JPS63205582A - Lsi testing circuit - Google Patents

Abstract

PURPOSE:To select an optional asynchronous circuit block by providing a 2nd switch circuit which selects an enable-circuit from a shift register when a mode control signal supplied to a 1st switch circuit selects an (a) terminals side or holds an enable-state when it selects a (b) terminal side. CONSTITUTION:The clock signal of the (b) terminal side of the circuit 1 is inputted to the terminal C of an asynchronous circuit block 2 and propagated by using the mode control signal the 1st switch circuit 1 and the output of a 2nd switch circuit 5 is all fixed in the enable-state, thereby performing normal operation. The enable data input is stored in the shift register 4 right before the input terminal for a test clock is switched from the (b) terminal of the circuit 1 to the (a) terminal by using the mode control signal to the circuit 1, and consequently the optional block 2 is put in operation to input the output signal of the block 2 to an added circuit 3, whose operation is tested. Thus, an optional asynchronous circuit can be selected.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is an LS for testing the operation of internal circuits of an LSI.
This relates to an I test circuit.

[Conventional technology]

Figure 2 shows, for example, Nikkei Electronics 1979゜4.
This is an LSI test circuit diagram for testing sequential circuits that adopts the conventional scan method shown in No. 16.The aim of this scan method is to be able to access all 7 lip-flops in the LSI chip from the pins (terminals). The circuit configuration is as follows.

In the figure, 1 is a switch circuit that switches between test scan data input to the a terminal and normal data input to the b terminal using a mode control signal, and 6 is a switch circuit that is switched by the switch circuit 1. The flip-flop 70, which holds the stored data using a clock signal, is a combinational circuit other than a sequential circuit that exchanges signals with the flip-flop 6.

Next, the operation will be explained. First, in the normal operation of a sequential circuit that adopts this scan method, the switch circuit 1
A mode control signal 11 to this switch circuit 1 is provided.
The data given to the b terminal side using 7 lip-flop 6
Normal operation is accomplished by propagating the signal to Also, during testing, by using the mode control signal %0 of the switch circuit 1 to propagate the data on the a terminal side to the 7 flip-flops 6, all the flip-flops 6 function as shift registers, and from the scan data input. The test data is set in each of the 7 lip-flops 6 and the combinational circuit T
Perform the test.

[Problem that the invention seeks to solve]

Since conventional LSI test circuits are configured as described above, a synchronous circuit synchronized with a clock signal must be used even during normal operation, and when a synchronous circuit is used, power consumption during operation is reduced. There was also the problem that the number of LSI internal elements also increased.

This invention was made to solve the above-mentioned problems, and even if an asynchronous circuit section exists, it is possible to test an LSI circuit without changing it to a synchronous circuit, and it also allows one test terminal to be used. The purpose is to obtain an LSI test circuit that requires less.

[Means for solving problems]

In the LSI test circuit according to the present invention, the asynchronous circuit is divided into blocks, an enable human power E for operation control is provided for each block, and a (first) switch circuit switches between the normal operation clock and the test clock for each block. In addition to providing a shift register for distributing control data for each block.

[For production]

The shift register for distributing control data for each block of the LSI test circuit according to the present invention makes it possible to select any rounded asynchronous circuit block to be tested, especially when serial data is converted into parallel data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In the diagram, the same parts as in FIG. 2 are designated by the same symbols, and in the critical condition diagram, 2 is an asynchronous circuit operated by the clock signal switched by the (first) switch circuit 1. 3 is an auxiliary circuit that exchanges signals with the asynchronous circuit block 2; 4 is a shift register that operates only when the mode control signal selects the b side of the (first) switch circuit 1; 5; selects the enable signal from the shift register 4 when the mode control signal selects the a terminal side of the (first) switch circuit 1, and enters the enable state when the mode control signal selects the b terminal side (the second ) is a switch circuit.

Next, the operation will be explained. First, using the mode control signal to the (first) switch circuit 1, the clock signal on the b terminal side of the (first) switch circuit 1 is input to the terminal C of the asynchronous circuit block 2 and propagated, and simultaneously K If all outputs of the (second) switch circuit 5 are fixed in the enabled state, normal operation is performed from K. Also, just before switching the test clock input terminal from the b terminal to the a terminal of the (first) switch circuit 1 using the mode control signal to the (first) switch circuit 1, enable data is input to the shift register 4. By storing , any asynchronous circuit block 2 is operated, and the output signal of the asynchronous circuit clock 2 is inputted to the associated circuit 3 to test the operation of the associated circuit 3.

Note that in the above embodiment, the mode control input is given to the shift register 4.jl) A circuit example is shown in which the number of external terminals of the LSI is reduced; however, if there is enough external terminals, the output of the shift register 4 A latch circuit may be provided in the latching circuit so that the latch signal is controlled by an external terminal, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, when testing an LSI circuit including an asynchronous circuit block, the LSI test circuit is configured without changing the asynchronous circuit block to a synchronous circuit, so that the LSI test circuit can be configured as a synchronous circuit operated by a clock. There is an effect that an LSI circuit can be obtained without increasing power consumption and with suppressed increase in the number of elements for testing.

[Brief explanation of the drawing]

FIG. 1 is an LSI test circuit diagram according to an embodiment of the present invention, and FIG. 2 is a conventional LSI test circuit diagram. In the figure, 1 is a (first) switch circuit, 2 is an asynchronous circuit block, 3 is an auxiliary circuit, 4 is a shift register, and 5
is the (second) switch circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An asynchronous circuit block in which the asynchronous circuit of the LSI circuit is divided into blocks and an enable input for operation control is provided for each block, a shift register that distributes enable data to each asynchronous circuit block, and a normal operation for each asynchronous block in the first half. a first switch circuit that switches between a clock and a test clock, and an enable signal from the shift register when the mode control signal applied to the first switch circuit selects the a terminal side of the first switch circuit; and a second switch circuit that maintains an enabled state when selecting the b terminal side.