JPS63204984A - Signal conversion processing circuit - Google Patents

Abstract

PURPOSE:To make the timing design of the switching of a switch circuit easy by constituting a circuit so as to supply a clock signal to an A/D and a D/A converters through the first and the second 35 buffers for a clock. CONSTITUTION:Plural digital signal processing circuits 5, 6 are connected, in parallel, between the A/D converter 3 and the D/A converter 4, which are single respectively, and between the output terminals of the respective digital signal processing circuits 5, 6 and the D/A converter 40, the three state buffers (3S buffers) 7, 8 for a data, which a control signal from a controller 3 is connected to, are inserted respectively. Even in the case when the digital signal processing circuits of more than three number are installed in parallel, because the output terminals of the 3S buffers, connected to the respective digital signal processing circuits, can be connected to the A/D converter 4 and the D/A converter 40, which are single respectively, simply through a wire-lead-OR connection, the timing design is easy.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is based on a digital signal processing circuit such as a video memory and a controller that controls the same, converts an analog signal into a digital signal, and then processes the signal. This relates to a signal conversion processing circuit that performs signal processing and converts the signal-processed data into an analog signal and outputs the signal.

(Prior Art) In recent years, in signal recording and reproducing devices such as audio recorders and video tape recorders (VTRs), digital signal processing has been performed on reproduced signals or recorded signals. In this case, the reproduced video signal is converted into a digital signal and once written into the video memory, and then the stored data is read out under continuous readout control by the controller, thereby improving image quality during special reproduction.

FIG. 3 shows an example of the configuration of a conventional signal conversion processing circuit in which such digital signal processing circuits are arranged in a plurality of columns.

The analog signal A0 supplied from the input terminal (9) is sent to the first and second signal processing systems (11
) (21) and processed by either signal processing system, the signal A1 or A2 is outputted from the output terminal (91) through a switching circuit (90) such as an analog switch.

The first and second signal processing systems (11) (21) include A/D converters (41) (42), digital signal processing circuits (5) (
6), a controller (3) that controls the D/A converter (43) (44), and the digital signal processing circuit (5) (6).
Equipped with controllers (31) and (32), respectively.
2) supplies the first clock signal CK to the A/D converters (41) and (42). CK + ', and the D/A converter (
43) Second clock signal CK2, CK z to (44)
' are supplied respectively.

By appropriately switching the switching circuit (90) using, for example, a control signal from a system controller (not shown), a desired analog signal processed by the first or second signal processing system can be obtained from the output terminal (91). It will be done.

(Problem to be solved) However, in conventional circuits, each signal processing system has an A/
A D converter and a D/A converter are required, and as the number of signal processing systems increases, the configuration of the switching circuit (90) has to become complicated, which makes the overall circuit configuration extremely complicated. There was a problem.

Furthermore, especially in a circuit that requires high-speed signal processing, it becomes difficult to design the timing for switching the switching circuit (90).

(Means for Solving Problems) An object of the present invention is that even when a circuit is equipped with a large number of signal processing systems, each signal processing system is equipped with a single A/D converter and a single D/A converter. To provide a signal conversion processing circuit that can share a converter and does not require a switching circuit such as an analog switch.

The processing circuits according to the present invention each include a single A/D converter (3
), the D/A2 PA device (4), and a plurality of digital signal processing circuits (5)<6) are connected in parallel. The output terminal of each digital signal processing circuit (5) (6) and D
/A converter (40), 3-state buffers (hereinafter referred to as 3S buffers) (7) and (8) for data are connected to control signals from the controller (3), respectively. .

In addition, the controller (3) or each digital signal processing circuit (
5) The clock signal obtained from (6) is transmitted through the first clock signal 3S buffer (71) (81) and the second clock signal 3S buffer (72) to which the control signal from the controller (3) is connected. 82), respectively A/D
It is supplied to a converter (4) and a D/A converter (40).

(Function) A predetermined digital signal processing circuit is set to an operating state by a control signal from the controller (3) (hereinafter, this circuit is referred to as an operation processing circuit), and the data connected to the output terminal of the operation processing circuit is set to an operating state. Only the data 3S buffer is activated, and the other data 3S buffers are kept inactive. At the same time, a first clock 3S buffer and a second clock 3S buffer are connected to the clock signal input/output terminal of the operation processing circuit or the controller (3) corresponding to the circuit.
Only the buffer is activated, and the other clock 3S buffers are kept inactive. As a result, the first and second clock signals with a period corresponding to the operation of the operation processing circuit are
After passing through the first and second clock 3S buffers, A
/D converter (4) and D/A converter (40), respectively.

This allows the A/D converter (4) and the D/A converter (
40) is operated, and the digital signal D0 output from the A/D converter (4) is subjected to predetermined signal processing in an operation processing circuit controlled by the controller (3). The processed digital signal is input to the D/A converter (40) via the activated 3S buffer for data, converted into an analog signal, and output.

When switching to signal processing by another digital signal processing circuit, the controller (3) sends a control signal to the digital signal processing circuit that becomes the operation processing circuit, and also sends a control signal to the 3S buffer for data and the 3S for the first and second clocks. The activated 3S buffer is changed by switching the level of the control signal sent to each buffer. At this time, activation and deactivation of each of the 38 buffers is switched by the control signal H","
This is done at an appropriate timing by switching the level of "L".

(Effects of the Invention) According to the signal conversion processing circuit according to the present invention, when a large number of digital signal processing circuits are installed in parallel, the output end of each 3S buffer for data is connected to the D/A converter (40). and the output terminals of the first and second clock 3S buffers are connected to the A/D converter (4) and the D/A converter (4).
They can be directly connected to the clock input terminals of 0) by wire-OR connection to each other, and a single A/D converter and D/A converter can be shared by multiple digital signal processing circuits, making it easy to switch analog switches, etc. No circuit equipment is required. Therefore, the circuit configuration is greatly simplified compared to the conventional one.

In addition, with the 3S buffer for data and 3S buffer for clock, the switching of the digital signal processing circuit that should be set to the operating state is performed under digital control. This is much easier than the conventional circuit using the switching circuit (90).

(Example) FIG. 1 shows an example of a signal processing circuit according to the present invention,
first and second signal processing systems (
102).

Between the A/D converter (4) and the D/A converter (40),
Equipped with a pair of digital signal processing circuits (5) (6) in parallel, and the data output terminals of each digital signal processing circuit (5) (6”) are connected to 3S buffers (7) and (8) for data, respectively. The output ends of each buffer (7) (8) are wired OR-connected to each other and connected to the data input end of the D/A converter (40).Each of the 38 buffers (7) (8) is ), one of the 38 buffers is activated by the control signal a sent from the buffer.

Further, the digital signal processing circuit (5) generates a first clock signal CK and a second clock signal CK2 having a period corresponding to the circuit operation, and the digital signal processing circuit (6) generates a first clock signal CK and a second clock signal CK2 having a period corresponding to the circuit operation. A first clock signal CK,' and a second clock signal CK,' are generated with the same period. First clock signals CK and C of each digital signal processing circuit <5) (6)
The output terminals of K and ' are connected to each other by wire OR after passing through the first clock 3S buffer (71) (81), respectively.
Connect to the clock signal input terminal of the A/D converter <4). On the other hand, the output ends of the second clock signals CK2 and CK2' are respectively connected to the second clock 3S buffer (72).
After passing through (82), wired OR connection is made to each other, and D
Connect to the clock signal input terminal of the /A converter (40).

The 3S buffers (71) (81) and (
72) In (82), a pair of 38 buffers connected to one of the digital signal processing circuits is activated by the control signal a from the controller (3).

As the 3S buffer, for example, LS367 manufactured by Texas Instruments can be used.

Figures 2 (a) to (e) show the control signal a before and after switching the circuit in Figure 1, which is supplied from the digital signal processing circuit (5) to the D/A converter (40). clock signal CK2, output data D1 of the digital signal processing circuit (5), D/A from the digital signal processing circuit (6)
It shows changes in the clock signal CK2' supplied to the converter (40) and the output data D2 of the digital signal processing circuit (6).

That is, when the control signal a is set to the "H" level, the 3S buffer (7) for data and the 3S buffer (7) for the first clock
S buffer (71) and 3S buffer for second clock (
72) is activated, and the A/D converter (4) and the D/A
The converter (40) operates by being supplied with clock signals CK and CK2, and data D processed by the digital signal processing circuit (5) is converted into an analog signal A1 via the D/A converter (40). It is converted and output from the output terminal (91).

When the control signal a is switched to the "L" level, the 3S buffer for data (8), the 3S buffer for the first clock (81), and the 3S buffer for the second clock (82) are activated, and A/D conversion is performed. device (4) and D/A converter (40
) is operated by being supplied with tarok signals CK1' and CK,', and the data D2 processed by the digital signal processing circuit (6) is converted into an analog signal A2 via the D/A converter (40), and is output. It is output from the terminal (91).

The above operation is performed under digital control, and as shown in FIG. 2, the clock signals are switched at appropriate timings.

According to the above signal conversion processing circuit, even when three or more digital signal processing circuits are installed in parallel, the output ends of the 3S buffers connected to each digital signal processing circuit are simply wired OR connected, and each digital signal processing circuit can be connected to a single A,/D converter (4)
Since it can be connected to the D/A converter (40), the circuit configuration is simpler than conventional ones, and the timing design is also easier.

It should be noted that the configuration of each part of the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made within the technical scope of the claims.

For example, clock signals to the A/D converter and D/A converter can also be generated by the controller (3).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal conversion processing circuit according to the present invention,
Figure 2 is a timing chart showing the operation of the circuit, and Figure 3 is a timing chart showing the operation of the circuit.
The figure shows a block diagram of a conventional circuit.

Claims (1)

[Claims] [1] A plurality of digital signal processing circuits (5) and (6) controlled by a controller, and an A/D converter and a D/A connected to the input terminal and output terminal of the digital signal processing circuit.
In a signal conversion processing circuit that selectively outputs a signal processed through a predetermined digital signal processing circuit, the signal conversion processing circuit is composed of a single A/D converter (3) and a single D/A converter. multiple digital signal processing circuits (5) between the
(6) in parallel, each digital signal processing circuit (5)
Between the output terminal of (6) and the D/A converter (40), 3-state data buffers (7) and (8) each connected to a control signal from the controller (3) are interposed, Controller (3) or each digital signal processing circuit (5) (6
) The clock signal obtained from the controller (3) connects the first clock 3-state buffer (71) (81) and the second clock 3-state buffer (72) (82) to which the control signal from the controller (3) is connected. A signal conversion processing circuit characterized in that the signal is supplied to an A/D converter (4) and a D/A converter (40), respectively, via the signal converter.