JPS63201835A - Interruption control method - Google Patents

Abstract

PURPOSE:To obtain a distributed multiprocessor system which can be coped with various types of applications by transferring and recognizing a handler selection code between an interrupter and an interruption handler in an interruption control sequence. CONSTITUTION:The interrupter 12 detects the 'LOW' of an interruption acknowledge daisy chain line IACK*. After the code of the low order 3 bit of an address line AX coincides with the priority level of an interruption request which said interrupter drives to 'Low' and the 'Low' of a data strobe signal DSO is recognized, the status/ID byte of 8 bits is outputted on a data bus DX. Thereby, the interruption handler 11 reads the status/ID byte from the data bus and opens a reading data transfer bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an interrupt control method in a system including a plurality of processors having the function of accepting and servicing interrupts.

[Prior Art] A conventional general configuration of a system that performs interrupt control using an interrupter and an interrupt handler is shown in FIG. Interrupt handler 1
constantly monitors the interrupt request lines IRQX from multiple interrupters 2 and 3, and when an interrupt is detected, determines the priority and notifies the processor of the level. When it becomes possible to start
After generating an interrupt acknowledge cycle and gaining control of the data transfer bus, it actually issues an interrupt request of the priority level currently being accepted by the processor using the IACK” stage chain line. Requests the interrupter that is currently running to send the status/ID.

Furthermore, when the interrupt handler reads the status/ID sent on the data transfer bus by the interrupter that meets the above conditions, it transfers this status/ID to the processor. The processor thus begins an interrupt servicing sequence.

In the case of a system with multiple interrupt handlers, such as a multiprocessor system, there is no problem as long as the interrupt request lines monitored by each interrupt handler do not overlap, but if two If either the interrupt handlers 4, 5 or both are monitoring interrupt request lines of the same priority level, from another point of view, the two interrupt handlers 4, 5, depending on whether one interrupt handler 6 or 7 or both When requesting an interrupt to any one of them at the priority level, in the conventional interrupt control sequence described above, since the two interconnected Pandora 4 and 5 both perform an interrupt acknowledge cycle, two interrupts are required in total. An acknowledge cycle will occur, resulting in malfunction.

Therefore, the interrupt priority levels for monitoring (accepting requests) for multiple interrupt handlers must be set so that they do not conflict with each other, which is a major limitation on the configuration of interrupt control in distributed multiprocessor systems. ing.

[Objective] The present invention provides functions for accepting interrupt requests of the same priority level and providing services by multiple interrupt handlers, which could not be achieved with conventional interrupt control methods using interrupters and interrupt handlers. This makes it possible to

[Example] Figure 1 shows an interrupter and an interrupt/interrupter in the present invention.
It shows the main signals between handlers. 11 in the diagram
Interrupted Pandora 12 is an interrupter.

The interrupt control sequence by the interrupter 12 and interrupt handler 11 in this configuration will be described. The interrupter 12 requests an interrupt by setting IRQX to Low. Interrupt handler 1
1 detects “Low” of “IRQX”, it requests control of the data transfer bus. If this request is granted, the interrupt handler 11 transfers the address line A
Outputs a 3-bit code to the lower 3 trees of X indicating that it is currently acknowledging the interrupt request "IRQX",
At the same time, IACK” and data strobe signal DS
+' to 'Low'.

The interrupter 12 detects ``Low'' on the interrupt acknowledge chain line IACK'', and the code of the lower 3 bits of the address line AX is
Matches the priority level of the interrupt request that this interrupter is driving “Low” and the data
After confirming that the strobe signal DSI is low, it outputs an 8-bit handler selection code onto the data bus DX.

The interrupt handler 11 reads the handler selection code from the data bus and releases the data transfer bus.

After confirming that the handler selection code matches its own handler number, the interrupt handler 11 notifies the processor of the interrupt. The sequence from this point on is the same as in the traditional method; once the processor is ready to start the interrupt servicing sequence,
Pandora 11 requests control of the data transfer bus again. If this request is granted, interrupt handler 1
1 is the current IRQX on the lower three address lines AX.”
3bi indicating that the interrupt request is acknowledged.
t code and simultaneously drives IACK' and data strobe signal DSO'' to l Low 11.

Interrupter 12 detects I Low 11 on interrupt acknowledge chain line IACK',
After confirming that the code of the lower 3 bits of the address line AX matches the priority level of the interrupt request being driven by this interrupter to "1, OW" and that the data strobe signal DSO is "Low", Outputs an 8-bit status/ID byte on the data hash DX.

Interwoven Pandora 11 reads the status/ID byte from the data bus and releases the data transfer bus. Interrupt handler 11 has this status/I
Transfer D bytes to processor. This begins the desired interrupt service sequence.

When the interrupt handler 11 does not match the handler selection code transferred from the interrupter 2 with its own Pandora number, it ignores the interrupt request currently being driven to "Low" and does not notify the processor. In this case, the stator/ID byte will be transferred to or from another interrupt handler or interrupter 12.

[Effect] As explained above, by adding a sequence to the interrupt control sequence to transfer and confirm the handler selection code between the interrupter and the interrupt handler,
It becomes possible to configure a system with multiple interrupter handlers that monitor interrupt request lines with the same priority level, and it becomes possible to construct a distributed multiprocessor system that can support a wider variety of applications.

[Brief explanation of the drawing]

Figure 1 shows the interrupter and interrupt
Figure 2 is a diagram showing the main signals between handlers. Figure 2 is a general configuration diagram of a system using interrupters and interrupt handlers. Figure 3 is a diagram showing the main signals between two interrupt handlers. 11 is an interrupt handler, and 12 is an interrupter.

Claims (1)

[Claims] Interrupt request, transmission of status/ID during interrupt acknowledge cycle, interrupt acknowledge data chain line control function, determination of priority of interrupt request from the interrupter, generation of interrupt acknowledge cycle, and , in a system that performs interrupt control using an interrupt handler that has functions of reading status/ID sent by the interrupter during an interrupt acknowledge cycle, an interrupt request issued by each interrupter is sent to multiple interrupt handlers. , between an interrupter and multiple interrupt handlers before the status/ID transfer in the interrupt acknowledge cycle when the interrupter is input to the same priority level. 1. An interrupt control method characterized by transferring and confirming a selection code for selecting an interrupt handler that is currently the target of the interrupt request.