JPS63201576A - Waveform formatter - Google Patents

Abstract

PURPOSE:To test the minimum operation period of an ultra-high speed logical integrated circuit by generating two clock pulses continuously in the minimum test period of an LSI tester. CONSTITUTION:When pattern data P has a logical value '1', a timing signal A or C is inputted to the set input S of an S-R flip-flop F and a timing signal B or D is inputted to the reset input R. A waveform inverted signal I has a logical valve '0' or '1' according to whether the polarity of a desired clock pulse O is plus or minus. Consequently, two clock pulses are outputted as an output O according to whether or not in a test cycle where the pattern data has a logical valve '1'. Those clock pulses for testing are supplied as a test signal to the logical integrated circuit to be tested to conduct a minimum clock cycle test.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application) The present invention relates to a waveform formatter for an ultra-high-speed logic integrated circuit tester, and more particularly to a waveform formatter circuit for generating logic signals for AC testing.

(Prior art) Conventionally, logic integrated circuit testing machines (hereinafter referred to as LSI testers)
For the waveform formatter, Non Return to
Zero (NRZ) waveform, Return to
Zero (RZ) waveform and Exclusive OR
Equipped with a waveform formatter that generates three types of (EOR) waveforms, AC tests are performed by selecting the desired format and applying it to one integrated circuit under test (DU). .

The format of each of the above waveforms is shown in FIG. 3, and each waveform is generated by combining pattern data and any one of clocks A, B, and C. First, the NRZ waveform is formed by a combination of pattern data and clock A. The RZ waveform is an RZ two-level waveform formed by a combination of pattern data and clocks B and C. In addition, the EOR waveform is
Set the pattern data to logical value “1” and clocks B and C.
The NRZ waveform is generated by EORing the RZ two-level waveform generated in combination with the NRZ waveform and the inverted waveform of the NRZ waveform.

(Problems to be Solved by the Invention) The above-mentioned conventional LSI tester has
The C test is conducted as follows.

A pulse signal having desired pattern data, waveform format and timing is generated by an LSI tester and applied to the input terminal of the DOT.

The pattern data logical value ' is input to the clock input terminal of the DUT.
1'' and apply a waveform with a desired timing, that is, a clock pulse, in the waveform format RZ2 level system.

LS output expected value pattern data and DUT output cover turn data for input cover turn data applied to the DUT.
Compare using the I tester's comparator.

AC tests include input timing tests that test the setup and hold times of input signals with respect to clock pulses, and minimum operating cycle tests that test how far the DUT can operate by shortening the clock cycle. . The former is done by changing the timing of the input signal with respect to the clock pulse, and the latter is done by changing the cycle of the tester clock. However, when the minimum operating cycle of the DUT is smaller than the minimum test cycle of the LSI tester, If it is an ultra-high-speed logic integrated circuit, it cannot be tested with a conventional LSI tester.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the waveform formatter according to the present invention is configured to combine one or more of pattern data and a plurality of timing signals generated in a logic integrated circuit tester. In a waveform formatter that generates a logic signal by combination and supplies the logic signal as a test signal to the logic integrated circuit under test, the combination of the four timing signals generated by the logic integrated circuit tester and the pattern data, The present invention is characterized in that two consecutive pulses are generated within a minimum test period of the logic integrated circuit tester, and these pulses are output as the logic signal.

(Example) The present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of a waveform formatter according to the present invention.
) is a logic block circuit diagram, and (b) of the same figure is a timing diagram.

In FIG. 1(a), A, B, C, and D are timing signals given by a timing generator within the LSI tester. P is pattern data, and when outputting a clock pulse to output 0, a logical value "1" is given, and when not, a logical value "0" is given. F is an S-R flip-flop, and as shown in FIG. 1(a), P has a logic value of "1".
”, the timing signal A or C enters the set input S, and the timing signal B or D enters the reset input R. ■ is a waveform inversion signal, and the polarity of the desired clock pulse 0 is positive. A logical value of "0" or "1" is given depending on whether the value is negative or negative.

As shown in FIG. 1(b), the timing signal A detects the rising edge of the first clock pulse, the timing signal B detects the falling edge of the first clock pulse, and the timing signal C detects the second clock pulse. If the rising edge of the second clock pulse is given as a timing signal, and the falling edge of the second clock pulse is given as a 0, two clock pulses are output in a test cycle in which the pattern data P has a logic value of '1'.

Next, the AC test method according to the first embodiment will be explained. FIG. 2 is a timing chart of various signals when a minimum clock cycle test is performed using the test clock pulses generated by the waveform formatter of FIG. 1.

■Is the DUT the minimum operating cycle? -, in which a is an input signal and b is a clock pulse supplied to the DUT from another circuit in order to operate the DUT at the minimum operating cycle.

If the minimum operating cycle of the LSI tester is greater than ts, testing cannot be performed at the timing (3). Therefore, a test clock signal such as b generated by the waveform formatter of the present invention is applied to an input signal a having a period ta as shown in (1) and (2). As a result, in the case of ■, the period is 0 → 1.2 →
3. Regarding ..., you can take the test at exactly the same timing as ■. In addition, in the case of ■, the period is 1 → 2.3 → 4. Regarding ..., you can take the test at exactly the same timing as ■. C is a strobe pulse, and this stroke pulse causes DU
The T output signal and the expected value can be compared. ■C is cycle 1
,3. ..., and ■C has a cycle of 0.2. ...
It is a signal that can be compared with .

By performing the test at the timings of (2) and (2), the test can be performed in the minimum clock cycle, albeit partially, rather than entirely as in (2). Note that timing signals A, B, and C in FIG.

Since D are independent, the widths of the first pulse and the second pulse of ■b or ■b are not necessarily the same.

(Effects of the Invention) As explained above, the present invention enables the minimum operating cycle test of ultra-high-speed logic integrated circuits to be performed by continuously generating two clock pulses within the minimum test cycle of an LSI tester. The present invention has such effects.

[Brief explanation of the drawing]

FIG. 1(a) is a logic block circuit diagram showing an embodiment of the waveform formatter of the present invention, and FIG. 1(b) is the same as FIG. 1(a).
FIG. 2 is a diagram showing an example of signal timing in a minimum operation cycle test, and FIG. 3 is a signal timing diagram in a conventional waveform formatter. A, B, C, D...timing signal, ■...waveform inversion signal, P...pattern data, F...RS flip-flop, Q...flip-flop output, 0...
Waveform formatter output, T...test cycle clock, ■
a... Input signal of minimum operating cycle, ■b... Clock signal of minimum operating cycle, ■a, ■a... Input signal of minimum operating cycle test, ■b, ■b... Minimum operating cycle Test clock signal, ■C2■C... Strobe pulse.

Claims (1)

[Claims] A waveform formatter that generates a logic signal by combining pattern data generated in a logic integrated circuit tester and one or more of a plurality of timing signals, and supplies the logic signal to the logic integrated circuit under test as a test signal. The combination of the four timing signals generated by the logic integrated circuit tester and the pattern data generates two consecutive pulses within the minimum test cycle of the logic integrated circuit tester, and these pulses are A waveform formatter characterized by outputting as a logical signal.