JPS6320021B2 - - Google Patents
Info
- Publication number
- JPS6320021B2 JPS6320021B2 JP6068682A JP6068682A JPS6320021B2 JP S6320021 B2 JPS6320021 B2 JP S6320021B2 JP 6068682 A JP6068682 A JP 6068682A JP 6068682 A JP6068682 A JP 6068682A JP S6320021 B2 JPS6320021 B2 JP S6320021B2
- Authority
- JP
- Japan
- Prior art keywords
- varistor
- strip
- semiconductor
- shaped
- cutting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 29
- 235000012431 wafers Nutrition 0.000 claims description 14
- 230000002457 bidirectional effect Effects 0.000 claims description 10
- 239000008188 pellet Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【発明の詳細な説明】
本発明はPN接合を有する複数のペレツトを積
層接着したPNペレツト積層体を逆並列接続して
なる双方向性半導体バリスタの製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bidirectional semiconductor varistor in which a PN pellet laminate, in which a plurality of pellets having PN junctions are laminated and bonded, is connected in antiparallel.
一般に電気回路に入来するサージを抑制した
り、或いはその電気回路が発生するサージ電圧を
吸収するのにバリスタが用いられる。斯かるバリ
スタとしてダイオードの順方向特性を利用して双
方向のサージ電圧を吸収すべく、PN接合を有す
る複数のペレツトを積層したものを逆並列に接続
してなる双方向性半導体バリスタがある。 Varistors are generally used to suppress surges entering an electrical circuit or to absorb surge voltages generated by the electrical circuit. As such a varistor, there is a bidirectional semiconductor varistor made by stacking a plurality of pellets having a PN junction and connecting them in antiparallel in order to absorb bidirectional surge voltage by utilizing the forward characteristics of a diode.
従来の斯かるバリスタの製造方法は、PN接合
を有する大面積の半導体ウエハを鑞材を介して所
望枚数積層して接着させた後、Ｘ、Ｙ方向に所定
の寸法で切断して多数のPNペレツト積層体に分
割し、第１図に示す様にこれらPNペレツト積層
体Ｐの２個を互いに逆方向になる様に電極Ｅ，
E′間に鑞材Ｓと一緒に配置すると共に加熱して前
記PNペレツト積層体Ｐを電極Ｅ，E′に鑞付けし
ていた。この様に従来の製造方法は個々に切断さ
れたPN半導体ペレツト積層体２個を逆並列にし
て組立てているので、工数が非常にかかり、且つ
PN半導体ペレツト積層体が非常に小さいために
組立て時に互いに逆方向にするところを互いに同
方向に組立ててしまう間違いが生じ易く、歩留り
を著しく低下させるという欠点があつた。 The conventional manufacturing method for such varistors is to stack and bond a desired number of large-area semiconductor wafers with PN junctions through a soldering material, and then cut them into predetermined dimensions in the X and Y directions to form a large number of PN junctions. As shown in FIG. 1, two of these PN pellet stacks P are connected to electrodes E and P in opposite directions.
The PN pellet stack P was soldered to the electrodes E and E' by placing it together with a solder material S between E' and heating it. In this way, the conventional manufacturing method involves assembling two individually cut PN semiconductor pellet stacks in antiparallel, which requires a large number of man-hours.
Since the PN semiconductor pellet stack is very small, it is easy to make a mistake in assembling the PN semiconductor pellets in the same direction instead of in opposite directions, which has the disadvantage of significantly lowering the yield.
本発明は斯かる従来方法による欠点を除去する
ことを目的とし、PN接合を有する大面積の半導
体ウエハを複数枚積層接着してなるPN半導体ウ
エハ積層体を所定幅にて一方向に切断して複数の
短冊状積層体を得、これら短冊状積層体の少くと
も２個を逆方向にして電極板間に並置して鑞付け
し、しかる後に所定幅毎に個々に切断することを
特徴としている。 The present invention aims to eliminate the drawbacks of such conventional methods, and involves cutting a PN semiconductor wafer stack in a predetermined width in one direction, which is made by laminating and bonding a plurality of large-area semiconductor wafers having PN junctions. The method is characterized in that a plurality of strip-shaped laminates are obtained, at least two of these strip-shaped laminates are placed in opposite directions and brazed in parallel between electrode plates, and then cut into individual strips of each predetermined width. .
第１図及び第２図Ａ〜Ｇにより本発明に係る双
方向性半導体バリスタの製造方法の一実施例を説
明する。 An embodiment of the method for manufacturing a bidirectional semiconductor varistor according to the present invention will be described with reference to FIG. 1 and FIGS. 2A to 2G.
先ず第２図Ａに示す様なPN接合を有する大面
積の半導体ウエハ１を所望枚数、ここでは４枚用
意し、これら半導体ウエハを鑞材（図示せず）を
介して同方向に積層した後に加熱して互いに接着
させることにより、同図Ｂに示す様なPN半導体
ウエハ積層体２を得ている。次に後の工程におい
て電極板を鑞接するために、半導体ウエハ積層体
２の全面に通常のメツキ方法によりメツキを施
す。しかる後同図Ｃに示す様にカツテイングマシ
ーンにより半導体ウエハ積層体２を所定の幅にて
同一方向に切断する。この結果、同図Ｄに示す様
な一方に細長い短冊状積層体３が多数個得られ
る。 First, a desired number of large-area semiconductor wafers 1 having PN junctions as shown in FIG. By heating and bonding them together, a PN semiconductor wafer stack 2 as shown in Figure B is obtained. Next, in order to solder electrode plates in a later step, the entire surface of the semiconductor wafer stack 2 is plated using a conventional plating method. Thereafter, the semiconductor wafer stack 2 is cut into a predetermined width in the same direction using a cutting machine as shown in FIG. As a result, a large number of elongated strip-shaped laminates 3 are obtained on one side as shown in FIG.
次に同図Ｄに示す様にほぼ同じ長さの短冊状積
層体３を２個ニツケル板或いはコバール板の様な
細長い金属板４，４′間に、互いに逆方向、つま
り逆並列になる様に並置する。この半導体バイリ
スタにあつてはダイオードの順方向を利用してい
るので、２個の短冊状積層体３，３を接触させて
並置しても、或いは若干間隔を設けて並置しても
電圧−電流特性に悪影響を及ぼすことはない。な
おこの際、短冊状積層体３，３と電極板４，４′
間には半田の様な細長い鑞材が介在されており
（図示せず）、従つてこれらを所定温度で加熱する
ことにより短冊状積層体３，３と金属板４，４′
とが鑞付けされ、短冊状バリスタ５となる。 Next, as shown in FIG. D, two strip-shaped laminates 3 of approximately the same length are placed between elongated metal plates 4, 4' such as nickel plates or Kovar plates so that they are in opposite directions, that is, antiparallel to each other. juxtaposed with. Since this semiconductor biristor utilizes the forward direction of the diode, even if the two strip-shaped laminates 3, 3 are placed side by side in contact with each other, or even if they are placed side by side with a slight spacing, the voltage-current will not change. No adverse effect on properties. At this time, the strip-shaped laminates 3, 3 and the electrode plates 4, 4'
A long thin solder material such as solder is interposed between them (not shown), so by heating these at a predetermined temperature, the strip-shaped laminates 3, 3 and the metal plates 4, 4' are bonded.
are brazed to form a strip-shaped varistor 5.
斯かる状態で短冊状バリスタ５はバリスタとし
ての電圧−電流特性を有するが、更に個々のバリ
スタ素子として分割される。つまり第２図Ｅに示
す様に細長い電極板４の長手方向に対し直角に所
定寸法にて短冊状バリスタ５を切断することによ
り、個々のバリスタ素子６に分割する。 In this state, the strip-shaped varistor 5 has voltage-current characteristics as a varistor, but is further divided into individual varistor elements. That is, as shown in FIG. 2E, the strip-shaped varistor 5 is cut at a predetermined dimension perpendicular to the longitudinal direction of the elongated electrode plate 4, thereby dividing it into individual varistor elements 6.
しかる後、同図Ｇに示す様に個々のバリスタ素
子６の両端にリード線７，７′を半田付けするが、
斯かる工程については個々のバリスタ素子に切断
する前に予め各バリスタ素子に適した形状のリー
ド線アレイを短冊状バリスタ５の電極板４，４′
に鑞付けしておき、しかる後に個々のバリスタ素
子に切断するものであつても良い。 After that, lead wires 7 and 7' are soldered to both ends of each varistor element 6 as shown in FIG.
In this process, before cutting into individual varistor elements, a lead wire array having a shape suitable for each varistor element is connected to the electrode plates 4, 4' of the strip-shaped varistor 5.
Alternatively, the varistor elements may be brazed and then cut into individual varistor elements.
次に同図Ｇに示す様に、通常のトランスフアー
モールド法により樹脂モールドし、完成した双方
向性半導体バリスタ８を得る。 Next, as shown in FIG. G, resin molding is performed using a normal transfer molding method to obtain a completed bidirectional semiconductor varistor 8.
以上述べた様に本発明の実施例によれば、PN
接合を有する大面積の半導体ウエハを所望枚数だ
け積層接着してなるPN半導体ウエハ積層体を所
定幅にて一方向に切断して複数の短冊状積層体を
作り、この短冊状積層体を少くとも２個互いに逆
方向にして細長い電極板間に並置して加熱接着
し、しかる後に個々のバリスタ素子に切断してい
るので、組立てが極めて簡略化され、しかも個々
の半導体ペレツト積層体に分割した後に逆並列接
続していないので、極性を誤つたり、半田付けに
際して位置ずれを生ずることがなく、従つて不良
品の発生が極めて少なくなる。 As described above, according to the embodiment of the present invention, PN
A PN semiconductor wafer laminate made by laminating and bonding a desired number of large-area semiconductor wafers with bonding is cut in one direction at a predetermined width to create a plurality of strip-shaped laminates, and these strip-shaped laminates are Since two varistor elements are placed side by side between long and thin electrode plates in opposite directions and then heat-bonded, and then cut into individual varistor elements, assembly is extremely simplified. Since they are not connected in antiparallel, there is no possibility of erroneous polarity or misalignment during soldering, and therefore the occurrence of defective products is extremely reduced.
第１図は従来の双方向性半導体バリスタの製造
方法を説明するための図、第２図Ａ乃至Ｇは本発
明に係る双方向性半導体バリスタの製造方法の一
実施例を説明するための図である。
１……半導体ウエハ、２……PN半導体ウエハ
積層体、３……短冊状積層体、４，４′……電極
板、５……短冊状バリスタ、６……バリスタ素
子、７，７′……リード線、８……双方向性半導
体バリスタ。
FIG. 1 is a diagram for explaining a conventional method for manufacturing a bidirectional semiconductor varistor, and FIGS. 2A to 2G are diagrams for explaining an embodiment of a method for manufacturing a bidirectional semiconductor varistor according to the present invention. It is. DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 2... PN semiconductor wafer laminate, 3... Strip-shaped laminate, 4, 4'... Electrode plate, 5... Strip-shaped varistor, 6... Varistor element, 7, 7'... ...Lead wire, 8...Bidirectional semiconductor varistor.
Claims (1)
層接着したPN半導体ペレツト積層体を逆並列接
続してなる双方向性半導体バリスタの製造方法に
おいて、 PN接合を有する大面積の半導体ウエハを鑞材
を介して所望枚数積層した後にこれを加熱して接
着する工程と、 このPN半導体ウエハ積層体を所定幅にて一方
向に切断して複数の短冊状積層体を形成する工程
と、 該短冊状積層体の少くとも２個を逆方向にして
電極間に並置すると共に加熱して、これら短冊状
積層体を前記電極に鑞付けして短冊状バリスタを
得る工程と、 該短冊状バリスタを所望寸法毎に切断して複数
のバリスタに分割する工程と、 を備えたことを特徴とする双方向性半導体バリス
タの製造方法。[Claims] 1. A method for manufacturing a bidirectional semiconductor varistor in which a PN semiconductor pellet laminate, in which a plurality of semiconductor pellets each having a PN junction are laminated and bonded, is connected in antiparallel, comprising: a large-area semiconductor wafer having a PN junction; a step of laminating a desired number of PN semiconductor wafers via a soldering material and then heating and bonding them; a step of cutting this PN semiconductor wafer stack in one direction at a predetermined width to form a plurality of strip-shaped stacks; arranging at least two of the strip-shaped laminates in opposite directions between electrodes and heating them to braze the strip-shaped laminates to the electrodes to obtain a strip-shaped varistor; A method for manufacturing a bidirectional semiconductor varistor, comprising: cutting the varistor into a plurality of varistors by cutting the varistor into desired dimensions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6068682A JPS58176962A (en) | 1982-04-12 | 1982-04-12 | Preparation of bidirectional semiconductor varister |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6068682A JPS58176962A (en) | 1982-04-12 | 1982-04-12 | Preparation of bidirectional semiconductor varister |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58176962A JPS58176962A (en) | 1983-10-17 |
| JPS6320021B2 true JPS6320021B2 (en) | 1988-04-26 |
Family
ID=13149429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6068682A Granted JPS58176962A (en) | 1982-04-12 | 1982-04-12 | Preparation of bidirectional semiconductor varister |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58176962A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60140851A (en) * | 1983-12-28 | 1985-07-25 | Origin Electric Co Ltd | Manufacture of semiconductor device |
| US5675180A (en) * | 1994-06-23 | 1997-10-07 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments |
-
1982
- 1982-04-12 JP JP6068682A patent/JPS58176962A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58176962A (en) | 1983-10-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3982080B2 (en) | Thermoelectric module manufacturing method and thermoelectric module | |
| EP1943683B1 (en) | Photovoltaic modules and interconnect methodology for fabricating the same | |
| US3142783A (en) | Electrical circuit system | |
| JP3223257B2 (en) | Manufacturing method of thermoelectric conversion module | |
| JP2912496B2 (en) | Solar cell module | |
| US6387730B2 (en) | Hybrid S.C. devices and method of manufacture thereof | |
| JP5515721B2 (en) | Method for manufacturing thermoelectric conversion module | |
| EP0482511A1 (en) | Integrated photovoltaic device | |
| US4687879A (en) | Tiered thermoelectric unit and method of fabricating same | |
| JP2014063978A (en) | Solar cell module and manufacturing method therefor | |
| CN102097743A (en) | Method for assembling double-side mounting soldering matching sheets of centimeter-grade strip-shaped semiconductor laser | |
| CN111564522A (en) | Preparation method of photovoltaic module combining P-type solar cell and N-type solar cell | |
| JPH0818109A (en) | Thermoionic element and manufacture thereof | |
| JPS6320021B2 (en) | ||
| US3449173A (en) | Thermoelectric couple with soft solder electrically connecting semi-conductors and method of making same | |
| US3256589A (en) | Method of forming an electrical circuit assembly | |
| US9543494B2 (en) | Thermoelectric conversion module and method of manufacturing the same | |
| US11652178B2 (en) | Solar cell module including solar cells | |
| JPS6154262B2 (en) | ||
| JPH10335710A (en) | Thermal conversion element and its manufacture | |
| JPH10313134A (en) | Manufacture of thermoelectric module | |
| JPH10229223A (en) | Thermoelectric element | |
| JPH02178958A (en) | Electronic cooling element and manufacture thereof | |
| JP2022052577A (en) | Thermoelectric module and manufacturing method thereof | |
| JPH07169995A (en) | Thermoelement array |