JPS58176962A - Preparation of bidirectional semiconductor varister - Google Patents
Preparation of bidirectional semiconductor varisterInfo
- Publication number
- JPS58176962A JPS58176962A JP6068682A JP6068682A JPS58176962A JP S58176962 A JPS58176962 A JP S58176962A JP 6068682 A JP6068682 A JP 6068682A JP 6068682 A JP6068682 A JP 6068682A JP S58176962 A JPS58176962 A JP S58176962A
- Authority
- JP
- Japan
- Prior art keywords
- varister
- laminated
- rectangular
- semiconductor
- varistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
本発明はＰＮ接合を有する複数のペレットを積層接着し
九ＰＮペレット積層体を逆並列接続してなる双方向性半
導体バリスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bidirectional semiconductor varistor in which a plurality of pellets having a PN junction are laminated and bonded and nine PN pellet stacks are connected in antiparallel.
一般に電気囲路に入来するサージ讐抑制したプ、或いは
その電気囲路が発生するサージ電圧を吸収するのくバリ
スタが用いられる。斯かるバリスタとしてダイオードの
順方向特性を利用して双方向のサージ電圧を吸収すべく
、ＰＮｉ１合を有する複数のペレットを積層したものを
逆並列に接続してなる双方向性半導体バリスタがある。Generally, a varistor is used to suppress the surge voltage entering the electric fence or to absorb the surge voltage generated by the electric fence. As such a varistor, there is a bidirectional semiconductor varistor made by stacking a plurality of pellets having PNi1 and connecting them in antiparallel in order to absorb bidirectional surge voltage by utilizing the forward characteristics of a diode.
従来の斯かる）Ｚ ９スタの製造方法は、ＰＮｇ合を有
する大面積の半導体ウェハを鑞材を介して所望枚数積層
して接着させた後、Ｘ、Ｙ方向に所定の寸法で切断して
多数のＰＮベレット積層体に分割し、第１図に示す様に
これらＰＮベレット積層体Ｐの２１１Ｉ ｔ−互一に逆
方向になる様に電極Ｅ、Ｂ’間に鑞材Ｓと一緒に配置す
ると共に加熱して前記ＰＮペレット積層体Ｐ（（電ｆｆ
１Ｅ、Ｅ’に鑞付けしてい友。この様に従来の製造方法
は個々に切断されたＰＮ半導体ペレット積層体２Ｗｋ逆
並列にして組立てているので、工数が非常にかかり、且
つＰＮ半導体ベレット積層体が非常に小さいために組立
て時に互いに逆方向にするところを互いに同方向に組立
ててしまう間違いが生じ易く、歩留りを著しく低下させ
るという欠点があった。The conventional manufacturing method for Z 9 stars is to stack and bond a desired number of large-area semiconductor wafers with PNg bonding via a soldering material, and then cut them into predetermined dimensions in the X and Y directions. The PN pellet laminates P are divided into a number of laminates, and as shown in FIG. At the same time, the PN pellet laminate P ((electronic ff
My friend is brazing 1E and E'. As described above, the conventional manufacturing method involves assembling 2Wk of individually cut PN semiconductor pellet stacks in antiparallel, which requires a large number of man-hours, and since the PN semiconductor pellet stacks are very small, they are assembled in opposite directions when assembled. It is easy to make a mistake in assembling the parts in the same direction, which has the drawback of significantly lowering the yield.
本発明は斯かる従来方法による欠点を除去することを目
的とし、ＰＮ接合を有する大面積の半導体ウェハを複数
枚積層接着してなるＰＮ半導体ウニ八へ層体を所定幅に
て一方向に切断して複数の短冊状積層体を得、これら短
冊状積層体の少くとも２個を逆方向にして電＃ｊ、板関
に並置して鑞付けし、しかる後に所定幅毎に個々に切断
することを特徴としている。The present invention aims to eliminate the drawbacks of the conventional method, and involves cutting the layered body in a predetermined width in one direction into a PN semiconductor wafer made by laminating and bonding a plurality of large-area semiconductor wafers having PN junctions. to obtain a plurality of strip-shaped laminates, at least two of these strip-shaped laminates are placed side by side on the board #j and board in opposite directions and brazed, and then cut individually into predetermined widths. It is characterized by
第１図及び第２図（Ａ）〜（Ｇ） Ｋよシ本発明に係る
双方向性半導体バリスタの製造方法の一笑施ガを説明す
る。1 and 2 (A) to (G) K. A brief explanation of the method for manufacturing a bidirectional semiconductor varistor according to the present invention will now be described.
先ず牙２図人）に示す様なＰＮ接合を有する大面積の半
導体９エバ１【所望枚数、ここでは４枚用意し、これら
半導体ウェハを鑞材（図示せず）を介して同方向に積層
した後に加熱して互い専接着させることにより、同図Ｂ
）Ｋ示す様なＰＮ半導体９工八積層体２を得ている。次
に後の工程において電極板を鑞接するために、半導体９
工バ積層体２の全面に通常のメッキ方法によりメッキを
施す。First, prepare a large-area semiconductor wafer 1 (desired number of wafers, here 4 wafers) having a PN junction as shown in Figure 2, and stack these semiconductor wafers in the same direction via a solder material (not shown). By heating and adhering them to each other,
) A 9-8 PN semiconductor stack 2 as shown in FIG. Next, in order to solder the electrode plate in a later process, the semiconductor 9
Plating is applied to the entire surface of the workpiece laminate 2 using a conventional plating method.
しかる後同図Ｃ）に示すＩＩＫカッティングマシーンに
よシ半導体ウェハ積層体２を所定の幅にて同一方向に切
断する。この結果、同図Ｄ） Ｋ示す様な一方に細長い
短冊状積層体３が多゛数個得られる。Thereafter, the semiconductor wafer stack 2 is cut into a predetermined width in the same direction using the IIK cutting machine shown in FIG. As a result, a large number of elongated strip-shaped laminates 3 are obtained on one side as shown in FIG.
次に同図Ｄ）Ｋ示す様にほぼ同じ長さの短冊状積層体３
ｔ２個ニッケル板或いはコバール板の様々細長い金属板
４．４′間に、互いに逆方向、っま夛逆並列になる様に
並置する。この半導体バイリスタにあってはダイオード
の順方向を利用しているので、２ｍの短冊状積層体３．
３を接触させて並置しても、或いは若干間隔を設けて並
置しても電圧−電流特性に悪影響を及ぼすことはない。Next, as shown in Figure D)K, a strip-shaped laminate 3 with approximately the same length
T2 various elongated metal plates 4.4' made of nickel plates or Kovar plates are arranged side by side in opposite directions to each other so as to be inversely parallel to each other. Since this semiconductor biristor utilizes the forward direction of the diode, the 2m long strip-shaped laminate 3.
Even if 3 are placed side by side in contact with each other, or even if they are placed side by side with some spacing between them, the voltage-current characteristics will not be adversely affected.
なおこの際、短冊状積層体６．６と電極板４．４′間に
は半田の様な細長い鑞材が介在されておシ（図示せず）
、従ってこれらを所定温度で加熱することによシ短冊状
積層体３．６と金属板４．４′とが鑞付けされ、短冊状
バリスタ５となる。At this time, a long thin solder material such as solder is interposed between the strip-shaped laminate 6.6 and the electrode plate 4.4' (not shown).
Therefore, by heating these at a predetermined temperature, the strip-shaped laminate 3.6 and the metal plate 4.4' are brazed to form the strip-shaped varistor 5.
斯かる状態で短冊状バリスタ５はバリスタとしての電圧
−電流特性ｔ″有するが、更に一々のバリスタ素子とし
て分割される。つまり第２図Ｅ）Ｋ示す様に細長い電極
板４の長手、方向に対し直角に所定寸法にて短冊状バリ
スタ５を切断することによシ、個々のバリスタ素子６に
分割する。In this state, the strip-shaped varistor 5 has voltage-current characteristics t'' as a varistor, but is further divided into individual varistor elements.In other words, as shown in FIG. The strip-shaped varistor 5 is cut into individual varistor elements 6 by cutting the strip-shaped varistor 5 with a predetermined dimension at right angles to the varistor element.
しかる後、同図Ｇ）に示す様に−々のバリスタ素子６の
両端Ｋ １７−ド線７．７’ｔ−半田付けするが、斯か
る工種については鰯々のバリスタ素子に切断する前に予
め各バリスタ素子に適した形状のり一ド纏アレイを短冊
状バリスタ５のＩＥ電極板、４′に鑞付けしておき、し
かる後に個々のバリスタ素子に切断するものであっても
良φ。After that, as shown in Figure G), both ends of each varistor element 6 are soldered to each other. It is also possible to braze a glue-wrapped array in a shape suitable for each varistor element to the IE electrode plate 4' of the strip-shaped varistor 5 in advance, and then cut it into individual varistor elements.
次に同図Ｇ）に示す様に、通常のトランスファーモール
ド法によシ樹脂モールドし、完成した双方向性半導体バ
リスタ８を得る。Next, as shown in FIG. G), resin molding is performed by a normal transfer molding method to obtain a completed bidirectional semiconductor varistor 8.
以上述べた様に本発明の実施的によれば、ＰＮ接合を有
する大面積の半導体９エバ【所望枚数だけ積層接着して
な名ＰＮ半導体つェへ積層体を所定幅にて一方向に切断
して複数の短冊状積層体を作り、この短冊状積層体を少
くとも２１１互いに逆方向にして細長−電極板間に並置
して加熱接着し、しかる後Ｋｌｌ々のバリスタ素子に切
断しているので１組立てが極めて簡略化され、しかも個
々の半導体ベレット積層体に分割した後に逆並列接続し
ていないので、極性を誤っ九り、半田付けに際して位置
ずれを生ずることがなく、従って不良品の発生が極めて
少なくなる。As described above, according to the embodiment of the present invention, a large-area semiconductor wafer having a PN junction is laminated and bonded in a desired number of layers, and the laminate is cut in one direction at a predetermined width into a PN semiconductor. A plurality of strip-shaped laminates are made, and these strip-shaped laminates are placed in parallel between the elongated and electrode plates in at least 211 directions in opposite directions and are heat-bonded, and then cut into KII varistor elements. Therefore, one assembly is extremely simplified, and since there is no anti-parallel connection after dividing into individual semiconductor pellet stacks, there is no possibility of incorrect polarity or misalignment during soldering, and therefore there is no possibility of defective products. becomes extremely small.
第１図は従来の双方向性半導体バリスタの製造方法を説
明するための図、第２図ム）乃至Ｇ）は本発明に係る双
方向性半導体バリスタの製造方法の一実施Ｐ１を説明す
るための図である。
１・・・半導体ウェハ
２・−・ＰＮＮ半導体ウニへ層体
５・−・Ｍｉ冊状積層体
４．４′・・・電極板
５・・・短冊状バリスタ
６・・・バリスタ素子
７、７′・・・リード線
８・・・双方向性半導体バリスタ
特許出願人 オリジン電気株式会社FIG. 1 is a diagram for explaining a conventional method for manufacturing a bidirectional semiconductor varistor, and FIG. This is a diagram. 1...Semiconductor wafer 2...PNN semiconductor layer 5...Mi strip-shaped laminate 4.4'...Electrode plate 5...Strip-shaped varistor 6...Varistor elements 7, 7 '... Lead wire 8... Bidirectional semiconductor varistor patent applicant Origin Electric Co., Ltd.
Claims (1)
ＰＮ半導体ベレット槓積層体逆並列接続してなる双方向
性半導体バリスタの製造方法において、 ＰＮ接合を有する大面積の半導体ウェハを鑞材を介して
所望枚数積層した後にこれを加熱して接着する工程と、 このＰＮ半導体ウェハ積層体を所定幅にて一方向に切断
して複数の短冊状積層体を形成する工程と、 該短冊状積層体の少くとも２個゛を逆方向にして電極間
に並置すると共に加熱して、これら短冊状積層体を前記
電極に鑞付けして短冊状バリスタを得る工程と、 骸短冊状バリスタを所望寸法毎に切断して被数のバリス
タに分割する工程と、 全備え九〇とｔ−特徴とする双方向性半導体バリスタの
製造方法。[Scope of Claims] A method for manufacturing a bidirectional semiconductor varistor formed by connecting a plurality of semiconductor pellets having a PN junction in antiparallel and bonding a single layer of PN semiconductor pellets, comprising: a large-area semiconductor wafer having a PN junction; a step of laminating a desired number of PN semiconductor wafers via a soldering material and then heating and bonding them; a step of cutting this PN semiconductor wafer stack in one direction at a predetermined width to form a plurality of strip-shaped stacks; arranging at least two of the strip-shaped laminates in opposite directions between electrodes and heating them, and brazing these strip-shaped laminates to the electrodes to obtain a strip-shaped varistor; A method for manufacturing a bidirectional semiconductor varistor, comprising: a step of cutting a varistor into desired dimensions and dividing the varistor into a number of varistors;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6068682A JPS58176962A (en) | 1982-04-12 | 1982-04-12 | Preparation of bidirectional semiconductor varister |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6068682A JPS58176962A (en) | 1982-04-12 | 1982-04-12 | Preparation of bidirectional semiconductor varister |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58176962A true JPS58176962A (en) | 1983-10-17 |
| JPS6320021B2 JPS6320021B2 (en) | 1988-04-26 |
Family
ID=13149429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6068682A Granted JPS58176962A (en) | 1982-04-12 | 1982-04-12 | Preparation of bidirectional semiconductor varister |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58176962A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60140851A (en) * | 1983-12-28 | 1985-07-25 | Origin Electric Co Ltd | Manufacture of semiconductor device |
| US5661087A (en) * | 1994-06-23 | 1997-08-26 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments |
-
1982
- 1982-04-12 JP JP6068682A patent/JPS58176962A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60140851A (en) * | 1983-12-28 | 1985-07-25 | Origin Electric Co Ltd | Manufacture of semiconductor device |
| US5661087A (en) * | 1994-06-23 | 1997-08-26 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6320021B2 (en) | 1988-04-26 |
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