JPS63198356A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63198356A JPS63198356A JP3101687A JP3101687A JPS63198356A JP S63198356 A JPS63198356 A JP S63198356A JP 3101687 A JP3101687 A JP 3101687A JP 3101687 A JP3101687 A JP 3101687A JP S63198356 A JPS63198356 A JP S63198356A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer wiring
- wiring part
- insulating film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000003870 refractory metal Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005192 partition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 8
- 239000011574 phosphorus Substances 0.000 abstract description 8
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 238000002844 melting Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000008018 melting Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
半導体装置に広く使用されている多結晶シリコン膜の配
線は、半導体装置の高密度化にともなう配線幅の縮小と
配線長の増大により配線抵抗が無視できなくなり、多結
晶シリコンに比べて約１桁抵抗が小さく取扱いの容易な
高融点金属硅化物の配線技術が高密度化、高速化半導体
装置にとって不可欠の技術となっている。Polycrystalline silicon film wiring, which is widely used in semiconductor devices, has a wiring resistance that cannot be ignored due to the reduction in wiring width and increase in wiring length due to the increasing density of semiconductor devices, and is approximately one order of magnitude lower than that of polycrystalline silicon. Wiring technology using high-melting point metal silicide, which has low resistance and is easy to handle, has become an indispensable technology for high-density, high-speed semiconductor devices.
従来の半導体装置の製造方法の一例は、半導体素子領域
と前記素子領域を区画するフィールド絶縁膜とを備えた
半導体基板の上に多結晶シリコン膜の下層配線を設け該
下層配線を含む全面に下層絶縁膜を形成し、前記素子領
域上および前記下層配線の下層絶縁膜に配線接続用の開
口部をそれぞれ設け、前記開口部を含む全面に不純物を
含む多結晶シリコン膜と高融点金属膜を順次堆積し、前
記多結晶シリコン膜と高融点金属膜を選択エツチングし
て前記開口部で前記素子領域と前記下層配線にそれぞれ
接続し前記下層配線上に延在する上層配線を形成し、前
記上層配線を熱処理して前記高融点金属膜と接触してい
る前記多結晶シリコン膜を反応させ、高融点金属硅化物
膜と多結晶シリコン膜の配線を形成する。この場合、前
記多結晶シリコン膜には接続抵抗を下げるためにイオン
注入法等を用いて不純物の添加が必要である。An example of a conventional method for manufacturing a semiconductor device is to provide a lower layer wiring of a polycrystalline silicon film on a semiconductor substrate having a semiconductor element region and a field insulating film that partitions the element region, and to cover the entire surface including the lower layer wiring. An insulating film is formed, openings for wiring connection are provided on the element region and in the lower insulating film of the lower wiring, and a polycrystalline silicon film containing impurities and a high melting point metal film are sequentially formed over the entire surface including the openings. The polycrystalline silicon film and the high melting point metal film are deposited and selectively etched to form an upper layer wiring which is connected to the element region and the lower layer wiring through the opening and extends over the lower layer wiring, and the upper layer wiring is connected to the element region and the lower layer wiring through the opening. is heat-treated to cause the polycrystalline silicon film in contact with the high melting point metal film to react, thereby forming wiring between the high melting point metal silicide film and the polycrystalline silicon film. In this case, it is necessary to add impurities to the polycrystalline silicon film using ion implantation or the like in order to lower the connection resistance.
上述した従来の半導体装置の製造方法は、上層配線と素
子領域および下層配線との接続抵抗を下げるためには多
結晶シリコン層に拡散法やイオン注入法等を用いて不純
物の添加を必要とし、工程が長くなるという問題点があ
る。また、多結晶シリコン層と高融点金属膜の２層構造
を加工するため微細加工性に欠けるという問題点があっ
た。The conventional semiconductor device manufacturing method described above requires adding impurities to the polycrystalline silicon layer using a diffusion method, an ion implantation method, etc. in order to lower the connection resistance between the upper layer wiring, the element region, and the lower layer wiring. There is a problem that the process becomes long. Furthermore, since a two-layer structure consisting of a polycrystalline silicon layer and a high melting point metal film is processed, there is a problem in that microfabrication is lacking.
本発明の目的は、工程を簡素化し、かつ低抵抗の配線お
よび素子領域等への接続抵抗を下げた半導体装置の製造
方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that simplifies the process and reduces the resistance of connections to low-resistance wiring and element regions.
本発明の半導体装置の製造方法は、半導体素子領域と前
記素子領域を区画するフィールド絶縁膜とを備えた半導
体基板の前記フィールド絶縁膜の上に多結晶シリコン膜
の下層配線を形成する工程と、前記下層配線を含む全表
面に前記素子領域の配線接続領域と同一導電型の不純物
を３〜１０ｍｏｌ％含む下層の絶縁膜を形成する工程と
、前記配線接続領域および前記下層配線の上の前記下層
の絶縁膜のそれぞれの箇所に配線接続用の開口部を設け
該開口部を含む前記下層の絶縁膜上に高融点金属硅化物
膜を形成する工程と、前記高融点金属硅化物膜を選択的
にエツチングして前記接続領域と前記下層配線とに接続
する上層配線を形成する工程と、前記上層配線を被覆し
前記不純物と同一導電型の不純物を同量含む上層の絶縁
膜を全面に形成しかつ前記不純物を前記上層配線中に拡
散させて接続抵抗を下げるための熱処理を行う工程とを
含んで構成される。A method for manufacturing a semiconductor device according to the present invention includes the steps of: forming a lower layer wiring of a polycrystalline silicon film on the field insulating film of a semiconductor substrate including a semiconductor element region and a field insulating film that partitions the element region; forming a lower layer insulating film containing 3 to 10 mol % of impurities of the same conductivity type as the wiring connection region of the element region on the entire surface including the lower layer wiring; forming an opening for wiring connection at each location of the insulating film and forming a refractory metal silicide film on the lower insulating film including the opening, and selectively forming the refractory metal silicide film. etching to form an upper layer wiring to connect the connection region and the lower layer wiring, and forming an upper layer insulating film covering the upper layer wiring and containing the same amount of impurity of the same conductivity type as the impurity on the entire surface. and a step of performing heat treatment to diffuse the impurity into the upper layer wiring and lower connection resistance.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の詳細な説明するための
工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps to explain the present invention in detail.
第１図（ａ）に示すように、Ｐ型シリコン基板１に素子
形成領域を区画するフィールド絶縁膜２を設け、前記素
子形成領域にヒ素を選択的にイオン注入してＮ型拡散領
域３を形成する。次に、下層配線としてフィールド絶縁
膜２の上にリンを含む多結晶シリコン膜４を選択的に設
け、多結晶シリコン膜４を含む全面にリンを５ｍ０１％
含む酸化シリコン膜（以後ＰＳＧ膜と記す）５をＣＶＤ
法により形成する。As shown in FIG. 1(a), a field insulating film 2 is provided on a P-type silicon substrate 1 to define an element formation region, and an N-type diffusion region 3 is formed by selectively implanting arsenic ions into the element formation region. Form. Next, a polycrystalline silicon film 4 containing phosphorus is selectively provided on the field insulating film 2 as a lower layer wiring, and 5m01% of phosphorus is applied to the entire surface including the polycrystalline silicon film 4.
The silicon oxide film (hereinafter referred to as PSG film) 5 containing
Formed by law.
次に、第１図（ｂ）に示すように、拡散領域３と多結晶
シリコン膜４との上のＰＳＧ膜５にそれぞれ開口部を設
け、前記開口部を含む全面に硅化チタニウム膜６をスパ
ッタリング法により約０．３μｍの膜厚に形成する。Next, as shown in FIG. 1(b), openings are formed in the PSG film 5 on the diffusion region 3 and the polycrystalline silicon film 4, and a titanium silicide film 6 is sputtered over the entire surface including the openings. The film is formed to a thickness of about 0.3 μm using the method.
次に、第１図（ｃ）に示すように、硅化チタニウム膜６
を選択的にエツチングして前記開口部の拡散領域３およ
び多結晶シリコン膜４にそれぞれ接続する上層配線を設
ける。Next, as shown in FIG. 1(c), a titanium silicide film 6
is selectively etched to provide upper layer interconnections connected to the diffusion region 3 and the polycrystalline silicon film 4 in the opening, respectively.
次に、第１図（ｄ）に示すように、硅化チタニウム膜６
を被覆して全面にリンを約５ｍ０１％含むＰＳＧ膜７を
ＣＶＤ法で形成し、９００℃の熱処理を行いＰＳＧ膜７
を平坦化すると同時にＰＳＧ膜５，７より硅化チタニウ
ム膜６にリンを拡散させて拡散領域３および多結晶シリ
コン膜への低抵抗接続を行なう。Next, as shown in FIG. 1(d), the titanium silicide film 6
A PSG film 7 containing about 5m01% of phosphorus is formed on the entire surface by CVD, and then heat-treated at 900°C to form a PSG film 7.
At the same time, phosphorus is diffused from the PSG films 5 and 7 into the titanium silicide film 6 to establish a low resistance connection to the diffusion region 3 and the polycrystalline silicon film.
以−ト説明したように本発明は、上層配線として高融点
金属硅化物膜をスパッタリング法で直接形成することで
工程を簡素化し、かつ、上層配線を上、下層より被覆す
る絶縁膜より高融点金属硅化物膜の上層配線中へ不純物
を拡散させることによリ、配線の低抵抗化と素子領域お
よび下層配線への接続抵抗を下げる効果がある。As explained above, the present invention simplifies the process by directly forming a high melting point metal silicide film as the upper layer wiring by sputtering, and has a higher melting point than the insulating film that covers the upper layer wiring from above and below. Diffusion of impurities into the upper layer wiring of the metal silicide film has the effect of lowering the resistance of the wiring and the connection resistance to the element region and lower layer wiring.
第１図＜ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。
１・・・シリコン基板、２・・・フィールド絶縁膜、３
・・・拡散領域、４・・・多結晶シリコン膜、５・・・
ＰＳＧ膜、６・・・硅化チタニウム膜、７・・・ＰＳＧ
膜。
代理人 弁理士 内 原 音
一′−一・
入
万１図FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. 1... Silicon substrate, 2... Field insulating film, 3
...diffusion region, 4...polycrystalline silicon film, 5...
PSG film, 6...Titanium silicide film, 7...PSG
film. Agent Patent Attorney Otoichi Uchihara
Claims (1)
縁膜とを備えた半導体基板の前記フィールド絶縁膜の上
に多結晶シリコン膜の下層配線を形成する工程と、前記
下層配線を含む全表面に前記素子領域の配線接続領域と
同一導電型の不純物を３〜１０ｍｏｌ％含む下層の絶縁
膜を形成する工程と、前記配線接続領域および前記下層
配線の上の前記下層の絶縁膜のそれぞれの箇所に配線接
続用の開口部を設け該開口部を含む前記下層の絶縁膜上
に高融点金属硅化物膜を形成する工程と、前記高融点金
属硅化物膜を選択的にエッチングして前記接続領域と前
記下層配線とに接続する上層配線を形成する工程と、前
記上層配線を被覆し前記不純物と同一導電型の不純物を
同量含む上層の絶縁膜を全面に形成しかつ前記不純物を
前記上層配線中に拡散させて接続抵抗を下げるための熱
処理を行う工程とを含むことを特徴とする半導体装置の
製造方法。forming a lower layer interconnection of a polycrystalline silicon film on the field insulating film of a semiconductor substrate including a semiconductor element region and a field insulating film that partitions the element region; forming a lower layer insulating film containing 3 to 10 mol% of impurities of the same conductivity type as the wiring connection region of the region, and wiring connection to each location of the lower layer insulating film above the wiring connection region and the lower layer wiring; forming a refractory metal silicide film on the lower layer insulating film including the opening, and selectively etching the refractory metal silicide film to separate the connection region and the lower layer. forming an upper layer insulating film covering the upper layer wiring and containing the same amount of impurity having the same conductivity type as the impurity, and diffusing the impurity into the upper layer wiring; 1. A method of manufacturing a semiconductor device, comprising the step of performing heat treatment to reduce connection resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3101687A JPS63198356A (en) | 1987-02-13 | 1987-02-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3101687A JPS63198356A (en) | 1987-02-13 | 1987-02-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63198356A true JPS63198356A (en) | 1988-08-17 |
Family
ID=12319739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3101687A Pending JPS63198356A (en) | 1987-02-13 | 1987-02-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63198356A (en) |
-
1987
- 1987-02-13 JP JP3101687A patent/JPS63198356A/en active Pending
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