JPS63198094A - Lithography for bit map display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The explanation will be given in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problems to be solved by the invention E. Means for solving the problems (Fig. 1) F. Effect G. Examples (Figs. 1 to 6) ) Effects of the Invention A Field of Industrial Application This invention relates to a drawing method in a bitmap display system.

B. Summary of the Invention The present invention provides a bit map display system in which bit blocks of predetermined pattern data are transferred from a pattern memory to a display memory using a special method, and the pattern data is weighted in a predetermined manner. This enables high-speed drawing without aliasing.

C. Prior Art] When displaying figures in computer graphics, CAD, etc., a bitmap display system is generally used, but in this system, a raster scan type CRT display and a A display memory (frame buffer) is used to supply bit pattern data to the CRT display.

However, since this display system performs drawing using pixels, aliasing such as jaggies appears when diagonal lines or curved lines are drawn.

However, it is known that one way to eliminate this aliasing is to narrow the grid spacing.

That is, in FIG. 7, the solid line (1) shows a grid with standard spacing, the broken line (11) shows a grid with half the standard spacing,
Pixels are displayed at the intersections of these grids (1) and (11), that is, grid points (2) and (12), and straight lines and the like are drawn.

Figure 8 shows the case where pixel (3) is displayed at standard grid point (2) and diagonal line (4) is drawn, and Figure 9 shows 1/
Display the pixel (13) at the grid point (12) of No. 2 and draw the “ζ diagonal line (
14) is drawn, and from these figures, the lattice +
It can be seen that aliasing can be improved by narrowing the intervals in (1) and (11).

Document 2: Specification and drawings of Japanese Patent Application No. 1983-314921,
- Patent dated January 22, 1986 by the applicant and the same agent As the grid (1
), (11) requires increasing the horizontal scanning frequency of the raster, and there is a limit to this.

Therefore, in this raster scan display system, in order to improve aliasing, some kind of processing other than the method of narrowing the interval between grids +1) and (11), that is, antialiasing processing is required.

However, the processing speed of conventional unarchealing processing is slow, and is 1/1 of the speed without unarchealing processing.
The drawing speed is about 0 to 1/100, so it cannot be used interactively, and the hardware tends to be complicated.

This invention attempts to solve the above problems.

E. Means for Solving Problems Therefore, in the present invention, in a bit map display system, bit blocks of predetermined pattern data are transferred from a pattern memory to a display memory using a special method, and the pattern data is By weighting the data in a predetermined manner, high-speed drawing without aliasing is achieved.

F Action: High-speed drawing and antialiasing are simultaneously realized.

G. Example First, the high-speed drawing method which is the basis of this invention will be explained.

In this drawing method, a pattern memory having blocks of the same capacity as display memory blocks is provided, data of a desired pattern is retrieved from the pattern memory, and bit block transfer is performed to the display memory. During this transfer, the desired drawing is performed by shifting or rotating the data.

That is, in Fig. 10, (105) indicates a display memory, and this memory (105) is divided into a plurality of blocks (5B) as shown in Fig. 11, and in this example, , each block (5B) is 8
The capacity is 4 bits x 4 lines. Note that the numbers in parentheses are block addresses.

Further, (101) indicates a pattern memory, and this memory (101) is constituted by a ROM and is divided into a plurality of blocks (IB).

And in this case, block (IB) is block (5B
), that is, bits A1 to H4 of 8 bits x 4 lines, and these bits A1 to H4 are used as bit pattern data for drawing straight lines with different slopes for each block (IB).

Then, the data in the memory (101) is transferred to the barrel shifter (
Beef Rotator”) (102), (103
) and memory (105) through the ALU (104)
) and the focus block is transferred to the CRT display (
The straight bit pattern drawn in 132) is the memory
(105).

That is, for example, address (X,
The data A1 to H4 from the block (1B) of the barrel shifter (1
02), the shifted data A is shifted in the X direction (rightward) by, for example, 5 bits (Sx=5) as shown in FIG. 11B by the control signal Sx.
1 to H4 are the control signals S in the barrel shifter (103).
As shown in FIG.
The output is written to memory (105) through ALU (104).

In this case, as shown in C and D of the same figure, the barrel shifter (1
Of the outputs of memory (105), bits A1 to C3 are located in the lower right area of the shifter output.
Since the focus D1-113 is located in the lower left area of the shifter output, it is written in the lower left area of address (M+1, N), and so on. is written so that the bit position in the thick output matches the focus position in block (5B) of memory (105). That is, data A1 to HL (the same data for any block (IB)) in memory (101) is transferred to memory (105).
When transferring to the position shown in the same figure,
This transfer is performed by setting Sx-5*Sy-1 in accordance with the amount of bit position deviation between the data A1 to H1 and the block (5B).

In addition, the memory (105) is set to read-modify-write mode, and only the “l” bit of data A1 to 1r4 is written to the bit in the corresponding position of the memory (105), which corresponds to the “0” bit. The bit at the location (the bit in memory (105)) is left as is.

So, for example, bits A 4 * B4 r C3 * D3 * of the block at address (X, Y)
When E2 +F2, Gt, Ift are @1'' and the drawing data is a straight line with a slope of 172, the block at this address (X, Y) is shown in Figure 11B,
Through the processing of C, bit blocks are transferred as shown in the same figure, and then the address (
If the block of
This means that the drawing data for a straight line with a slope of /2 has been written over two pronks in the memory (5), and the straight line with a slope of 1/2 is displayed on the CRT display (133).
It will be displayed over the block length.

In this case, when a straight line is drawn halfway, the masking data stored in the masking pattern memory (10B) is supplied to the masking register (107), and the unnecessary portions are masked in the ALU (41). If necessary, the data in the memory (105) is supplied to the ALU (4) through the latch (108), and logical operations are performed on the data A1 to Ilt.

Further, a block address is supplied from the memory address controller (111) to the memory (105) through addition/subtraction circuits (112) and (113). Also,
The shift amounts Sx and Sy are determined by the shift controller (114) based on the addresses of the memories (101) and (105).

Therefore, when displaying a straight line, a block (IB) of memory (101) is selected based on the slope of the straight line, and data A1 to H4 are selected from the selected block (IB).
bit position shift Sx for block (5B),
The focus A l" H4 is shifted by Sv and written to block (5B) of memory (5). By repeating this process, a straight line of any length with any slope can be displayed. become.

Thus, according to the above drawing method, when displaying a straight line, a block (IB) of memory (1) is selected based on the slope of the straight line, and data A1 to H4 are extracted from the selected block (IB). , this data A1-114
Bit position shift Sx+ for block (5B)
All you need to do is shift bits At~114 by SV and write this to block (5B) of memory (105), that is, select a drawing pattern in memory (101) and generate an address for drawing in memory (101). , setting the shift amount for the barrel shifters (102) and (103) and transferring the bit block, and the focus block transfer only needs to be done once (1-cycle), so the read/modify/write mode of the memory (105) is possible. It is possible to perform drawing at high speed up to the speed limited by the cycle time of .

In addition, the circuits (101) to (114') are all TTL
Alternatively, it can be C-MOS, and these circuits (1
01') to (114') or interfaces with peripheral circuits are easy.

In the present invention, an anchoring process is performed in the above-described drawing method.

In FIG. 12, the grid (1) has a standard spacing, for example, a spacing corresponding to a display capacity of 1024 x 1280 pixels, and a pixel is placed at a predetermined one of the grid points (2) of this grid (1). (3) is displayed. Note that this grid point (3) is displayed.
) will hereinafter be referred to as "device coordinates."

Then, for such a lattice (1), its 1/N (N
is an integer greater than or equal to 2), for example, a grid (11) with 1/2 spacing.
is set. However, this grid point (11) and its grid point (12) are virtual, and no pixel will be displayed at the grid point (12).
The coordinates of 12) are called "logical coordinates."

Then, in this logical coordinate system, pixels (13) of straight lines or curves to be drawn are plotted using a method such as DDA. FIG. 12 shows a pixel (13) when drawing a straight line (4).

And this one plotted! (13) is weighted and mapped to pixel (3) on the device coordinate system.

In this case, the weighting is - For example, the center is pixel (3) in the device coordinate system, and the grids (1
Assuming a diagonally shaded area (15) surrounded by 1), three pixels (13) are calculated according to the area (crosshatched part) of the pixel (13) included in this area (15). , (13) , 0 of (13)
．． Since the area (15) includes an area of 5.1 and 0.25, the brightness of the central pixel (3) is 0.5 +
1 + 0.25-1.75.

That is, for example, in FIG. 14, it is assumed that pixel P is a pixel to be displayed and is therefore located at grid point (2) indicated by device coordinates. Also, the center and surrounding pixels on the logical coordinate centering on this pixel P are Po=P
Let it be θ. However, these pixels Po to P8 are pixels whose values are calculated by DDA or the like as described above, and take a value of "0" or "1" depending on the figure to be drawn.

At this time, the brightness P of the pixel P is P=Po +
(P2 +P4 +P6 ÷Pa)+ (
Px → -P3 → -Ps +Pv). In other words,
When pixel (13) on the logical coordinates is at the i center as seen from the corresponding pixel (3) on the device coordinates...
...1.0ii When it is on the edge of the boundary of area (15) ...0.5iii When it is also at the corner ...Add with a weight of 0.25 , this addition result is taken as the luminance of pixel (3).

Therefore, when drawing straight line (4) in Figure 8,
As shown in FIG. 13, the brightness of each pixel (3) is controlled. However, in this figure, the luminance of the pixel (3) is indicated by the size of the circle mark without indicating the pixel (3). Furthermore, although the brightness is not standardized in this figure, it is actually preferable to standardize the brightness.

FIG. 1 shows an example of hardware for realizing the above drawing process. That is, in this example, the pixel (
3) is a case where the brightness is controlled in four stages to perform the antialiasing process. In order to control the brightness in four stages, two bits are required for one pixel (3), so a similar circuit (
201) to (213) are provided in parallel, and the memory (1
The data (bits) of 05) and (205) are supplied to the CRT display (132) through the look-up table (131).

At this time, the memory (101'), (2
01) as described above, each of their blocks (IB)
.

(1B) has bit pattern data for drawing straight lines with different inclinations at the pinch of the auxiliary grid point (12), and one focus of the memory (101) for one pixel (3) and the memory (201) The value ('''1
”, “O”) are defined.

FIG. 2 shows an example of the bit pattern of blocks (IB) and (1B) of memories (101) and (201). In this example, in the case of 16 bits x 4 lines, the O mark is ” bit, and a blank is “0”.
” indicates the bit.

Furthermore, the table (131) is a kind of D/A converter, and in this example, the table (131) is a third
It performs the conversion shown in the figure, for example, memory (
The data (bits) from memory (105) is “11” and memory (2
If the data from 05) is "0", it outputs an analog level of 0.7.

According to such a configuration, the memory (101).

(201) bit pattern data is stored in memory (10
5).

(205') and drawing is performed on the display (132), and at this time, the memory (105')
).

The data in (205) is weighted by the table (131) and supplied to the display (132), so
The brightness of the pixel (3) is corrected and angeliasing is performed.

And in this case, in particular, according to this invention, the memory
(101), (201") selection of drawing pattern, generation of drawing address for memory (101), (201"), barrel shifter (102')
It is only necessary to set the shift amount for ~ (203) and transfer the bit block, and the bit block transfer only needs to be done once (1 cycle), so the memory (105),
Drawing can be performed at high speed up to the speed limited by the cycle time of the read/modify/write mode (205).

Also, at this time, the memory (101”), (20
Since the data in 1) also includes information on anchoraging, no time is required for anchoraging processing during drawing, and there is no reduction in drawing speed due to anchoraging processing.

Next, we will consider possible problems with straight lines drawn by the above method.

First, pattern memory (101), (201
), and the starting points of the straight lines in each block (IB) are as shown in FIG. 4. However, in this figure, 36
Auxiliary grids (
11) is assumed. Moreover, the straight line BL is the boundary line of the block (IB).

Points S1 to S4 and E1 to E1 are the starting points and ending points required for straight lines with various slopes. For example, if a straight line is drawn with points S2 and El2 as the starting and ending points, the slope will be 7/31. It becomes a diagonal line.

In other words, if any of the points S1 to S4 is taken as the starting point of a straight line, the straight line S2 El and the straight line S2'E39 will not appear in the first quadrant considered as the X axis and the Y axis, so other blocks (IB ), and all straight lines with positive slopes can be expressed by setting any of the points E1 to E39 as the end point. Note that for a straight line with a negative slope, the pattern may be reversed.

Furthermore, in order to increase the drawing efficiency, if the inclination of the straight line is greater than 45°, point Sd, and if the inclination of the straight line is less than 45°, points Sa and Sb may be selected as starting point candidates.

Note that the capacity of each of the memories (101) and (201) may be the same as when the unarchealing process is not executed, which is 4 points x 39 points - 156 patterns - 9984 bits.

Next, blocks (IB) and (IB) of memory (101) and (201) are transferred to memory (105) and
Memory when bit block is transferred to (205)
(105).

Block (IB) in (205), (1[1
), there may be a problem when the end point is near the corner of the block (IB).

When considering cases that meet this condition, there are cases shown in FIGS. 5A to 5C. In other words, A and B in the same figure
In the case of , no particular problem arises with respect to the connection between blocks A and B. In the case of C in the same figure, there is no problem by shifting block B by one lattice.

Therefore, in any case, by clearly indicating the next point to start drawing, drawing can be performed smoothly. namely, memory (101).

As soon as the pattern (201) is selected, the next starting point becomes clear, so it is only necessary to select a pattern that has a matched ending point.

Furthermore, blocks (IB) and (IB) of memory (101) and (201) are transferred to memory (105) and
(205') to draw a straight line, so the memory (105).

(205) There is a possibility that a straight line becomes a broken line at the boundary BL between a block (IB) and an adjacent block (IB).

So, how big is the actual line, that is,
FIG. 6 shows a study of how much error occurs. In addition, in the same figure, the thick line (5) is the pixel (3)
Figure A is a drawing drawn using the grid (11), Figure B is a diagram derived from the target straight line (4), and Figure C is a straight line (broken line) drawn using the grid (11). ) This is a drawing limited to the top.

According to this figure, 1/2 of the interval of the grid (11)
There may be some deviation, but this error is smaller than when the antialiasing process is not performed.

In particular, when 2000 x 2000 pixels are displayed on a 20 x 20 inch screen, the resolution is 4 lines/-, and the error of this 1/2 grid is 8 lines/1III, which poses no problem at all in practice.

Note that in the above, the memories (101) and (201
) may be used as a RAM, and necessary pattern data may be written into it using DDA or the like.

Effects of the invention H According to this invention, memories (101), (201
) selection of a drawing pattern, memory (101).

All that is required is generation of the drawing address for (201), setting of the shift amount for barrel shifters (102) to (203), and bit block transfer. ), drawing can be performed at high speed up to the speed limited by the cycle time of the read-modify-write mode (205).

Also, at this time, the memories (101) and (201
) data also includes information on anchoraging, so no time is required for anchoraging processing during drawing, and there is no reduction in drawing speed due to anchoraging processing.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 to 14 are diagrams for proving the same. +1), (11) are grid points, (2), (12) are grid points, (3). (13) is a pixel.

Claims (1)

[Scope of Claims] A plurality of pattern memories each having a plurality of blocks of the same size as a plurality of display memory blocks are provided, and a block at a predetermined block address of the plurality of pattern memories is provided. The data of the desired pattern is extracted in sets, the extracted sets of data are transferred in bit blocks to each of the plurality of display memories mentioned above through the barrel shifter, and the data in these plurality of display memories are weighted. A drawing method in a bitmap display system in which drawing data is obtained by using a 3D display, and this drawing data is supplied to a raster scan type display to perform drawing that has been subjected to anti-aliasing processing.