JPS63197252A - Electronic computer - Google Patents

Abstract

PURPOSE:To easily obtain an electronic computer containing a cache memory by converting a logic address into an n-bit physical address (n: an integer of >=2) and using a part of an output signal of the n-bit physical address to decide the selection or non-selection of the cache memory. CONSTITUTION:When the logic address is converted into a physical address by a memory managing unit MMU13, a bit of conversion information corresponding to the page number of the logic address is read out of a main memory 3. Then the page number held by the memory 3 is used as the page number of the physical address corresponding to the page number of the logic address. The most significant bit of the output signal of the physical address is inputted to a cache memory control means 16 in a cache memory 12 as a cache memory control signal 15. When this signal 15 goes to 0, the memory 12 is set under a selection state and then in a non-selection state when the signal 15 goes to 1 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an electronic computer equipped with a cache memory.

Conventional Technology To improve the performance of electronic computers, high-speed storage, which holds data accessed by processors, is used.
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L±M;'1 x column m (rIP-'IVe is placed. However, for example, in a computer with a direct memory access file 2C or below, referred to as a DMA controller), the DMA controller also accesses the main memory, so Data in main memory may be changed without the processor accessing main memory. That is, a mismatch occurs between the data held in the cache memory and the data in the main storage device. In addition, an electronic computer with a multiprocessor configuration (multiprocessor system)
In some cases, multiple programs that share main memory are executed on separate processors, resulting in data mismatch between caches and between cache and main memory.

One method for resolving such data mismatches is to prohibit data in an address space accessed by multiple devices such as processors and DMA controllers from being held in the cache memory.

In a multiprocessor system, it is desirable to be able to map data shared by multiple processors to any address within the logical address space of each processor. Therefore, for example, in a multiprocessor system that performs memory management using the paging method, the conversion information (C page table entry) provided for each page to obtain the physical address from the logical address is stored together with the physical page number of the page for cache memory control. It also holds bits. When converting an address from a logical address to a physical address, the memory management unit (hereinafter referred to as MMU) outputs a cache memory selection signal as a signal different from the address signal according to the value of the cache memory control bit, and It controlled memory selection and non-selection states.

Problems to be Solved by the Invention However, the conventional method described above has a problem in that it cannot be applied to a processor that has a built-in MMU but does not have the function of outputting a cache memory control signal. Particularly when the processor is a microprocessor, this poses a serious problem because it is impossible for the user of the microprocessor to modify the built-in MMU.

The present invention has been made in view of such problems, and is applicable to MMUs that do not have the function of outputting cache memory control signals.
To provide an electronic computer capable of controlling the selection and non-selection states of a cache memory even for a built-in processor using a part of a physical address converted and output corresponding to a space designated by a logical address. The purpose is to

Means for Solving the Problems The present invention provides a processor having memory management means for converting and outputting a logical address into an n-bit physical address (n is an integer of 2 or more), and an output signal of the n-bit physical address. and a cache memory control means that determines a selected or non-selected state of the cache memory using a part of the output signal of the n-bit physical address.

For production The effects of the present invention are as follows.

During address conversion, the processor uses built-in memory management means to convert a logical address into a physical address and outputs it as an address signal. The selected and non-selected states of the cache memory are controlled using part of the address signal as a control signal.

Embodiment FIG. 1 is a block diagram showing an embodiment of the electronic computer of the present invention. The system has a multiprocessor configuration in which a plurality of equivalent processor modules 1.2 and a main memory 3 are connected to a system bus 4.

Each processor module 1.2 comprises a processor 11 and a cache memory 12. The processor 11 has a built-in MMU 13 that supports virtual memory using a paging method.

The MMU 13 converts the logical address into a physical address in page units of 4 bytes in size, and outputs this physical address to the system bus 4 as an address signal 14.

The bit configurations of logical addresses and physical addresses are of the same type, and the width of these addresses is 32 bits. The lower 12 bits (A11 to AO) are the intra-page offset, and the upper 20 bits (A31 to A12) are the page number. In other words, the address space is 1 mega (=2
It is divided into 2') pages and managed. Furthermore, conversion information C (page table entry) is provided for each page, and this page table entry is held in the main storage device 3.

Each conversion information (page table entry) is composed of a page number 21 and page information 22 as shown in FIG. When converting a logical address to a physical address by the MMU 13, first the conversion information (page table entry) corresponding to the page number of the logical address is read from the main storage device 3, and the page number held therein is read out from the main storage device 3. is generated as the page number of the physical address corresponding to the page number of this logical address.

The layer upper bit A31 of the output signal of this physical address is used as the cache memory control signal 15, and the cache memory 1
The data is input to the cache memory control means 16 in 2. When this cache memory control signal 16 is 0, the cache memory 12 is in the selected state, and when it is 1, the cache memory 12 is in the selected state.
becomes unselected. Also, the lower 3 of this physical address
1 bit (A30 to Ao) is access address signal 1
7. ゛ It is input to the cache memory 12 and used for accessing the cache memory 12.

As described above, even for processors with a built-in MMU that do not have the function of outputting cache memory control signals,
It is possible to control the selection and non-selection states of the cache memory by using a part of the physical address converted and output to the space designated by the logical address as a control signal.

Effects of the Invention As described above, according to the present invention, even for a processor with a built-in MMU that does not have the function of outputting a cache memory control signal, a cache memory control signal can be converted and output to a space specified by a logical address. Since the physical invention controls the selection and non-selection states of the cache memory by address signals, only a small amount of hardware is added. Therefore,
The present invention is extremely effective in easily realizing an electronic computer having a cache memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic computer according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of conversion information (page table entries) in the computer. 1.2...Processor module, 11...
...Processor, 12...Cache memory, 13...Memory management unit, 14...
. . . Physical address signal, 15 . . . Cache memory control signal, 16 . . . Cache memory control means.

Claims (1)

[Claims] a processor having memory management means for converting and outputting a logical address to an n-bit physical address (n is an integer of 2 or more); a cache memory accessed using an output signal of the n-bit physical address; and a cache memory that is accessed using an output signal of the n-bit physical address; cache memory control means for determining a selected or non-selected state of the cache memory using a part of the output signal of the physical address of the computer.