JP2570361B2 - Storage control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a storage control method capable of improving the processing capability of a computer system, a storage control method that improves the performance of a processing device by maximizing a page mode function of a storage element is described. A normal mode in which all address bits are designated for access, and a page mode in which, for a storage area specified in advance by a predetermined portion of the address bits, access is performed by specifying only an address in the storage area. In the control of the data read access of the storage element having
Holding means for holding the predetermined portion of the address bits; comparing means for outputting a signal indicating whether the content held in the holding means at the start of access matches the predetermined portion; Control means for starting access in the page mode in parallel with the operation of the means, and switching to access in the normal mode when the signal indicating mismatch is output from the comparing means.

[Industrial applications]

The present invention relates to a storage control method that can improve the processing capability of a computer system.

In recent years, computers have been applied to all fields of technology and business. In computer processing, a processing unit reads and executes instructions and operands from a main storage device, and thus the performance thereof is greatly affected by the speed of a memory element used. However, a high-speed memory device consumes a large amount of power and is expensive, and a storage control method that can efficiently use a given memory device and improve the performance of a computer system is desired.

[Conventional technology]

FIG. 4 is a timing chart showing a conventional example. The same reference numerals indicate the same objects throughout the drawings.

Dynamic RAM (hereinafter referred to as DRAM) accesses include normal mode access and page mode access. For example, DRAM with a storage capacity of 16,384 words
In the access in the normal mode, the upper 8 bits of the address 16 bits are output as a row address to specify a required storage area, and then the lower 8 bits are output as a column address to specify a target address. . On the other hand, in the access in the page mode, the same storage area (hereinafter, referred to as the upper 8 bits specified in the address) is used.
In the case of specifying an address within a page, a high-speed memory access can be performed by outputting only the column address and specifying the address. Therefore, in the access control of the main memory of the processing device that stores the program in which most of the instructions are executed in the order of arrangement in the page, the access in the page mode is effective. In order to utilize this positively, it is determined whether the address requested for access is within the same page as the previous access, and if it is within the same page, access is performed in the page mode. When the pages are not in the same page, the access in the normal mode is executed. That is, in FIG. 4, in the determination cycle at the start of memory access, it is determined whether or not the upper 8 bits of the address specify the same page as that of the previous access. If not, the access in the normal mode shown in FIG. Is executed, and when the pages are the same, the access is executed in the page mode shown in FIG.

In FIG. 4A, when it is determined in the determination cycle at the start of access that the access is not for the same page as the turn, the upper eight addresses are determined in the address designation cycle.
The bits are output as a row address (indicated by R in the figure), the lower 8 bits are output as a column address (indicated by C in the figure), and the timing signals * RAS and By outputting * CAS, data is read in an access cycle, a check such as parity check is performed, and a signal indicating read data “valid” (hereinafter, referred to as a ready signal) is output to the processing device.

In FIG. 4 (b), when it is determined in the determination cycle that the access is to the same page as the previous time, * CAS is controlled while the * RAS is kept low in the addressing cycle, and only the column address is output. Thereby, data is read in an access cycle and a ready signal is output.

[Problems to be solved by the invention]

As described above, according to the conventional method, the determination cycle for determining whether the current access specifies the same page as the previous access is effective in increasing the speed of the processing device by utilizing the high-speed access in the page mode. However, since it takes time for each memory access, there is a problem that the performance of the processing device cannot be sufficiently improved.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a storage control method that maximizes the page mode function of a storage element to improve the performance of a processing device.

[Means for solving the problem]

 FIG. 1 is a block diagram showing the principle of the present invention.

In the figure, reference numeral 1 denotes a normal mode in which all address bits are specified and accessed, and a page mode in which, for a storage area specified in advance by a predetermined portion of the address bits, access is performed by specifying only an address in the storage area. 2 is holding means for holding the predetermined portion of the address bits for each access, and 3 is whether or not the content held in the holding means 2 at the start of access matches the predetermined portion. The comparison means 4 outputs a signal indicating the page mode in parallel with the operation of the comparison means 3, and switches to the access in the normal mode when the signal indicating the mismatch is output from the comparison means 3. Means.

[Action]

According to the present invention, the holding means 2 holds a predetermined part of the address bit every time the storage element 1 is accessed, and the comparison means 3 requests access to the contents held in the holding means 2 at the start of access. Comparing a bit of the address with the predetermined portion to output a signal indicating match / mismatch;
The control means 4 starts access in the page mode in parallel with the comparison operation of the comparison means 3, and switches to access in the normal mode when the non-match signal is output from the comparison means 3, so that the match signal is output from the comparison means 3. In such a case, the time required for the comparing operation of the comparing means 3 can be substantially reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 2 and 3. FIG. The same reference numerals indicate the same objects throughout the drawings.
In FIG. 2, those corresponding to FIG. 1 are surrounded by alternate long and short dash lines.

In FIG. 2, a DRAM 1a is a dynamic RAM having the same function and configuration as the DRAM described in the conventional example and having a page mode function, and outputs read data by read access.

At the end of the access cycle to the DRAM 1a, the latch circuit 2a stores the upper 8 bits A00 of the addresses A00 to A15 (A00: MSB, A15: LSB) from the microprocessor (hereinafter referred to as MPU) 10.
~ A07 is latched and held.

At the start of access, the comparison circuit 3a compares the address bits held in the latch circuit 2a during the previous access with A00 to A07 input from the MPU 10, and outputs a match / mismatch signal based on the comparison result.

The timing control circuit 4a switches the row address corresponding to A00 to A07 and the column address corresponding to A08 to A15 from the MPU 10 and outputs the switched address. The RAS generator generates the row address timing signal * RAS. 41, CAS generator that generates timing signal * CAS for column address
42, etc. at the start of access, that is, the comparison circuit 3a
The addressing cycle is executed in parallel with the comparison operation to perform high-speed access in the page mode (refer to the addressing cycle in FIG. 4 (b)). Read data “valid”
Is output, and when a mismatch signal is input, the ready signal is not output and the addressing cycle is executed again to access in the normal mode (see the addressing cycle in FIG. 4 (a)). And outputs a ready signal together with the read data.

In the timing chart of the embodiment of the present invention shown in FIG. 3, the operation of the present invention is shown in comparison with the timing of the conventional example.

In parallel with the comparison operation (judgment cycle) of the comparison circuit 3a,
The timing control circuit 4a executes an addressing cycle to perform high-speed access in the page mode, and
When the match signal is output, a ready signal is output to the MPU 10 together with the read data in the access cycle.

When the result of the comparison (judgment cycle) by the comparison circuit 3a executed in parallel with the page mode addressing cycle does not match, the ready mode is not output and the addressing cycle is executed again to access in the normal mode. Then, a ready signal is output to the MPU 10 together with the read data in the access cycle.

Therefore, as is apparent from FIG. 3, when the designated page of the current access differs from the designated page of the previous access, such as when the program crosses a page boundary, the time required for the memory access of the embodiment of the present invention is the same as the conventional example. In the case of (and) an access within the same page that occupies most of the program execution, the time required for the conventional determination cycle is substantially reduced according to the present invention. The processing capacity of the MPU 10 was correspondingly increased, and in one application example, the performance of the processing device could be improved by several tens of percent.

In the present embodiment, an example in which the MPU is applied to the main memory has been described. However, the present invention can be applied to other systems in a similar manner, and has a remarkable effect particularly in a system in which accesses are continuous within the same page.

〔The invention's effect〕

As described above, according to the present invention, the time required to determine whether the current access is the same page designation as the previous access is reduced, and the page mode access function of the storage element DRAM1a is fully utilized. This has the effect that the instruction execution speed of the processing device MPU10 can be shortened and the performance of the computer system can be improved.

[Brief description of the drawings]

 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a timing chart of the embodiment of the present invention, and FIG. 4 is a timing chart showing a conventional example. . In the figure, 1 is a storage element, 1a is a DRAM, 2 is a holding unit, 2a is a latch circuit, 3 is a comparing unit, 3a is a comparing circuit, 4 is a control unit, 4a is a timing control circuit, 41 is a RAS generation unit, 42 Indicates a CAS generator, 43 indicates an address generator, and 10 indicates an MPU.

Claims (1)

(57) [Claims] 1. A normal mode in which all address bits are specified for access, and a page mode in which, for a storage area specified in advance by a predetermined portion of the address bits, access is performed by specifying only an address in the storage area. In the control of the data read access of the storage element (1), the holding means (2) for holding the predetermined portion of the address bits for each access, and the contents held in the holding means (2) at the start of the access And a comparing means (3) for outputting a signal indicating whether or not the predetermined part matches or does not match. In parallel with the operation of the comparing means (3), the access in the page mode is started, A control unit for switching to access in the normal mode when the signal indicating the mismatch is output from (3). That the storage control system.