JPS63193747A - Repeater - Google Patents

Abstract

PURPOSE:To exactly recognize a data from its first bit even when an NRZ signal generating asynchronously is encoded and transmitted, by providing control means at a data generating part and a data reproducing part respectively. CONSTITUTION:The data generating part is provided with a first limiting means 7 which stops a conversion operation after the NRZ signal is generated and a desired time elapses, and the data reproducing part is provided with a second limiting means 8 which stops a reproducing operation after an RZ signal to be reproduced is received and the desired time elapses. Thus, by providing the first and the second limiting means 7 and 8 in a repeater, it is possible to recognize the data exactly from the first bit by the repeater at a reception side even when the NRZ signal generated asynchronously is encoded and transmitted in a system in which the repeaters are connected in multiple stages.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a repeater in an information network, and more particularly to a repeater having a timing regeneration function.

[Prior art] LA where a large number of terminals are connected in a bus type, ring type, etc.
In local area networks (N), the waveform distortion of each repeater is added over multiple stages, resulting in deterioration of transmission quality. Therefore, a timing regenerator section is installed in the repeater (3R type repeater) to ensure correct signal transmission. We are trying to

FIG. 3 is a schematic configuration diagram of a conventional repeater.

In the figure, an NRZ signal S1 asynchronously generated from a terminal device such as a personal computer is inputted into a data generation section by a data acquisition circuit 1, encoded by a code conversion circuit 2, and sent as an RZ signal S2 from a transmission circuit 3 to a transmission path. sent to.

On the other hand, R transmitted from another terminal device through the transmission path
The Z signal S3 is sent to the timing recovery circuit 5 through the reception circuit 4.
and input to the reproduction circuit 6.

The timing regeneration circuit 5 inputs the RZ signal S3 and regenerates the timing clock CLK, and the regeneration circuit 6 inputs the RZ signal S3.
The RZ signal S3 is converted into an NRZ signal S4 based on LK.

[Problems to be Solved by the Invention] However, in the conventional repeater described above, when asynchronously occurring asynchronous signals are encoded and transmitted, due to the sign rule of the code, on the receiving side there is a difference between several bits. However, there was a problem in that the data could not be recognized correctly. The details will be explained below.

FIG. 4 is a timing chart in the case of CMI encoding. However, here, for convenience of explanation, the transmitting side and the receiving side are described together, but signals S1 and S2 are for the data generation section of the terminal device on the transmitting side, and signals S3 and S4 are for another terminal device on the receiving side. Each of the data reproducing units is shown in FIG.

Furthermore, as an example, the asynchronously generated signal S1 is R3-
232C signal, the signal S1 that is CMI coded and transmitted is called a CMI transmission signal S2, the received signal S2 is called a CMI received signal S3, and the signal S3 is reproduced as a reproduced R3-232C signal S4. .

In FIG. 4, since the R5-232C signal S1 is generated asynchronously, the transmitter's R5-232C data clock may be discontinuous at the start portion A of the signal S1. Such a signal S1 is CMI encoded and transmitted as a signal S2.

On the receiving side, the CMI coded signal S3 is input to the data reproducing section, and the timing reproducing circuit 5 synchronizes at the rising edge of the signal S3 and performs timing regeneration.

However, depending on the generation timing of the R3-232C signal S1, the CMI encoded signal S2 and signal S3 may not rise for several bits. In this case, the timing regeneration circuit 5 outputs the timing clock CLK of the previous signal.

At that timing, the reproducing circuit 6 operates (B in Fig. 4).
part).

For this reason, the reproducing circuit 6 cannot correctly reproduce data for several bits, resulting in a reproduced signal S4 different from the original R5-232C signal S1.

[Means for Solving the Problems] The repeater according to the present invention has the following features:
A data generation unit that converts the Z-fold signal and transmits it, and the received R
In a repeater comprising a data reproducing section that regenerates an NRZ signal from a JRZ signal by regenerating the timing of the Z-fold signal.

The data generation section includes first limiting means for stopping the conversion operation after a predetermined time has elapsed since the NRZ signal was generated.

The data reproducing section is characterized in that it has a second limiting means that stops the reproducing operation after a desired time has elapsed after receiving the RZ-multiplied signal to be reproduced.

[Function] By providing the first and second limiting means in the repeater,
Therefore, in a system in which multiple repeaters are connected, even when asynchronously generated NRZ signals are encoded and transmitted, the receiving repeater can correctly recognize the data from the first bit.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of a repeater according to the present invention.

In the figure, an NRZ signal S1 asynchronously generated from a terminal device such as a personal computer is input into a data generation section by a data acquisition circuit 1, and is encoded by a code conversion circuit 2. Further, the data length limiting circuit 7 sets the limiting signal LSI to a high level only for a predetermined number of data or a period corresponding to it when the NRZ signal S1 is generated.
Output to code conversion circuit 2.

The code conversion circuit 2 performs the code conversion operation only while the limit signal LS is at a high level, and sends the NRZ signal S1 as the RZ signal S2 from the transmission circuit 3 to the transmission line. When the limit signal LSI becomes low level after a certain period of time has elapsed, the code conversion circuit 2 is reset.

For this reason, the start bits of the encoded transmission signal S2 and reception signal S3 are always "1" or "0", and the data reproducing section can synchronize with the rise or fall of the reception signal S3. ” On the other hand, R transmitted from another terminal device through the transmission path
The Z signal S3 is sent to the timing recovery circuit 5 through the reception circuit 4.
and input to the reproduction circuit 6.

The timing regeneration circuit 5 inputs the RZ signal S3 and regenerates the timing clock CLK, but as described above, since resynchronization can be applied at the edge of the signal S3,
The correct timing clock CLK can be reproduced from the start bit.

Further, the clock CLK is input to the data length limiting circuit 8,
The data length limiting circuit 8 outputs the limiting signal LS2 to a high level to the reproducing circuit 6 only for a predetermined number of data or a period corresponding thereto.

The reproduction circuit 6 operates only when the limit signal LS2 is at a high level, and converts the RZ signal S3 into the NRZ signal S4 based on the -clock CLK. When the limit signal LS2 becomes low level, the reproduction circuit 6 is reset.

For this reason, the regeneration circuit 6 never operates at the timing of the previous signal, and the regeneration circuit 6 always receives the received NR signal S.
The reproducing operation is performed at the timing when the NRZ signal s4 is reproduced from 3. Therefore, it is possible to accurately reproduce the NRZ signal s4.

FIG. 2 is a timing chart of this embodiment in the case of CMI encoding. However, here, as in the case of FIG. 4, the transmitting side and the receiving side are shown together.

Furthermore, as an example, the asynchronously generated signal S1 is R3-
232C signal, the signal S1 is converted into CMI code and transmitted as a CMI-coded transmission signal S2, and the received signal S2 is converted into a CMI-coded reception signal S3. The reproduced signal S3 is referred to as a reproduced R3-232C signal S4.

In FIG. 2, since the R5-232C signal S1 is generated asynchronously, the transmitting R3-232C data clock may be discontinuous at the start portion A of the signal S1. However, the code conversion circuit 2 operates only while the limit signal LSI from the data length limit circuit 7 is at a high level.

The start bit of the CMI coded signal S2 is always a rising edge.

On the receiving side, the CMI coded signal S3 is input to the data reproducing section, and the timing reproducing circuit 5 resynchronizes at the rising edge of the start bit of the signal S3 and regenerates the timing clock CLK. Regenerated clock C
LK is output to the reproducing circuit 6.

Since the reproduction circuit 6 operates only while the limit signal LS2 is at a high level, it is not affected by the clock of the previous signal.
The regeneration operation is performed based on the clock CLK which is resynchronized at the rising edge of the received CMI coded signal S3. For this purpose, the R5-232G signal S1 on the transmitting side is converted into the regenerated R5-232C signal S4 which has been correctly regenerated. Obtainable.

Note that although this example shows the case of CMI encoding,
RZ that can reproduce the timing of DMI, Dipulse, etc.
If there is a double signal, the present invention is applicable.

[Effects of the Invention] As explained in detail above, the repeater according to the present invention provides restriction means in each of the data generation section and the reproduction section, thereby suppressing NRZ that occurs asynchronously in a system in which repeaters are connected in multiple stages. Even if the signal is encoded and transmitted, it is possible to correctly recognize the data from the first bit.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an embodiment of a repeater according to the present invention. FIG. 2 is a timing chart of this embodiment in the case of CMI encoding. FIG. 3 is a schematic diagram of a conventional repeater. The configuration diagram, Figure 4, is C
It is a timing chart when converted into MI code. 2...Code conversion circuit 5...Timing regeneration circuit 6--Regeneration circuit 7-Data-data length restriction circuit 8-φ-Data length restriction circuit Agent Patent attorney Jo Taira Yamashita Figure 1 Figure 3 Tenge playback Ondo

Claims (2)

[Claims] (1) A data generation unit that converts an asynchronously generated NRZ signal into an RZ signal whose timing can be reproduced and transmits it, and a data reproduction unit that reproduces the NRZ signal from the received RZ signal by reproducing the timing from the RZ signal. In the repeater, the data generating section has a limiting means for stopping the conversion operation after a predetermined time has elapsed since the generation of the NRZ signal, and the data reproducing section receives the RZ signal to be reproduced. A repeater comprising second limiting means for stopping the regeneration operation after a predetermined period of time has elapsed. (2) The first limiting means stops the conversion operation after a period corresponding to the data length of the RZ signal to be transmitted has elapsed, and the second limiting means controls the data of the NRZ signal to be reproduced. Claim 1, characterized in that the reproducing operation is stopped after a period corresponding to a long time has elapsed.
Repeater as described in section.