JPS63192149A - Data bus controller - Google Patents

Abstract

PURPOSE:To prevent an oscillation phenomenon on a data bus by setting a flip-flop FF when a memory read signal outputted from a CPU is active and then resetting the FF when the output of a gate circuit is inactive. CONSTITUTION:An FF25 is set when the memory read signal outputted from a CPU 1 is active and then reset when the output of a gate circuit 26 is inactive respectively. Therefore, the conducting direction of a bidirectional driver 15 is fixed in a read mode before the output control signal given to the driver 15. At the same time, the fixed conducting direction is kept even after the output control signal is inactive and the driver 15 is cut off. Thus the driver 15 conducts only in the direction where the driver 15 moves toward the CPU 1 from a peripheral circuit in the read mode. As a result, an oscillation phenome non is prevented on a data bus 7.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention provides a CPU (CPU) in a microcomputer etc.
The present invention relates to a data bus control device that performs connection/disconnection control and direction control of a bidirectional data bus that connects a central processing unit (central processing unit) and peripheral devices such as memory circuits.

[Prior Art] FIG. 4 shows a block diagram of an example of a general configuration of a microcomputer. As shown in FIG. 4, this microcombi 1-1 connects the CP IJ 1 and peripheral circuits such as a memory circuit WR2, an input/output circuit 3, and an interface circuit 4 via a bus 5.

FIG. 5 is a block diagram specifically showing the bus 5 connected to CPLll. Bus 5 is on the 5th floor! As shown in FIG. 4, there are three types of busses: a unidirectional address bus 6, a bidirectional (1) channel bus 7, and an m-directional control bus 8, and the control bus 8 is related to the present invention. Memory read signal line 8a and memory write signal line 8b
Only shown in the diagram.

The bidirectional data bus 7 allows data D to flow in the direction of input to CPLJI when the CPU is in the red mode;
When IJI is in write mode, data ■ flows in the direction from the CPUI. Address AD and memory read signal M
EMR and memory write signals M P, M W always flow in the direction out of CP LJ 1.

Fig. 6 is a time chart in read mode and write mode in the microcomputer shown in Figs. , (c) show the memory write signal MEMW, and (d) show the data D, respectively.

In read mode, this microcomputer uses C
PIJI outputs a predetermined address A1), and this address selects, for example, memory circuit 2 among the peripheral circuits. After that, when the memory read signal MIMR becomes low level, data D is sent from the selected memory circuit 2.
is output, and this data D appears on the data bus 7.

This data D becomes stable after the access time of the memory circuit 2 has elapsed after the memory read signals MP and MR become low level, and is stored in the internal register of CPLJI just before the memory read signal MEMR becomes high level. Loaded. Then, after memory read No. 48 MEMR becomes high level, the output of data 100 from the memory circuit 2 ends.

On the other hand, in the write mode, CPLll outputs a predetermined address AD, and the memory circuit 2, for example, among the peripheral circuits is selected by this address AD. After this, at the same time that the memory write signal MEMW becomes low level, the CPU
Data D is output from I onto the data bus 7. Then, the output of data D from t&cpυl, where the memory write signal 114RMW becomes high level, ends. Normally, data is written to the memory circuit 2 at the timing when the memory write signal MaMW switches from low level to high level.

In addition, in FIG. 6(d), the data base is output from the memory circuit 2 which is a peripheral circuit, and the data base]2 is output from the CPUI
It is output from

In addition, the read operation and write operation by the CPUI can be performed by changing the address 5 of the input/output circuit 3.
This can also be done for the interface circuit 4.

As mentioned above, in a microcomputer, the direction in which 100 data flows is reversed between read mode and write mode, and it is difficult to correctly transfer 100 data between cput and, for example, memory circuit VtTl2. , address A
Data that controls connection and disconnection between the data bus 7 and, for example, a data input terminal of the memory circuit 2, and the direction in which the data 5 flows, based on the memory read signal M1 and the memory write signals MP and MW. It is necessary to provide a bus control device, and peripheral circuits such as the memory circuit 2 are configured to include a data bus control device.

FIG. 7 shows a concrete block diagram of the microcomputer shown in FIG. 4. However, illustration of the input/output circuit 3 and the interface circuit 4 is omitted.

As shown in FIG.
PU 1 and memory circuit 1/32 are connected by address bus 6, data bus 7 and control bus 8 (only memory read signal line 8a and memory write signal line 8b are shown).

The address AD given to the peripheral circuit through the address bus 6 is composed of, for example, the upper 2 bits of the peripheral Ifil path selection address and the lower 14 bits of the data storage location address, and the data D passing through the data bus 7 is
is, for example, 8 bits.

The memory circuit 2 connects the address bus 6 to the input end of a signal inverter 11, connects the lower 14 bits of the output end of the inverter 11 to the address input end of the RAM 12, and connects the output end of the inverter 11 to the address input end of the RAM 12. The upper two bits are connected to one input terminal of the comparator 13, and the other input terminal of the comparator 13 is connected to the setter 1 for setting the address for peripheral circuit selection.
The output end of 4 is connected.

Further, the data bus 7 is connected to one input/output end of the bidirectional driver 15, and the other input/output end of the bidirectional driver 15 is connected to the data input/output end of the RAM 12.

In addition, the memory read signal line 8a is connected to r! through the buffer 16. It is connected to the memory read signal input end of the AM 12, and the memory write signal line 8b is connected to the memory write signal input end of the RAM 12 via the buffer 17.

In addition, the output terminal of the comparison '/%13 is connected to the bidirectional driver 15.
is connected to the output control signal input terminal of buffer 1.
6 is connected to the direction control signal input width of the bidirectional driver 15.

In the above-mentioned microcomputer, the comparator 13, the setting device 14. Bidirectional driver 15 constitutes a data bus controller.

8 and 9 are time charts showing the operation of the microcombi shown in FIG. 7 during the overnight write mode and the read mode. In Figure 8, (a) is cp
(b) is the memory read signal M L' M l? output from u i through the address bus 6, and (b) is the memory read signal M L' M l? which is also output through the memory read signal line 8a.
, (C) is the memory write signal MEMW which is also output through the memory write signal line 8b, (d) is the data 1 which is also output through the data bus 7, (6)
is address A input to RAM 12 and comparator 13
(f) is the output of the comparator 113, that is, the output control signal OC input to the bidirectional driver 15, and (g) is the direction control signal DIR input to the bidirectional driver 15.
In other words, the read signal l? input to the RAM 12? of,(
h) is I? Each shows a write signal W input to AM12. In addition, in FIG. 9, (a) is the CPU
Address AD output from I through address bus 6
, (b) shows the memory read signal M E M R outputted through the memory read signal line 8a, (C) shows the memory write signal M Li M W outputted through the memory write signal line 8b, and (d ) is RAMI
2 and the address AD input to the comparison 813, (e
') is the output T of the comparator 13, that is, the bidirectional driver 1
5, (fl is the direction control signal DIR input to the bidirectional driver 15, that is, the read signal positive input to the RAM 12, and (g) is the output control signal σ input to the bidirectional driver 15.
Write signal W input to M12, (h) is RAM1
The data D output from 2 is shown respectively.

Here, the operation of the microcomputer shown in FIG. 7 in the write mode will be explained with reference to FIG.

When address AD is output from CP tJ 1, address AD is input to RAM 12 and comparator 13 a little later. Furthermore, the memory read signal M8MR output from the CPUI remains at a high level, so the read signal (4-π) input to the RAMI 2 also remains at a high level, and is further input to the bidirectional driver 15. The direction control signal M) DIR also remains at high level.

When the upper bit of address 80 is input to the comparison n13, if the upper focus of this address AD matches the output of the setter 14, the output Y of the comparator 13 becomes low level, and therefore the bidirectional driver 15 output control signals QC
becomes low level.

At this time, what direction? Since the l111 control signal DIR is at high level, the bidirectional driver 15 conducts from the CPUI to the RAM 12 from the moment the output control signal QC becomes low level.

After address 80 is output from CP tJ l, CI
) Memory write signal M I? output from U I? ,
MW becomes low level, and at the same time data D is output from the CPUI. Memory write signal M)? ,
When MW goes to low level, RA is activated a little later than this.
The write signal W input to M12 becomes low level.

At this time, since the bidirectional driver 15 is conducting,
Data ■ is inverted by bidirectional driver 15 and stored in RAM1.
It is input as data D to the data input/output terminal of No.2.

After this, the memory write signal MEMW becomes high level, and a little later, the write signal W becomes high level, and when this write signal W changes from low level to high level, the location specified by address ^D of RAM 12 Data D is written to.

After this, after a certain period of time has passed, the data completion output from the CPUI disappears, the address AD also no longer corresponds to the memory circuit 2, the output of the comparator 13 becomes high level, and therefore the output control signal of the bidirectional driver 15 The signal τ becomes high level, and the bidirectional driver 15 is cut off.

Next, referring to Fig. 9, see the 71st! i! ! The operation of the I microcomputer in read mode will be explained.

When address AD is output from CP [11, address A is sent to RAM 12 and comparison 113 a little later.
D is input. In addition, the memory write signal MEMW output from CP tJ 1 remains at high level,
Therefore, the write signal W input to the RAM 12 also remains at high level. In addition, memory read signal M F
, M R is at high level, and the bidirectional driver 15
Direction control signal Dlr? is also at a high level.

When the high-order bits of the address AD are input to the comparator 13, if the high-order bits of the address AD match the output of the setter 13, the output Y of the comparator 13 becomes low level, thus indicating bidirectionality. The output control signal of the driver 15 becomes low level.

At this time, since the direction control signals r) and lR are at high level, the output? From the moment when the Iil+ control signal OC becomes low level, the bidirectional driver 15 transfers data from the CPU 1 to the RAM.
Conductive in 12 directions.

After address AD is output from CP tJ 1, CP
[Memory read signal M F output from J1,
When MR becomes low level, the direction control signal DIR and read signal R become low level at time t1, which is a little later than this, and from this point on, the conduction direction of the bidirectional driver 15 is reversed, and the address AD in the RAM 12 is Access for reading the designated location begins, and data D begins to be output. Note that data D is unstable during the access time immediately after time (I, and becomes stable after the access time ends. This data D is input to tIIcPUI, which is inverted by the bidirectional driver 15.

The CPU reads data 100 into the internal register immediately before changing the memory read signals M P and M R to high level. When the memory read signal MEMR becomes high level, the direction control signals DIR and M R are read at time t2, which is a little later than this. Read signal R becomes high level. As a result, the conduction direction of the bidirectional driver 15 immediately returns to its original state, and the output of data D from the RAM 12 stops at time t3, which is further delayed than time (2).

After this, the address does not correspond to the memory circuit 2, and the output Y of the comparison 1113 becomes high level.Therefore, the output 1M control signal 5 of the bidirectional driver 15 becomes high level, and the bidirectional driver 15 is blocked.

[N points to be solved by the invention] In the conventional micro combinator data bus control device described above, the read signal τ input to the rlAM 12 is directly sent to the bidirectional driver 15 as the direction control signal DI.
In addition, the output of the comparator 13 is directly applied to the bidirectional driver 15 as the output control signal 5τ, so in the read mode, the output control signal OC goes to low level (
Since the bidirectional driver 15 first conducts from the CPUI to the RAM 12, and then from the RAM 12 to the CPUI, Then from the CPUI? Conductive in the direction of AM12,
I will have to cut off the t&, and I will have to change the direction of Dogo-dori.

When the bidirectional driver 15 first becomes conductive in the direction from the CPUI to the RAM 12, there is no problem because the read signal k is not at a low level and the RAM 12 is not accessed.
When the bidirectional driver 15 conducts in the direction of M12, the following problem occurs. That is, even if the positive read signal becomes high level at time t2, the RAM 12 remains unused until time t3.
continues to output data D, and at this time the bidirectional driver 15 conducts from the CPU to the RAM 12, so the data D and RAM 12 that are going to go out from cput through the data bus 7 continue to output. There is a problem in that a collision occurs with the data D that is being used, and unnecessary oscillation occurs on the data bus 7, making it impossible to access the RAM 12 normally next time.

An object of the present invention is to provide a data bus control device that can prevent data collisions on the data bus 7.

[Means for solving the gap]

The data bus control device of the present invention includes a bidirectional driver inserted in a bidirectional data bus that connects a CPU and peripheral elements, and a bidirectional driver that is set at the timing when a memory read signal output from the CPU becomes active. A set state output is sent from the peripheral element to the bidirectional driver to the CP.
A direction control signal is provided as a direction control signal for specifying the direction toward the LJ as the conduction direction, and a direction control for determining tFr of the reset state output to the bidirectional driver with the direction from the CPU to the peripheral element as the conduction direction. a flip-flop to be given as a signal; and a memory that is output from the CPU when a set state output is generated from the flip-flop and the memory read signal becomes active, and when a reset state output is generated from the flip-flop. a gate circuit that activates an output when a write signal becomes active and provides it as an output control signal for making the bidirectional driver conductive; and resets the flip-flop when the output becomes inactive; It is equipped with

(Operation) According to the data bus control device of the present invention, the flip-flop is set at the timing when the memory read signal output from the CPU becomes active, and the output of the set state of the flip-flop is sent to the bidirectional driver. It is given as a direction control signal to specify the direction from the circuit to the CPU as the conduction direction, and the output of the reset state of the flip-flop is sent to the bidirectional driver as the direction control signal.
It is given as a direction control signal to designate the direction from U to the peripheral circuit as the conduction direction, and when the set state output from the flip-flop occurs and the memory read signal becomes active, and when the flip-flop outputs the reset state. When an output is generated and the memory write signal becomes active, the gate circuit activates the output and provides it as an output control signal to the bidirectional driver to make it conductive, and the output of the gate circuit becomes inactive. In read mode, the conduction direction of the bidirectional driver for reading is determined before the output control signal applied to the bidirectional driver becomes active, and the flip-flop is reset when the flip-flop is reset. Continuity direction determination can be maintained until after the signal becomes inactive and the bidirectional driver is shut off. Therefore, in the read mode, the bidirectional driver conducts only in the direction from the peripheral circuit to the CPU, and even though data is being output from the peripheral circuit as in the conventional example, the bidirectional driver conducts from CI) tJ to the peripheral circuit. Since conduction does not occur in the direction toward the data bus, data collision on the data bus can be prevented, and oscillation phenomenon on the data bus can be prevented.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 1 to 3. This data bus control device is comprised of a bidirectional driver 15, a flip-flop 25, and a gate circuit 26, as shown in FIG.

The bidirectional driver 15 includes a CPU l and peripheral elements r? It is inserted into the bidirectional data bus 7 that connects with AM12.

The flip-flop 25 is set at the timing when the memory read signal MEMR output from the CPUI becomes active, and outputs the set state to the bidirectional driver 15.
A direction control signal DI for specifying the direction from the RAM 12, which is a peripheral element, toward the CPU as the conduction direction.
The output of the reset state is sent to the bidirectional driver 15 from the CP 131 to the peripheral element R.
It is given as a direction control signal DIR for specifying the direction toward AM12 as the conduction direction.

The gate circuit 26 generates a set state output from the flip-flop 25 and receives a memory read signal M L': M
When R becomes active, a reset state output is generated from the flip-flop 25, and the memory write signal "F, MW" output from the CPU becomes active, the output is set to 7 tapes and the bidirectional driver is activated. The flip-flop 25 is given as an output control signal (2) to make it conductive to the flip-flop 25, and when this output becomes inactive, the flip-flop 25 is reset.

A microcomputer including a data bus control device will be described below with reference to the drawings. As shown in FIG.
These are connected by an address bus 61, a data bus 7, and a control bus 8, as in the conventional example.

The memory circuit 2' includes an inverter 11. M 12° comparison to R'/, 413. Settings a14 and bidirectional driver 1
5. The inverters 16 and 17 are the same as the conventional example, and this configuration includes a flip-flop 25 consisting of a NOR gate 20, 21, a gate circuit 26 consisting of an AND gate 22, 23, and a NOR gate 24, and an AND gate 18.1.
9 has been added.

The flip-flop 25 and the gate circuit 26 have the above-mentioned functions, and the AND gates 18 and 19 have the address AD.
The memory read signal M
EM r? and memory write signal MEMW to RAM
12 and a flip-flop 25.

FIGS. 2 and 3 are time charts showing the operation of the microcombination unit shown in FIG. 1 in write mode and read mode. In Figure 2, (a) is CPt
Address A output from Jl through address bus 6
(b) is the memory read signal MEMR that will soon be output through the memory read signal line 8a, (C) is the memory write signal MEMW that will also be output through the memory write signal line 8b, and (d) is the same. (6) is the address AD input to the RAM 12 and the comparator 13, ([) is the output Y of the comparator 13, (g) is the lead input to the RAM 12. (h) is the write signal W input to the RAM 12, (翫) is the direction control signal DIR input to the bidirectional driver 15, (J) is the bidirectional driver 15.
In FIG. 3, (1) shows the address AD output from the CPU through the address bus 6, and (b) also shows the memory read signal line 8a. (C) is the memory write signal MRMW outputted through the memory write signal line 8b, (d) is the RAM 12 and the comparison P:
10) is the address AD input to the comparator 1.
(f,) is the read signal π input to the RAM 12, (g) is the write signal W input to the RAM 12, and (h) is the direction control input to the bidirectional driver 15. (1) is the output control signal C input to the bidirectional driver 15, (J) is I? A
Data D output from M12 is shown.

Here, the operation of the microcomputer shown in FIG. 1 in the write mode will be explained with reference to FIG. tJJ2.

When the address AD is output from the CPUI, the address An is input to the RAM 12 and the comparator 13 a little later.

When the upper bits of the address ^D are input to the comparator 13, if the upper bits of this address AD match the output of the setter 14, the output Y of the comparator 513 becomes low level, and J7'- ) 18.19 conducts, and the memory read signal MEM11 and the memory write signal MEM
W is input to the flip-flop 25 and is also input to the RAM 12 through imparks 16 and 17. At this time, the memory read signal WτV positive output from the CPUI remains at a high level (inactive), so F? The read signal positive input to AMl 2 also remains at high level. Also, since the flip-flop 25 is in the reset state, the direction control signal T)1
11 also remains at a high level.

After the address AD consisting of CPUI is output, the CPU
Memory write signals M L and MW output from CPU 1 become low level (active), and data D is output from CPU 1 at the same time. Memory write signal MP, MW
When becomes low level, RAM12
The write signal W input to becomes low level. As a result, the output control signal O input to the bidirectional driver 15
C becomes low level (active), the bidirectional driver 15 conducts from the CPU 1 to the RAM 12, and the data ■ is inverted by the bidirectional driver 15 and transferred to R MI2.
The data is human-powered as data D.

After this, memory write No. 13 Ml;, MW becomes high level (inactive), and a little later than this, the write signal W becomes high level, and this write IN%W
When changes from low level to high level, t? Data D is written to the location designated by address AD of I2.

Further, as the write signal W becomes high level, the output control signal QC becomes high level (inactive), and the bidirectional driver 15 performs 'IXVfft.

After this, after a certain period of time has passed, the data τ is no longer output from the CPU 1, and the address A1) is also output from the memory circuit 2.
The output Y of the comparison 'I513 becomes high level, and the AND gates 18 and 19 are cut off.

Next, referring to FIG. 3, the operation of the microcomputer shown in FIG. 1 in the board mode will be explained.

When the address AD is output from the CPUI, the address An is input to the RAM 12 and the comparator 13 a little later.

When the upper bits of the address AD are input to the comparator 113, if the upper bits of this address ΔD match the output of the setter 13, the output Y of the comparator 13 becomes low level, and the AND gate 18.19 is turned on. The memory read signal MEMR and the memory write signal MgMW are electrically connected to the flip-flop 25 and the inverter 16.17.
It will be input to the RAM 12 through. On this occasion,
Memory write signal MEM output from CP LJ 1
W remains at a high level (inactive), and therefore the write signal W input to the RAM 12 also remains at a high level. Furthermore, since the memory read signal MEMR is still at a high level (inactive) and the flip-flop 25 is in a reset state, the direction control signal DI
R is also at a high level.

After address AD is output from cput, CPLII
When the memory read signal MIEMR output from the memory read signal MIEMR becomes low level (active), the read signal positive becomes low level a little later than this, and from this point on, the RAM 12 is accessed and data D starts to be output, and after a little delay, direction? t, II message~) o+n becomes low level, and - becomes low level (active) with this single output control signal δ, and the bidirectional driver 15 becomes RA
Conducting from M12 to CPU1, data D is inverted by bidirectional driver 15 and data π is transferred to CP IJ l.
is entered as .

cput reads data D into the internal register immediately before changing the memory read signal M E M IJ to high level (inactive), a memory read signal M Fi M
When R becomes high level, a little later than this, the read signal I? becomes high level. As a result, the output control signal OC becomes high level and the bidirectional driver 15 is cut off. Then, when the output control signal QC becomes high level, the flip-flop 25 is reset, and the direction control signal DIR returns to high level.

Thereafter, the output of data D from the RAM 12 is stopped.

After this, the address AD does not correspond to the memory circuit 2, the output Y of the comparator 13 becomes high level, and the gates 18 and 19 are cut off.

Note that the flip-flop 25 is also reset by the output of the gate 19.

In this embodiment, the flip-flop 25 is set at the timing (falling edge) when the memory read signal MEMR output from the CPUI becomes active, and the output of the set state of the flip-flop 25 is sent to the bidirectional driver 15 to the RAM 12. The direction control signal DIR (low level) is provided to specify the direction from the CPU 1 to the CPU as the conduction direction, and the output of the reset state of the flip-flop 25 is sent to the bidirectional driver 15 to specify the direction from the CPU 1 to the RAM 12 as the conduction direction. Direction control signal DI+? (high level),
And when the flip-flop 25 generates a set state output and the memory read signal πτM R, /+<active (low level), the flip-flop 25 generates a reset state output and the memory write signal M
When L(MW becomes active (low level), the gate circuit 26 activates the output and makes the output conductive to the bidirectional driver 15.
Since the flip-flop 25 is reset when the output of the gate circuit 26 becomes inactive, the conduction direction of the bidirectional driver 15 for reading is set to active (
Low level) output control signal τ or bidirectional driver 1
It is possible to maintain the conduction direction value in a fixed state until the output control signal S becomes inactive (high level) and the bidirectional driver 15 is cut off. Therefore, in the read mode, the bidirectional driver 15 conducts only in the direction from the RAM 12 to the CPU, and even though data D is output from the RAM 12 as in the conventional example, the bidirectional driver 15
Since there is no conduction in the direction from t to the RAM 12, data collision on the data bus 7 can be prevented, oscillation phenomenon on the data bus 7 can be prevented, and access can be performed normally.

In the above embodiment, a case has been described in which the peripheral element is the RAM 12, but it may be a ROM or an input/output element other than a memory.

〔Effect of the invention〕

According to the data bus control device of the present invention, the flip-flop is set at the timing when the memory read signal output from the CPU becomes active, and the output of the set state of the flip-flop is sent to the bidirectional driver from the peripheral circuit to the CPU. The direction control signal is given as a direction control signal to determine the direction toward trt as the conduction direction, and the direction control signal is used to specify the reset state output of the flip-flop to the bidirectional driver in the direction from the CPU to the peripheral circuit as the conduction direction. The gate is applied as a signal, and when a set state output from the flip-flop occurs and the memory read signal becomes active, and when a reset state output occurs from the flip-flop and the memory write signal becomes active. The circuit activates the output and gives it as an output control signal to make it conductive to the bidirectional driver, and the flip-flop is reset when the output of the gate circuit becomes inactive, so in read mode. The conduction direction of the bidirectional driver for reading is determined before the output control signal applied to the bidirectional driver becomes active, and the conduction continues until the output control signal becomes inactive and the bidirectional driver is cut off. A direction-determined state can be maintained. Therefore, in the read mode, the bidirectional driver conducts only in the direction from the peripheral circuit to the CPU, and even though data is being output from the peripheral circuit as in the conventional example, the bidirectional driver conducts from the CPU to the peripheral circuit. There is no conduction in the direction, preventing data collision on the data bus, and preventing oscillation on the data bus.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart in its write mode, Fig. 3 is a time chart in its read mode, and Fig. 4 is an example of a conventional microcomputer. Schematic block diagram of 5th
The figure is a block diagram showing the configuration of the bus, Figure 6 is its time chart, Figure 7 is a block diagram showing the specific configuration of Figure 4, and Figures 8 and 9 are time charts showing its operation. be. 1...CPU, 7...Data bus, 12...RA
M. 15...Bidirectional driver, 25...Flif-buf flow control, 26...Gate circuit (Figure 4) Figure 5A /% /% /hook-1)
, Ω υ ・0 Fig. 8

Claims (1)

[Claims] A bidirectional driver inserted in a bidirectional data bus that connects a CPU and peripheral elements, and a set state that is set at the timing when a memory read signal output from the CPU becomes active. output from the peripheral element to the bidirectional driver to the CP
A direction control signal is provided as a direction control signal for specifying a direction toward U as a conduction direction, and a direction control signal for specifying a reset state output to the bidirectional driver as a direction from the CPU toward the peripheral element. and a memory write signal output from the CPU when a set state output is generated from the flip-flop and the memory read signal becomes active, and a reset state output is generated from the flip-flop. a gate circuit that activates an output when the output becomes active and provides it as an output control signal for making the bidirectional driver conductive, and resets the flip-flop when the output becomes inactive. Data bus controller.