JPS63191977A - Method and device for generating test pattern for memory ic - Google Patents

Abstract

PURPOSE:To easily generate a complicate test pattern by computing the offsets of the address of a test cell and the address of a corresponding disturbing cell and combining those computed values. CONSTITUTION:Constant values to be supplied to counters 3 and 4 are stored in constant registers 1 and 2 of arithmetic means 100 and 101 for elements of the test pattern. The counters 3 and 4 counts up or down the constant values fetched from the registers 1 and 2 and supply their counted values to a combination arithmetic means 200 for the elements. Then the means 200 combines the elements by controlling AND gates 5-1-5-n, and 6-1-6-n, exclusive OR gates 7-1-7-n, and 8-1-8-n and +1/PASS circuits 9 and 10 with control signals 50, 51, 52, and 53, and an adder P adds them. Consequently, the complicate pattern is easily generated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a test pattern generation method and a generation device for testing a memory IC, and in particular, to a test pattern generation method and a generation device, which make it possible to easily generate a complicated pattern. This invention relates to a test pattern generation method and generation device.

[Conventional technology]

Conventional test pattern generators include, for example, the Japanese Patent Publication No. 57-5
As described in No. 2679, a plurality of fixed registers storing initial values and a value stored in any one of these fixed registers are selected and imported, and
It is equipped with a plurality of arithmetic circuits that perform arithmetic operations based on the captured values, and a plurality of arithmetic registers that select and capture the output of any one of these arithmetic circuits, and tests the memory IC from these plurality of output registers. I was starting to get a pattern.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, all the test addresses of the memory IC are treated as unified, and when the test pattern is generated, the address of the test cell of interest and the address of the disturb cell are The address value of must be calculated in the calculation register,
There is a problem in that the arithmetic instructions given to these arithmetic registers become more complicated than necessary.

In a memory IC test pattern, the address of a disturb cell is usually defined by its relative position to the address of the first test cell of interest. That is, it is necessary to successively generate addresses of disturb cells located at specific relative positions with respect to the address of the test cell of interest. Hereinafter, the address of the test cell will be referred to as a test address, and the address of the disturb cell will be referred to as a disturb address.

FIG. 2 shows a general procedure for generating test patterns. First, in step 1, write data to all addresses, initialize the test address and initialize the disturb address (offset; relative value, that is, the displacement of the address with respect to the test address), then in step 2, Write data 1 to the test address, then read data 1 from the test address. Next, in Step 1, data is read from the disturb address, and in Step 5, data 1 is read from the test address, the disturb address (offset) is updated, and the process returns to Step 4 and repeats Steps 4 and 5. When all the disturb addresses are finished, exit and go to step 6, write the data to the test address, update the test address, disturb address (offset)
, go back to step 2, and repeat steps 2 to 6. When all test addresses are completed, the process exits and the test of the memory IC is completed.

In such a test pattern generation procedure, when returning from step 6 to step 2, it is necessary to initialize the disturb address and update the test address. At this time, if the disturb address is defined as a value relative to the test address, the arithmetic register that is computing the disturb address requires multiple steps to compute the initial position of the disturb address with respect to the updated test address. It is impossible to calculate in one step. In complex patterns, dummy cycles are likely to occur due to insufficient computing power in this part.

As a specific example, FIG. 3 schematically shows the movement of the calculation register when a test pattern is generated. Here, the operation of the arithmetic register when a test pattern is generated for test addresses "100" and "101" is shown assuming that two addresses before and after the test address are disturb cells.

In the figure, O and 口 indicate the movement of a register for calculating a test address or a disturb address.

0 indicates the movement of the arithmetic register with respect to the test address ``100'', and the opening indicates the movement of the arithmetic register with respect to the test address ``101''.

That is, first, address 10, which is the first test cell,
To test the 0 disturb cell, go to the address 98 two places before the test address 100, then go to the address 99 one place before the test address 100, then go to the address one place after the test address 100. Go to 101,
Next, address 102 two places after test address 100
go to Next, in order to similarly test the next test cell, the disturb cell at address 101, go to address 99, which is two places before test address 101, and then
Go to the previous address 100, then go to the next address 102, and then go to the second address 103.

In this way, it can be clearly seen how the computation of the disturb address is more complicated than the computation of the test address. This is because the conventional arithmetic unit configuration is [disturb address = test address + offset (relative value; displacement)]
This is due to a lack of recognition that test addresses and disturb addresses are all handled in a unified manner, and the address value itself must be calculated in one of the calculation registers, making the calculation instructions more complicated than necessary. .

An object of the present invention is to provide an arithmetic unit configuration that focuses on the constituent elements of the address of a test pattern, and to provide a test pattern generation method and a generation device for a memory C that enables the generation of complex patterns more easily. be.

[Means for solving problems]

In order to achieve the above object, the present invention includes two calculation means.
First, the first calculation means calculates the constituent elements of the test pattern to be output, and then the second calculation means combines the individual pattern elements calculated by the first calculation means and calculates the necessary This is achieved by calculating the output cover pattern.

That is, the test pattern generation method of the present invention includes a first step of calculating components of a test pattern to be output, and a second step of combining the calculated individual components, and , is characterized in that the above combined results are output as a test pattern for the memory C to be tested.

Further, the pattern generation device of the present invention includes a first calculation means for calculating the constituent elements of the test pattern to be output, a second calculation means for combining the calculated individual constituent elements, and a combination of the above-mentioned combinations. The present invention is characterized by comprising an output means for outputting the results as a test pattern for the memory C to be tested.

The first calculation means includes, for example, at least one register capable of storing an initial value and a plurality of counters capable of arbitrarily taking in the initial value, and the second The calculation means is comprised of an arithmetic and logic operation circuit to which arbitrary outputs of the plurality of counters are input.

Further, in place of the counter, an arithmetic unit (arithmetic circuit) that can arbitrarily take in the initial value, and a second register that takes in the output of the arithmetic unit, and the second
The output of the register may be fed back to the arithmetic unit and input to the arithmetic and logic circuit.

FIG. 1 is a conceptual diagram showing a basic configuration example of the present invention. In the figure, 100, 101, . . . are calculation means (first calculation means) for the constituent elements of the test pattern, and 200 is a combination calculation means (second calculation means) for each component.

[Effect]

With the above configuration, the calculation of the address of the disturb cell is performed by calculating the absolute value of the address of the test cell and the offset (relative value) of the address of the disturb cell with respect to the address of the test cell, respectively, in the first calculation step or calculation means. The second calculation means performs addition and subtraction between the calculated values of each component calculated by the first calculation means. In this way, you can individually specify the address value of the test cell, the offset value, and the operation between them, which are the individual elements that make up the address of the disturb cell, so you can create a very simple program. Therefore, it becomes possible to easily generate complex patterns.

Furthermore, in the present invention, since the arithmetic process or arithmetic means has a two-stage configuration, the functional burden on the arithmetic circuit that requires a feedback path in the first arithmetic process or arithmetic means can be reduced, and the second arithmetic process or arithmetic means can be operated in two stages. Since the arithmetic unit without a feedback path in the means can be made highly functional, speeding up can be achieved.

〔Example〕

Embodiment 1 FIG. 4 is a block diagram showing a first embodiment of the present invention.

In this embodiment, a case where a test pattern is generated using two test pattern components will be described as an example. Therefore, as shown in FIG. 4, the test pattern generator of this embodiment includes two test pattern component calculation means (first calculation means) 100 and 101, and a combination calculation of each component. It consists of means (second calculation means) 200. , 1.2 is a constant register, 3.4 is a counter, and this counter 3.4 is used for UP count and DO
It is assumed that it is possible to import WN counts and constant values. Constant register 1.2 stores a constant value given to counter 3.4. Constant register 1.2
and counter 3.4 constitute calculation means 100, 101 for the constituent elements of the test pattern, respectively. 5
-'i to 5-n and 6-1 to 6-n are AND gates, 7-1 to 7-n and 8-1 to 8-n are exclusive OR gates, 5o, 51.52.53 are control Signal, 9.1
0 is +1/PASS circuit.

11 is an adder. AND gates 5-1 to 5-n, 6
-1 to 6-n can each mask the output of the counter 3.4 and force all bits to be true according to the control signal 50.51. Exclusive OR gate 7-1~
7-n, 8-1 to 8-n can each invert the output of the counter 3.4 according to the control signal 52.53. +1/PASS circuit 9.10 increases +1 when inversion is performed by exclusive OR gates 7-1 to 7-n and 8-1 to 8-n in the previous stage, and remains unchanged when inversion is not performed. Outputs the value of . The adder 11 adds the inputs of both the calculation means 100 and 101 of the two pattern constituent elements and outputs the sum. Assuming that the output value of the counter 3 is A, the output value of the counter 4 is B, and the output value of the adder 11 is P, in order to set P=A, the control signal 51 is set to H'' (1), and the remaining control signal 50, 52, and 53 should all be set to "L". Also, to set P=A-B, control signals 50, 51, and 52 should be set to I.
I L II and the control signal 53 is It HIt. Similarly, the control signal is a Hu or 14 L It
Various functions can be realized by setting the value of . This is shown in the operational function table in Table 1.

Table 1 First, in order to generate a disturb address for the test address "100" explained in FIG.
The counter 4 generates a test address, and the counter 4 generates the absolute offset value of the disturb address from the test address. That is, in this example, the counter 4 is 2, 1,
1,2;2,1゜1.2;... and (2,1,1
, 2] may be repeatedly generated. This can be generated by setting the initial value of the counter 4 to 2 and subsequently using only -1, +, and +1 instructions. Furthermore, the output instruction is changed to P when the disturb address is before the test address.
The test pattern shown in Figure 2 can be generated by simply setting =A-B and then setting P=A+B.
It's very simple.

In this way, in this embodiment, the disturb address can be separated into the test address and offset components, and arithmetic instructions can be given to each of them separately.
Complex patterns can be generated very easily.

In the above description, the pattern has two constituent elements, but the present invention is not limited to this, and it is clear that any number of constituent elements may be prepared.

Furthermore, although the types of operations have been explained limited to arithmetic operations, logical operations are of course also possible. This is particularly effective in generating data test patterns for memory ICs.

Further, in the above embodiment, one constant register 1.2 is provided for each counter 3.4, but even higher functionality can be achieved by using a plurality of constant registers 1.2.

Further, in the above embodiment, the counter 3.4 is used as a means for generating pattern constituent elements, but the invention is not limited to this.
By using an arithmetic unit (arithmetic circuit) and an arithmetic register, it becomes easier to generate even more complex patterns.

This embodiment will be explained next.

Embodiment 2 FIG. 5 is a block diagram showing a second embodiment of the present invention. In the figure, 12.13 is an arithmetic unit, and 14.15 is a register. As shown in FIG.
The outputs of 5 are fed back to arithmetic units 12 and 13, respectively, and are input to an arithmetic and logic operation circuit 200. These arithmetic units 12, ]3 and registers 14.1
5 is the counter 3 in the first embodiment shown in FIG.
．． It performs the same function as 4.

Other configurations, operations, and effects are similar to those of the first embodiment.

〔Effect of the invention〕

As explained above, according to the present invention, since the configuration is such that a test pattern is calculated for each element and then a desired pattern is calculated by combining these elements, the program for generating the test pattern becomes very simple and complex. It is also possible to generate patterns with great ease.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram for explaining the present invention in detail, FIG. 2 is a diagram showing a pattern calculation procedure, FIG. 3 is a diagram showing an example of generation of a disturb address, and FIG. FIG. 5 is a block diagram showing a second embodiment of the present invention. 1.2... Constant register 3.4... Counter 5-1 to 5-n, 6-1 to 6-n = #kND gate 7
-1 to 7-n, 8-1 to 8-n...Exclusive OR gate 9.10...+1/PASS circuit 11...Adder 12.13...Arithmetic unit 14.15... ··register

Claims (1)

[Claims] 1. A first step for calculating the constituent elements of the test pattern to be output.
and a second step of combining the calculated individual components, and outputting the result of the combination as a test pattern of the memory IC under test. test pattern generation method. 2. The first step to calculate the components of the test pattern to be output.
A second calculating means for combining the calculated individual components, and an output means for outputting the combined result as a test pattern of the memory IC under test. Memory IC test pattern generator. 3. The first calculation means is composed of at least one register that can store an initial value and a plurality of counters that can arbitrarily take in the initial value,
The memory according to claim 2, wherein the second calculation means is constituted by an arithmetic and logic operation circuit into which an arbitrary output of at least one of the plurality of counters is input. IC test pattern generator. 4. The first calculation means includes at least one first register that can store an initial value, a calculation unit that can arbitrarily take in the initial value, and an output of the calculation unit. It consists of a second register to take in, and the second
The arithmetic means comprises an arithmetic and logic circuit to which an arbitrary output of at least one of the plurality of counters is input, and the output of the second register is fed back to the arithmetic unit, and the arithmetic and logic 3. A test pattern generator for a memory IC according to claim 2, wherein the test pattern generator is configured to input the test pattern to an arithmetic circuit.