JPS63191723U

JPS63191723U -

Info

Publication number: JPS63191723U
Application number: JP2750888U
Authority: JP
Priority date: 1988-03-03
Filing date: 1988-03-03
Publication date: 1988-12-09

Description

[Brief explanation of the drawing]

第１図は従来のデイジタルフイルタのブロツク
図、第２図は本考案によるデイジタルフイルタの
ブロツク図、第３図はテーブルメモリ回路のブロ
ツク図、第４図は本考案によるデイジタルフイル
タの別の実施例のブロツク図、第５図は従来のデ
イジタルフイルタの別のブロツク図、第６図は本
考案によるデイジタルフイルタの更に別に実施例
のブロツク図である。１１，１４……シフトレジスタ、１３……加算
器、１２１〜１２ｎ，１５１〜１５ｍ……テーブ
ルメモリ回路。 FIG. 1 is a block diagram of a conventional digital filter, FIG. 2 is a block diagram of a digital filter according to the present invention, FIG. 3 is a block diagram of a table memory circuit, and FIG. 4 is another embodiment of a digital filter according to the present invention. 5 is another block diagram of a conventional digital filter, and FIG. 6 is a block diagram of yet another embodiment of the digital filter according to the present invention. 11, 14...Shift register, 13...Adder, 121-12n, 151-15m...Table memory circuit.

Claims

[Claims for Utility Model Registration] (1) A first shift register having multiple stages for sequentially delaying and storing input digital signals;
a first multiplier that multiplies the contents of each stage of the shift register by a predetermined value, an adder that adds all the outputs of the first multiplier to provide a digital filter output; a second shift register that sequentially delays and stores output through a plurality of stages; a second multiplier that multiplies the contents of each stage of the second shift register by a predetermined value;
and means for applying the output of the second multiplier to the input of the adder, the numerical value represented by the output code word of each stage of the shift register in place of the first and second multipliers. and a read-only memory in which a numerical value obtained by multiplying by a predetermined coefficient is stored as a code word, and the contents of each stage of the first and second shift registers are stored in the read-only memory in code word units. A digital filter characterized in that it is applied to each of the read-only memories as a memory address, and each numerical value stored in each of the read-only memories is read out and supplied to the adder. (2) The digital filter according to claim (1) of claim 1, wherein the read-only memory only performs multiplication of absolute values, and multiplication of codes is performed by a separately provided polarity separation circuit and polarity synthesis circuit. . (3) The digital filter according to claim (1), wherein the read-only memory is a common collective memory for each stage of the shift register.