JPS63190559A - Rectifier circuit - Google Patents
Rectifier circuitInfo
- Publication number
- JPS63190559A JPS63190559A JP1984587A JP1984587A JPS63190559A JP S63190559 A JPS63190559 A JP S63190559A JP 1984587 A JP1984587 A JP 1984587A JP 1984587 A JP1984587 A JP 1984587A JP S63190559 A JPS63190559 A JP S63190559A
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- resistor
- rectifier circuit
- power source
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 1
Landscapes
- Rectifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、整流回路に関し、特に整流時の電圧降下が小
さく、損失が小さい、し九がって、低電圧の整流に適す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a rectifier circuit, and in particular, the voltage drop and loss during rectification are small, and therefore it is suitable for low voltage rectification.
〔従来の技術〕
従来、整流回路は整流ダイオードを使用しているので、
約ＩＶの電圧降：Ｆｔ−生じ、ＩＡ、ｌ＋九シ約ＩＷの
損失がろう九。[Conventional technology] Conventionally, rectifier circuits use rectifier diodes, so
A voltage drop of approximately IV: Ft- will result, and a loss of approximately IW will occur in IA, l+9.
し九がって、従来の！ｖＲ１路は、大電流の電流では放
熱全考慮する必要があり、まｔ前記電圧降下のため、低
電圧の交流電源の整流には、不晴当であつｔｏ
〔問題点ｔ−解決する丸めの手段〕
本発明による＠流回路は、１個のＭＯＳＦＥＴの片端に
、抵抗の片端を接続しＭＯ８ＰＥ’ｊ’の他端と、負荷
抵抗の他４ｔ−交流電源に接続し次回ｖｑｒｔ−基本回
路とし、その負荷抵抗の両端を出力とし九整流回路であ
る。However, conventional! The vR1 path is unsuitable for rectifying low-voltage AC power supplies because of the voltage drop, which requires consideration of heat dissipation at large currents. Means] In the @flow circuit according to the present invention, one end of a resistor is connected to one end of one MOSFET, and the other end of MO8PE'j' is connected to a 4t AC power source in addition to a load resistor, and the next time vqrt is used as a basic circuit. , it is a nine rectifier circuit with outputs at both ends of the load resistance.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.
ｌは抵抗、２は交流電源、・３は直流電源、４ａはＭＯ
ＳＦＥＴ、４ｂはＭＯＳＦＥＴの寄生ダイオード、５は
址抗、６ａは発光ダイオード、６ｂは発光ダイオードと
結合されたホトトランジスタ、７は抵抗である。l is resistance, 2 is AC power supply, 3 is DC power supply, 4a is MO
SFET, 4b is a parasitic diode of the MOSFET, 5 is a resistor, 6a is a light emitting diode, 6b is a phototransistor coupled to the light emitting diode, and 7 is a resistor.
図においてＭ（ＪＳ、ｆ；”Ｆ、Ｔ４ａのドレインに、
正電圧が印加される交流電源２の極性においては、抵抗
５を通じて、発光ダイオード６８に電流が流れ点燈する
ので、６１のホトトランジスタが（ＪＮＬＡＩＡＵＳＦ
ＥＴ４ａのゲート・ソース間を短絡する。そのタメ、Ｍ
ＯＳＦＥＴ４ａは（ＪＦＦ状態であシ、抵抗ＩＫ電流は
流れない。次に、ＭＯ８ＦＥＴ４ａのドレインに、負電
圧が印加される交流電源２の極性においては、発光ダイ
オード６ａｉＣ電流が流れないため、点燈せず、６６の
ホトトランジスタはＵＦＦ状態となる。し次がってｓ
Ｍ（Ｊ Ｓ Ｆ ｈａ Ｔ ４ ａのゲート・ソース間
に直流′電源３の電圧が印加され、ＯＮし、交流電＃２
、ＭＯ８ＦＥＴ４ａ １に通じて、抵抗ｌに電流が流れ
る。ＭＯ８ＦＥＴ４ＨのＯＮ抵抗は、一般に１０数ｍ（
１以下なのが容易に得られるので、ＩＡ流した時の電圧
降下は、約０．ＯＩＶであり、ダイオードに比、ぺて、
非常に低い電圧降下になる。In the figure, M(JS,f;”F, at the drain of T4a,
In the polarity of the AC power supply 2 where a positive voltage is applied, a current flows to the light emitting diode 68 through the resistor 5 and turns on the light emitting diode 68, so that the phototransistor 61
Short-circuit the gate and source of ET4a. That charge, M
The OSFET 4a is in the JFF state, and the resistance IK current does not flow.Next, in the polarity of the AC power supply 2 where a negative voltage is applied to the drain of the MO8FET 4a, the light emitting diode 6aiC current does not flow, so the light is not turned on. First, the phototransistor 66 is in the UFF state.
The voltage of DC' power supply 3 is applied between the gate and source of M (J S F ha T 4 a, it turns on, and AC power #2
, MO8FET4a1, and a current flows through the resistor l. The ON resistance of MO8FET4H is generally about 10 m (
Since it is easy to obtain a value of 1 or less, the voltage drop when IA is applied is approximately 0. OIV, compared to a diode,
This results in a very low voltage drop.
し友がって、損失の低減による外形の小形化、低電圧交
流への適用という点で、特にすぐれｔ整流回路を提供す
るものである。Accordingly, the present invention provides a T-rectifier circuit which is particularly excellent in terms of reducing loss, reducing the external size, and applicability to low-voltage alternating current.
第２図は、本発明の他の実施例の回路図である。FIG. 2 is a circuit diagram of another embodiment of the invention.
８はＭＯＳＦＥＴである。8 is a MOSFET.
図において、ＦＥＴ４ａのドレインに、正電圧が印加さ
れる交流電源２の極性においては、 ＭＯＳＦＥＴ８が
ＯＮ ｌ、 ＭＯＳＦＥＴ４ａ のゲート、ソース間
を短絡する。そのため、ＭＯＳＦＥＴ４ａはＯＦ”Ｆ状
態であシ、抵抗ｌに電流は流れない。次に、ＭＯ８ＦＥ
Ｔ４ａのドレインに、負電圧が印加される交流電源２の
極性においては、Ｍ（ＪＳＦＥ’ｌ’８がυＦＦ状態と
なる。したがって、ＭＯ８ＦＥＴ４ａのゲート。In the figure, when the polarity of the AC power supply 2 is such that a positive voltage is applied to the drain of the FET 4a, the MOSFET 8 is ON, short-circuiting the gate and source of the MOSFET 4a. Therefore, MOSFET4a is in the OF”F state, and no current flows through the resistor l.
In the polarity of the AC power supply 2 where a negative voltage is applied to the drain of T4a, M(JSFE'l'8 is in the υFF state. Therefore, the gate of MO8FET4a.
ソース間に直流電源３の電圧が印加され、ＯＮＬ、交流
電源２、ＭＯＳＦＥＴ４ａを通じて抵抗１に電流が流れ
、実施例−と同じ動作となる。また、ＭＯ８ＦＥＴ４ａ
とＭＵＳＦＥＴｓはＰ形ＭＯＳＦＥＴｆ も実現する事
ができる。The voltage of the DC power supply 3 is applied between the sources, and current flows through the resistor 1 through the ONL, the AC power supply 2, and the MOSFET 4a, resulting in the same operation as in the embodiment. Also, MO8FET4a
And MUSFETs can also realize P-type MOSFETf.
以上説明したように本発明は、ＭＯＳＦＥＴを使用し、
整流時の電圧降下を数分の１以下にする事ができ、し念
がって、損失の低減による外形の小形化、低電圧の整流
への適用という点で、時にすぐれ友整流回路を提供でき
る効果がある。As explained above, the present invention uses MOSFET,
It is possible to reduce the voltage drop during rectification to less than a fraction of a fraction of a second, and in this regard, we offer an excellent rectifier circuit in terms of reducing loss, reducing the size of the external shape, and applying it to low-voltage rectification. There is an effect that can be achieved.
以上は負荷として抵抗を使って説明し念が、容量性、誘
尋性負荷においても、図２においては、ＭＯＳＦＥＴの
両端り蔽を検出゛して劃−している、ｔめ、１６１剥ζ
整流動作を行わせることが出来ることは明ら之である。The above explanation uses a resistor as the load, but even with capacitive and dielectric loads, in Fig. 2, the crossing of the MOSFET at both ends is detected.
It is clear that a rectifying operation can be performed.
ざらに、ＭＯ８ｋ’ＥＴ４ａ 、ＭＵＳＦｅＴ８はＮチ
ャンネルのもので以上説明し九が、ＰチャンネルのＭＯ
ＳＦＥＴを使用しても同様の効果が得られる。Roughly speaking, MO8k'ET4a and MUSFeT8 are N-channel ones, and 9 is a P-channel MO.
A similar effect can be obtained using SFET.
１・・・・・・抵抗、２・・・・・・交流を源、３・山
・・直流電源、４ ａ−−−−−−ＭＯＳＦＥＴ、４
ｂ−−−−−ＭＯＳＦＥＴの寄生ダイオード、５・・・
・・・抵抗、６ａ・・・・・・発光ダイオード、６ｂ・
・・・・・ホトトランジスタ、７・・・・・・抵抗、８
・山・・Ｍｏ５ｐＥＴＡ
ｓ１語、第１図
第２図1... Resistance, 2... AC source, 3... DC power supply, 4 a----- MOSFET, 4
b---MOSFET parasitic diode, 5...
...Resistor, 6a...Light-emitting diode, 6b.
...Phototransistor, 7...Resistor, 8
・Mountain・Mo5pETA
s1 word, Figure 1 Figure 2
Claims (1)
記ＭＯＳＦＥＴの他端と前記負荷の他端を交流電源に接
続し、前記ＭＯＳＦＥＴのドレインに正電圧が印加され
た時は、ＭＯＳＦＥＴはＯＦＦ状態となり、前記ＭＯＳ
ＦＥＴのドレインに負電圧が印加された時のみ、ＭＯＳ
ＦＥＴがＯＮする事を特徴とする整流回路。One end of a load is connected to one end of one MOSFET, the other end of the MOSFET and the other end of the load are connected to an AC power source, and when a positive voltage is applied to the drain of the MOSFET, the MOSFET is turned off. state, and the MOS
Only when a negative voltage is applied to the drain of the FET, the MOS
A rectifier circuit characterized by an FET being turned on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984587A JPS63190559A (en) | 1987-01-29 | 1987-01-29 | Rectifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984587A JPS63190559A (en) | 1987-01-29 | 1987-01-29 | Rectifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63190559A true JPS63190559A (en) | 1988-08-08 |
Family
ID=12010591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984587A Pending JPS63190559A (en) | 1987-01-29 | 1987-01-29 | Rectifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63190559A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999026354A1 (en) * | 1997-11-13 | 1999-05-27 | Rohm Co., Ltd. | Information communication device |
-
1987
- 1987-01-29 JP JP1984587A patent/JPS63190559A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999026354A1 (en) * | 1997-11-13 | 1999-05-27 | Rohm Co., Ltd. | Information communication device |
| US6464145B1 (en) | 1997-11-13 | 2002-10-15 | Rohm Co., Ltd. | Non-contact communication device |
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