JPS6319041A - Interrupting system - Google Patents

Abstract

PURPOSE:To perform an interruption processing at high speed, by providing a specific one-byte instruction code when the interruption processing is performed on a control means, and an ordinary processing is stopped, and a processing is jumped to another address. CONSTITUTION:A microprocessor 1 reads out a code from a memory 2. As a various kinds of instruction codes stored in a memory 2, there are a one-byte instruction which requires no address data, and a two-byte instruction, or a three-byte instruction which requires the address data. The microprocessor 1 judges while byte instruction code is the instruction code, and identifies which code is an instruction code, and which code is a data code, in order. As a result, it is resulted that a jump processing by a conventional three-byte instruction can be realized by the specific one-byte instruction code, and processing speed by the interruption on the processor 1 can be remarkably improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a system for performing interrupt processing on a so-called microprocessor used in, for example, an electronic computer.

BACKGROUND ART In general, an electronic computer has a storage means for storing programs, data, etc., and a control means (hereinafter abbreviated as a microprocessor) for reading out the stored contents from the storage means and performing processing such as various calculations. It consists of: The microprocessor reads programs and data stored in the storage means starting from the lowest address.
Processing will be performed sequentially. At this time, depending on the processing, there may be a case where a transition is made to various subprograms provided in relation to the main program during the processing of the main program. At this time, the address read by the microprocessor on the storage means is jumped to continue processing from the start address of the desired subprogram.

Such jump processing generally uses, for example, a 2-byte or 3-byte jump instruction.

This noyamp instruction code is, for example, ro 2+, 55
1-1.44HJ, the first code “02+J
is the jump instruction code, and the remaining code “55H1
44H'' represents the address on the storage means to which the process is transferred by the jump instruction. That is, by using such a jump instruction, which is, for example, a 3-byte instruction, in, for example, a main program, jump processing is executed in the middle of processing of the main program by the microprocessor.

Problems to be Solved by the Invention In the conventional jump processing as described above, in order to execute the jump processing, it is necessary to read a byte instruction consisting of an instruction code and a data code representing the jump destination address as described above. First, it takes a relatively long time to execute an instruction, which limits the improvement in processing speed.

An object of the present invention is to provide an interrupt method that can solve the above-mentioned problems and significantly improve processing speed.

Means for Solving the Problems The present invention comprises: a control means; a storage means in which a program etc. that defines the operation of the control means is stored; information read from the storage means; and specific command information stored in advance. determination means for determining whether the
The control means causes the discrimination means to perform the above discrimination process, and when the read information matches the specific command information, the discrimination means outputs an interrupt signal to the control means, and the control means specifies the address on the storage means from which the information is to be read. This is an interrupt method characterized by a jump.

Operation In the interrupt system according to the present invention, when the control means reads information from the storage means, this information is input to the control means and also to the determination means.

At this time, only when the information read from the storage means is command information, the control means causes the determining means to perform a process of determining whether the information matches specific command information stored in advance in the determining means.

When the read information is command information, the control means causes the discriminating means to perform a discriminating process, and when the read information matches the specific command information, the discriminating means outputs an interrupt signal to the control means. This interrupt signal causes the control means to jump to an address on the storage means from which information is to be read.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The configuration of this embodiment will be explained with reference to FIG. The configuration of this embodiment includes a microprocessor 1 as a control means, which is a central processing unit of, for example, an electronic computer.
This is a configuration related to. This microprocessor 1 stores programs or various data that define the control operations of the microprocessor 1, and has RAM (random access memory) and ROM (read only memory).
A memory 2, which is a storage means consisting of, etc., is connected by an address bus 3 and a data bus 4.

In addition, various codes that are information read from memory 2 are
The information is input via a data bus 6 to an instruction code discriminating circuit (hereinafter abbreviated as discriminating circuit) 5 which is a discriminating means. On the other hand, this discrimination circuit 5 is connected to a control line from the microprocessor 1! 1, the command 7 output signal F is output,
There is also a control line from the discrimination circuit 5! 2, an interrupt signal INT is output to the microprocessor 1.

FIG. 2 is a flowchart illustrating interrupt processing according to this embodiment. The interrupt method of this embodiment will be explained with reference to FIGS. 1 and 2.

In step n1, microprocessor 1 reads a code from a predetermined address in memory 2. Such reading of codes from the memory 2 is performed by the microprocessor 1 when the first illustrated arrangement is first powered and started.
is performed so as to start reading the code from address 0 of memory 2.

The various instruction codes stored in the memory 2 include 1-byte instructions that do not require address data as an operand of the instruction code, and 2-byte or 3-byte instructions that require such address data. When microprocessor 1 starts reading a code from address 0 of memory 2, microprocessor 1 processes the code stored at address 0 of memory 2 as an instruction code. When the microprocessor 1 reads such an instruction code, the microprocessor 1 determines how many bytes the instruction code is, and if it is a 2-byte or 3-byte instruction, it reads 1 byte from the following address. Or read 2-byte address data, etc. Thereafter, in this manner, the microprocessor 1 can sequentially identify which code on the memory 2 is an instruction code or a data food that is not an instruction code.

When the microprocessor 1 is reading the code from the memory 2 in this way, for example, after address 100, r
o 1 y , F F+ , 44)4. FF+,・
The case where the code string "..." is stored will be explained. At this time, assume that the code [01+J is a 3-byte instruction, such as an addition instruction. That is, in this case, the code string rF FH=44HJ is the data code necessary for the instruction food "01H". Furthermore, since the instruction code "01H" is identified as a 3-byte instruction in this way, the following code rFFHJ is processed as an instruction code.

Microprocessor 1 first reads 10 of the above code strings.
Read the code "01H" at address 0. Next step n2
Now, it is determined whether the read code "01H" is an instruction code. If this judgment is negative, the process returns to step n1, and the microprocessor 1
reads the code at the subsequent address. step n2
If the judgment result is affirmative in step n3, the microprocessor 1 controls the control line! 1 through instruction 7
The output signal F is output to the discrimination circuit 5. The code read from the memory 2 by the microprocessor 1 is simultaneously input to the discrimination circuit 5.

In step n4, the determination circuit 5 determines whether the code input from the memory 2 via the data bus 6 is a pre-stored specific instruction code (in this embodiment, for example, an instruction code).
'rFF, J), and a determination process is performed to determine whether or not they match. Here microprocessor 1 is memory 2
If the code read from the microprocessor 1 is a data code, the microprocessor 1 does not output the instruction 7 processing signal F to the discriminating circuit 5, so the discriminating circuit 5 does not perform such discriminating processing.

The code "01H" read from address 100 by the microprocessor 1 is determined by the microprocessor 1 to be an instruction code as described above, and therefore the instruction 7 input signal F is output to the control line 1, so that the code "01H" is determined by the discrimination circuit 5.
performs the above determination process.

At this time, the determination result is negative, the process returns to step n1, and the microprocessor 1
Reads the code “FF+J” at address 101H following the instruction code “FF+J”.
It is determined that "OIH" is a 3-byte instruction, so the determination result is negative in step n2, and the process returns to step n1 again to read the following code "44HJ" at address 102. This code r44HJ is also a data code. It is determined that there is, and the process returns to step n1 again.

When the subsequent code “FFH” is read from memory 2,
The microprocessor 1 determines that it has finished reading only 2 bytes of the data code attached to the instruction code "01H", which is a 3-byte instruction, and reads the following code rFF+J.
is determined to be an instruction code.

Therefore, the judgment in step n2 becomes affirmative, and in step n3, the microprocessor 1
outputs command 7 output signal F. step n4
The odor discrimination circuit 5 performs the discrimination processing based on the outputted command signal F.

At this time, the judgment result is affirmative, and the process proceeds to step n5.
Move to. That is, the discrimination circuit 5 outputs an interrupt signal INT to the control line 2. In step n6, the microprocessor 1 moves the processing to a jump destination address that is stored in advance as hardware in the microprocessor 1 itself, for example. After this, the process returns to step n1 again, and the microprocessor 1 starts reading the code from the new address to which it has jumped.

In this way, according to the present embodiment, a specific 1-byte instruction code can be used to jump to a jump instruction such as a 3-byte instruction, instead of reading and executing a jump instruction such as a 3-byte instruction as shown in the prior art. The process was made possible. Therefore, the processing speed of such an interrupt to the microprocessor 1 is significantly improved.

In the above-mentioned embodiment, the jump destination address to which the processing of the microprocessor 1 is transferred was explained as an address fixed as hardware in the microprocessor 1 itself, but in another embodiment of the present invention, this jump destination address is It may also be provided as software.

That is, in the flowchart shown in FIG. 2, the hardware of the microprocessor 1 may be configured so that the following processing is performed based on the input of the interrupt signal INT to the microprocessor 1 at step n5. That is, by inputting the interrupt signal INT, the microprocessor 1 starts a fetch cycle for fetching the jump destination address from the memory 2, and fetches the desired address before starting a new instruction 7 cycle. Jump to the address.

Effects As described above, according to the present invention, when interrupt processing is performed on the control means to stop normal processing and jump the processing to a new address, the program stored in the storage means, which generally consists of multiple bytes, There is no need to read and execute jump instructions, and the processing speed is greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a flowchart showing the processing operation of this embodiment. 1...Microprocessor, 2...Memory, 5...
・Discrimination circuit, F...7 command signal, INT...
Interrupt signal Figure 1 Figure 2

Claims (1)

[Scope of Claims] Control means; Storage means for storing a program etc. that defines the operation of the control means; Discrimination for determining whether information read from the storage means matches specific command information stored in advance. means, and only when the information read from the storage means is command information,
The control means causes the discrimination means to perform the above discrimination process, and when the read information matches the specific command information, the discrimination means outputs an interrupt signal to the control means, and the control means specifies the address on the storage means from which the information is to be read. An interrupt method characterized by a jump.