JPS63189896A - Image display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an image display device that performs display using a substrate on which a plurality of column electrodes are formed and a liquid crystal sandwiched between an opposing substrate. .

[Prior Art] In the field of high-density image display, an image display device shown in FIG. 37 is conventionally known. In this device, (68) is a shift register that outputs a signal to sequentially open the gates of the latches (70), and (72) is a liquid crystal display in which liquid crystal is sandwiched between a substrate on which a plurality of column electrodes are formed and a counter substrate. , (71) is a shift register that outputs a signal for sequentially selecting the pixel group (72) for each row.

(72) has an active element formed for each pixel, and (71
) selects the active element, and the signal on the column electrode is guided to the pixel electrode and stored. The pixels in that row are unselected,
That is, when the active element becomes unselected, the stored signal causes
The liquid crystal between the pixel electrode and the counter electrode at the potential of Vc is driven.* CL and Ds are the clock, data and CLe of (69).
, DG is the clock and data of (71), D is each output of (68) Ds(1), Ds(2), Da(3) ~Da
(N) 2J: ri sequential 5-/f 2'J Serial image data to be input, D(1), D(2), 0(3)
~D(N) is data transmitted from the latch in parallel to each column electrode (72), and G(1), G(2) to G(M) are signals that sequentially select the active element group for each row electrode. be. ,VOO
.

VSS is (89), (70) (7) Power input, VG,
VEE is a (71) chisel mixed input. FIG. 38 is a timing chart of each signal. Os is sequentially shifted by CL, and each shifted output Ds(1), 0s(
2), Da(3) to Ds(N) open the gate of the latch with a pulse width equal to the clock period. When image data is determined for all 1N pixels of a liquid crystal display with a frame period T, this pulse width is within TbatN).

[Problems to be Solved by the Invention] As image display devices become larger in capacity and higher in definition, the number of pixels in a liquid crystal display increases. Conventional image display devices transfer image data serially.

Data is transferred to the latch for each column electrode of the liquid crystal display by opening the gate of the latch in the column corresponding to the serial data, and the gate of the latch in that column is opened immediately before the data corresponding to the next column is input. is closed, and the gate of the next row of latches is opened. Therefore, as the number of pixels increases,
The opening time of the latch gate is shortened, and very tight timing is required to open and close the latch gate in accordance with the serially transferred image data.

[Means for Solving the Problems] The image display device of the present invention has been made to solve the above-mentioned problems, and includes a liquid crystal sandwiched between a substrate on which a plurality of column electrodes are formed and a counter substrate. An image display device that performs display using a shift register includes a peripheral circuit having a shift register and a data switch that is turned on by the output of the shift register and samples image data that is transferred in series, and the output of the shift register is overlapped in multiple columns. The data is sequentially applied to the data switches while having a period of time, and data is supplied from the peripheral circuit to the column electrodes in parallel.

For image data to be transferred serially, the data switch is turned on to start sampling at the time of the data in the previous column, and the data switch is turned off and captured just before data is transferred from that column to the next column, and the data is transferred to the shift register. The period during which the data switch is turned on by the output of is made to overlap in multiple columns, so that there is margin in the timing of sampling the image data.

FIG. 1 is a block diagram of an image display device of the present invention. ((2) is the shift register that shifts the data Da using the clock CL, (2) is the output DsR (1) of the shift register,
0s6(1), DsB(1)~Ds”(N), DsG(
N).

A data switch that samples image data [JR, [lG, [1B] turned on by DsB(N) and transferred in series, (3) a shift register that shifts data LO G with a clock CLG, and (4) a plurality of This is a liquid crystal display in which liquid crystal is sandwiched between a substrate on which column electrodes are formed and a counter substrate. Shift register (1) and data switch (
The peripheral circuit having 2) is driven by the power supply potentials voo and vss, and outputs image data pR and pG of the three primary colors of red (R), green (G), and blue (8).

QB is the output of (1) DsR(1), DsG(1), D
s”(1) ~DsR(N), DsG(N), 0sB(
Through the data switch (2), which is turned on sequentially with N),
C5R (1), C5G (1), °Cs6 (1) ~ Cs
R(N) + Cs'(N), Cs B(N
) and (4) the capacitance associated with each column electrode. (For 0, an active element is formed for each pixel,
Each stored column electrode signal DR(1), DG(1)
, DB (1) to DR (N), DG (N).

DB(N) is the output G(1), G(2) to G( of (3))
Of M), the signal of the potential ve for selecting the active element is sent to the pixel group of the row outputting and stored, and when the signal of that row becomes VEE and the active element is deselected, the stored signal causes the pixel electrode to be and drives the liquid crystal between the opposing electrodes at the potential of VC.

[Operation] FIG. 2 is a timing chart showing the operation of the image display device of the present invention. Data Ds of the shift register (1)
has a pulse width of two periods of the clock CL, and the signals with the same pulse width but shifted by the clock period are sequentially DsR(1), 0
sG (1), Ds' (1), UsR (2).

DsG(2), Os8(2) ~03R(N)IDs6
(N) and DSB(N). Image data at potentials from Vb to Va that are serially transferred to multiple data lines [lR, [lG, [1B] is D, which turns on the data switch so as to capture the image data of each data line.
s'(I) and [13G(1), Os6(1) and Ds
The output period of the potential vDD of the signal B(T) (IJ-N) is sampled overlappingly, and Ds'(I) (P-R
, G, B) until the data switch is turned off at the potential Vss of the signal and the data of the pixel group in the primary row is sampled.
stored in each column electrode.

As can be seen in the output G(1) of the shift register (3), which outputs a signal for sequentially selecting active elements row by row, the output of the shift register (1) has an overlapping period in multiple columns, and the data switch (2) ), data is supplied in parallel from one peripheral circuit to the column electrodes, and is input into each row of pixel groups.
1) IDSB (1) ~ 0sR (N), DsG (N), D
0 which continues after the sB(N) signal is output until just before the next data switch starts to turn on.
There are multiple data lines that transfer image data, and the image data that is transferred to multiple data lines at the same time is sampled overlapping periods in multiple columns by turning on the data switch, and is sampled from the column to be transferred to the next column. Since the data switch is turned off and finalized just before the image data shifts to , the pulse width for sampling when the data switch is turned on is multiple times larger than in the conventional example, and the R, G, 8
In the case of the data lines for each of the three primary colors, the data is taken into the column that transmits data to each color pixel of R, G, and H at a timing that is double C. The potential of each signal is
If the TE element of each pixel of the liquid crystal display (4) is an N-channel transistor, VE, Vss&Vb<Va≦
There is a relationship between Voo and Ve(7).

[Embodiment] FIG. 3 is a timing chart showing the operation of the first embodiment of the image display device of the present invention, and FIG. 4 is a circuit diagram showing the configuration of a shift register in the peripheral circuit of the image display device.
FIGS. 5 and 6 are circuit diagrams of clock-controlled inverters used in shift registers. In FIG. 3, the data DS of the shift register has a pulse width of two periods of clock 7 and CL, and each output of the shift register is a signal shifted by a clock period with a pulse width of 2.5 periods of clock OL. sequentially DsR(1), [1sG(1) ID5
B(1), DsR(2), 0sG(2), DsB(2
) to 0sB(N). Figure 4 shows three stages of shift registers connected in series: (J◆1) stage, (
J◆2) Shows the part of the stage. The three-stage shift register consists of a clock-controlled inverter and an inverter (5
), (8), (7), (8), (9), (10) and a NAND (11) for data switch control output, and a clock-controlled inverter (5) outputs the output 5 of the previous stage.
(J-1) is input. Output 5(J) of inverter (8) is a signal obtained by shifting 5(J-1) by one bit, and output M('') of inverter (6) is a signal obtained by shifting 5(J-1) by half a bit. The input for (8) and (9) is 14 (J).

5(J), and (11) inputs the signals M(J) and 5(J) shifted by 1 bit for each half bit, and Os(J
)-M(J)+5(J) signal is output. As shown in Figures 5 and 6, when the clock OL arrow points upward, the clock-controlled inverter is: - The clock is high (V
When it is oo), the input is inverted and output, and when it is low (Vss), it becomes high impedance. When the clock arrow points downward, the input is inverted and output when the clock is low (Vss), and the impedance becomes high when the clock is high (Vss).

The shift register is (5).

As shown in (7), (8), and (10), they are controlled by mutually inverted clocks, and when (5) and (10) are in the output state, the outputs of (7) and (8) are off. (5
), (1G) are turned off, (7) and (8) are in the output state, and the configuration is such that the signal of 5 (J-1) is statically shifted. 5 in J-1 (J-1)
is the data Ds, and the high (VDD) signal of Os is sequentially shifted in the shift register by half a bit when the clock is high and one bit when the clock is low, so Ds(J
) signal goes high (Voo) when the clock is high, turning on the data switch, and 03 (J) goes low (Vs
s) and turns off the data switch when the clock is low. The three-stage signal 5(J) is obtained by shifting the input of (11) by 1 bit relative to 5(J-1), and
) corresponding to the next stage clock-controlled inverter (12
The shift register can be constructed so that the signal M(J◆1) is shifted by 1.5 bits with respect to 5(J-1) of ), and the output thereof is Ds(J). At this time, Ds(J) goes high when the clock is low, and goes low when the clock is high. DsP(I) (1”1
(R), 2(G).

3(B), I-1~N) and 0s(J) are J-3・(1-
Compatible with 13+P. Image data [JR, [lG, [
1B, the outputs of the shift registers connected in series as shown in Fig. 4 are sampled by turning on data switches in multiple stages redundantly as shown in Fig. 3.
As shown in DS'(1) and DS'(2), there is no overlap in the period during which the data switch is turned on to capture the image data DP transferred to the data line.
sR(1), DsG(I), Ds8(1)(1-1,2
---) The period in which the data switch is turned on to capture image data IIR, DG, [1B] transferred to multiple data lines overlaps in the number of columns equal to the number of data lines. As seen in Ds8(1), the sampling of the first two columns, that is, Ds''(1), contains image data of pR, [lG from different data lines.

At the time of the high signal of Ds' (1), it becomes high and turns on the data switch and starts sampling the image data DB, and immediately before the image data moves from that column to the next, it becomes low and turns off the data switch. Sampling has ended.

FIG. 7 is a peripheral circuit diagram of the second embodiment of the image display device of the present invention, and FIGS. 8 and 9 are sample diagrams configuring the peripheral circuit.
A circuit diagram of the data switch or transfer switch used in the hold circuit, and FIG. 10 is a circuit diagram showing the output portion of the shift register of the peripheral circuit. In Fig. 7, one peripheral circuit is a shift register (13) and an output Ds' (1) of the shift register (P=R, G, B l
-1-N), and the image data [
It consists of a data switch that samples JP, and a sample number hold circuit (14) that has a transfer switch that is turned on by enable signals w and w' in order to transfer the sampled data to the column electrodes of the liquid crystal display in parallel. If 0w turns on the transfer inch group and w' turns off, then [JP is mouth s'(
The signal is stored in the data capacitor of CP(I) and the capacitor associated with the column electrode of the liquid crystal display through the data switch that is turned on by I) and the transfer switch that is turned on by the transfer signal, and becomes the signal Dr(1), which is transferred. If you want to turn off the switch group and turn it on.

The signal is stored in the data capacity of C'P(I) and the capacitance attached to the column electrode and becomes the signal D'P(1), so that the pixel group of the liquid crystal display receives signals from different column electrodes in adjacent rows. If configured, W and W' alternately turn on and off the transfer switch group for each row to obtain OF(1), D
'P (1) signal is set to the column electrode. data switch.

As shown in Figure 8, the transfer switch is an N-type or P-type field effect transistor (in the case of P-type, it is a high (
The gate signal is the inverted signal of the N-type gate signal that turns on at Voo).As shown in Figure 9, it is composed of complementary connected N-type and P-type field effect transistors, and in the format shown in Figure 8, the liquid crystal By integrating transistors of the same conductivity type as the transistors formed on each display substrate on the liquid crystal display substrate, and incorporating a sample and hold circuit on the same substrate, single P(I) and D'P( 1) The number of connection terminals between the output terminals transmitting the signal and the column electrodes (8N), the number of connection terminals between the output terminals of the shift register and the data switches (3N), the number of data lines for image data (3), and the total number of enable signal terminals (2) 3N+5). The shift register (13) sets the power supply potential to Voo, VccOVss.
) is constructed by adding the output part shown in FIG. 10 to the shift register shown in FIG. 4, and M(J) in FIG.
, 5(J), and Ds (J) as Q(J).
The signal between OO and VCC is generated by the circuit shown in Figure 1.
It is converted into a signal between 'vss' and outputs a signal of 0s (J).

Similarly to FIG. 4, 0s(J) and Ds'(1) correspond in J-3-(1-1)+P. The Ds(J) signal is used together with the 0s(J) signal to control a switch formed by parallel connection of complementary transistors as shown in FIG. The peripheral circuit shown in FIG. 7 operates at the timing shown in FIGS. 2 and 3, and is configured such that the outputs of the shift registers are sequentially applied to the data switches while having overlapping periods in multiple columns.

FIG. 11 is a peripheral circuit diagram of the third embodiment of the image display device of the present invention, FIG. 12 is a timing chart showing its operation, and FIGS. 13 and 14 are diagrams of sample and hold circuits used in the peripheral circuit. It is a circuit diagram. The peripheral circuit in FIG. 11 includes a shift register (15) and the output Ds'(I) of the shift register (Ptrim R, G).

B, l-1-N), the data switch samples the image data to be transferred in series, and the enable signal W controls the data switch to transfer the sampled data in parallel to the column electrodes of the liquid crystal display. It consists of a sample-and-hold circuit (1B) using a clock-controlled inverter as a transfer switch.

In FIG. 12, the data Os of the shift register has a pulse width of three cycles of the clock CL, and each output of the shift register sequentially generates a signal 0sR (1 ), Ds(1).

The 0 image data output as O58(1) ~0sB(N) is sampled to ff1cP(1) through the data switch turned on by the shift register output Ds'(1), and the other is high (Voo) and clocked. When the controlled inverter is in the output state and 0%lI, which transmits the DP (1) signal obtained by inverting the sampled data to the column electrode of the liquid crystal display, is low (Vss), the output of the clock controlled inverter becomes high impedance. DP
The signal (1) is held in the capacitance associated with the column electrode. The enable signal - puts the clock-controlled inverter into the output state while all the shift register outputs are low (Vss) and the data switch is off, and the signal that selects the pixel group of the liquid crystal display for each row is The signal G(
As shown in Fig. K), the data of each column electrode is output in parallel to the pixel group of the selected row.
As seen in DsR (1), Ds' (1), and DsB (1), the output of the shift register is duplicated in multiple columns, but the data switch is turned on to capture the image data transferred to the same data line. There may be overlap in the period of
Os in FIG. 12 and each output of the shift register can be made to have a pulse width of three cycles or more of the clock CL. 13th
In the figure, a clock-controlled inverter is used as the data switch of the sample-and-hold circuit (1B), and one image data DP is inverted by the clock-controlled inverter, which is brought into the output state by the output Ds' (I) of the shift register, and the capacitance CP is The signal of DP(1) stored in DP(1) and further inverted by a clock-controlled inverter which becomes output in response to an enable signal - is transmitted to the column electrodes of the liquid crystal display. In FIG. 14, image data [lP is stored in He' (I) through a data switch turned on by the output Ds' (1) of the shift register, and the enable signal -
The signal of DP(I), which is inverted by the clock-controlled inverter and stored in the capacitor ff1sP(I), is further inverted by the inverter and is in the output state, and is transmitted to the column electrode of the liquid crystal display. Even if the controlled inverter has a high impedance, the inverter always outputs a signal of 0P(1) due to the potential of 5P(1).

FIG. 15 is a peripheral circuit diagram of a fourth embodiment of the image display device of the present invention, FIG. 16 is a timing chart showing its operation, and FIG. 17 is a circuit of a buffer amplifier used in the sample/hold circuit of the peripheral circuit. It is a diagram. The peripheral circuit in FIG. 15 includes a shift register (17), a data switch that is turned on by the output DsP (1) of the shift register and samples image data DP that is serially transferred;
The data stored in the capacitor 5P(I) is passed through a buffer amplifier with a gain of approximately 1 that outputs a signal with approximately the same potential as the data sampled and stored in the capacitor CP(I), and a transfer switch that is turned on by an enable signal W. Furthermore, the output signal DP(1) is passed through a buffer amplifier with a gain of approximately l.
It consists of a sample and hold circuit (18) that drives the column electrodes of the liquid crystal display. In Figure 18,
The data Ds of the shift register has a pulse width of one cycle of the clock CL, and each output DsR of the shift register
(1), Ds (1), mouth 58 (1) ~ 0sB (N) is C
The signal has a pulse width of one cycle of L and is shifted by half a clock cycle. The shift register (17) is M in Figure 4.
The signals shown as (J) and 5(J) are respectively (2J
-1), 2J stage output, Os'(1)(P
Snow 1(R), 2(G), 3(B), 1(INN) is 3
・(1-1)◆This is the output of P stage. As shown in Figure 17, the buffer amplifier consists of a field effect transistor (19) that serves as a constant current source, an input quadrant sister (20), (
Transistor (21) with the same characteristics and size as (20), (
20), a reverse polarity transistor (22) serving as a load;
It consists of a voltage follower using a differential amplifier consisting of a transistor (23) which has the same characteristics and size as (22) and serves as a load for (21). The gate bias Va (19) is configured to be commonly applied to the buffer amplifier group (18). Similarly to Figure fJS12, the enable signal W turns on the transfer switch group during the period when all the outputs of the shift register turn off the data switches, and the signal that selects the pixel group of the liquid crystal display for each row is G(K ), the output of the buffer amplifier is supplied in parallel to the pixel group in the row selected from each column electrode of the liquid crystal display.

FIG. 18 is a peripheral circuit diagram of a fifth embodiment of the image display device of the present invention, and FIG. 19 is a signal timing chart.

The image data PP, which is serially transferred by the data switch turned on by the output Os' (1) of the shift register (24), is stored in the capacitor CP(I), and the transfer signal is turned on by the enable signal - when the data switch is turned off. The signal is transferred to the capacitor ff1sP(1) by a switch, and a signal of 0r(I) is transmitted to the column electrode by a buffer amplifier with a gain of 1. Sample/hold circuit (25)
has a data switch, a transfer switch, a buffer amplifier, capacitors CP (1), 5IP (1), and a switch that is turned on by a clear signal, clears the data stored in 5P (1), and makes it a constant potential. . The clear signal is output during the period when the output of the shift register turns off the data switch and the enable signal turns off the transfer switch.Subsequently, the enable signal turns on the transfer switch and stores data in 5P(1). CP(I) and 5P(I) are switches,
Assuming that the capacitance attached to the electrodes such as the input end of the buffer amplifier is included, the fJP data stored in CP(1) is 5P(1) as CP(1)/(CP(1)◆5P
It is stored at the potential of (I)). Sampled [JP
0F(1) is set larger than 5P(1) in order to make it close to the potential of 5P(1). The signal that selects the pixel group of the liquid crystal display for each row is output almost in synchronization with the clear signal, as shown in G (K), and the subsequent enable signal selects the selected row through the transfer switch and buffer amplifier. Data is supplied to the pixel group.

FIG. 20 is a peripheral circuit diagram of a sixth embodiment of the image display device of the present invention, and FIG. 21 is a signal timing chart.

Output DsP(1) of shift register (26) (P-
R, G, B,! -1 to N), samples the image data [lP into ftcP(I), and inputs it to the buffer amplifier through the first transfer switch, which is turned on by the enable signal Wp.

The second switch is turned on by an enable signal Wp′ synchronized with Wp.
The signal 0P(1) from the buffer amplifier passed through the transfer switch is stored in the capacitor 15P(1) and the capacitor attached to the column electrode of the liquid crystal display, and the row signal G(K) (
K-1-M) is transmitted to the pixel group of the row selected by K-1-M). In FIG. 21, the high period of the enable signal Wp' that turns on the second transfer switch is equivalent to the high period of the enable signal Wp' that turns on the first transfer switch.
is within the period of high. Wp' and Wp can also be the same signal. Multiple enable signals WR, WG IW8
is to sequentially turn on a plurality of adjacent first transfer switch groups side by side to guide data to a buffer amplifier,
wR, wG, the same number of enable signals wR' as We;
Since wG' and We' transmit signals from the buffer amplifier to the column electrodes by sequentially turning on a plurality of second transfer switch groups side by side, the second
The sample and hold circuit (27) in Figure 0 has the number of buffer amplifiers '/3. the same number of enable signals WR as the number of data lines of image data to be serially transferred;
WG IW [l or IIR', WG', We'
can be configured to be different from the number of data lines of image data. The lower circuit part shown by the dashed line in (27),
That is, enable signal 11' * 'G' + 'B'
A second group of transfer switches controlled by.

As mentioned in the second embodiment, by integrating on the substrate together with the transistors formed for each pixel of the liquid crystal display, the number of connections between the sample and hold circuit and the electrodes on the column side of the liquid crystal display can be reduced to 1/1. (number of enable signals) and a mounting surface that can increase the spacing between connected electrode terminals;
The semiconductor integrated circuit including the shift register and the sample-and-hold circuit shown above the one-dot chain line has the advantage of reducing the number of parts, which is advantageous in terms of cost. Capacity CP (1),
The ground potential of one electrode of SP (I) may be a constant potential, for example, VDD or VSS, and 5P (1) may be included in the capacitance associated with the column electrode of the liquid crystal display.

FIG. 22 is a peripheral circuit diagram of the seventh embodiment of the image display device of the present invention, FIG. 23 is a circuit diagram of a buffer amplifier used in the sample/hold circuit of the peripheral circuit, and FIG. 24 is a constant potential voltage applied to the buffer amplifier. Bias circuit diagram for inputting, No. 25
The figure is a signal timing chart. The shift register (28) turns on the data switch of the sample/hold circuit (29) with the output Os' (1), samples the image data DP into the capacitor CP (1), and inputs it to the buffer amplifier. The buffer amplifier becomes operational when the enable signal E is high (Voo), and outputs the output signal DP through the transfer switch that is turned on when the enable signal W is applied.
(I) is stored in the capacitor 5P(I) and the capacitor attached to the column electrode of the liquid crystal display, and is sent to the pixel group selected by the row signal G(K). The buffer amplifier is a transistor (31) that turns on when E is high, and a constant current source transistor (32).
, a transistor (30) with the same characteristics and the same size as the input quadrant sister (33), and a transistor (35) with the opposite polarity that becomes the load of (33), the same characteristics and the same size as (35) and the load of (34) The first differential amplifier stage consists of a transistor (36), a transistor (37) that is turned on when the inverted signal of E is low (Vss) by an inverter (30), a constant current source transistor (38), and an input quadrant sister ( 38), a transistor (40) serving as a pair of (38), a transistor (41) of opposite polarity serving as a load of (38), a transistor (42) serving as a load of (40) and a pair of (41), a second differential amplification stage in which the transistors corresponding to each transistor of the first differential amplification stage have opposite polarities; a transistor (43) to which the output of the first differential amplification stage is input; a second differential amplification stage; The output of the stage is inputted to (43) and the transistor (40) of opposite polarity.
It consists of an output stage consisting of. The input signal is (33)
, (39) are commonly transmitted to the gates of (43), (4
The signal of the connected output stage of 4) is fed back as the input of (34) and (40), forming a voltage follower. E
are high and off (45), (4B) and (47)
, (48) is turned on when E is low, and (3
5), (38).

(43) gate potential is high, (41), (42),
The gate potential of (44) is set to low to turn it off, and E is set to low to turn off (31) and (37), and the buffer amplifier is brought to a standstill state. The buffer amplifier shown in FIG. 23 is characterized by a higher output current than that shown in FIG. 17. (32), (38)
The gate biases VeN, Vep, E c7) are configured so that they are commonly applied to the buffer amplifier group of the inverted signal 4i (29), and VBN tVBP can be configured such that one potential input causes the other to be output. So, V.I.P.
A transistor (50) whose gate input is
Vss, which is connected in series to transistors (52), (50), and (52) whose drains are connected and outputs a voltage of VAN-VSS that is approximately equal to the voltage of Vo o - Ver;
Vo.

Transistor (4θ) with gate input, (51)
(51) and (52) are (49) and (5
0),! : It is a transistor with reverse polarity. As shown in FIG. 25, the high period of the enable signal W that turns on the transfer switch is within the high period of the enable signal E that turns on the buffer amplifier.
The current consumption can be reduced by the E signal.

It is also possible to set the signal of E to high and keep the buffer amplifier in constant operation.

FIG. 26 is a pixel arrangement diagram of a liquid crystal display of the eighth embodiment of the image display device of the present invention, FIG. 27 is a timing chart of signals input to the column electrodes of the pixel arrangement of FIG.
FIG. 8 is a circuit diagram configuring the shift register clock and data signals CL and O9 from the peripheral circuit. Second
In Figure 8, pixels with filters for each of the three primary colors RlG and B are formed so that pixels of filters of different colors are adjacent to each other, and in odd-numbered rows, R, G, and B are repeated in the row direction, and in even-numbered rows, pixels are arranged at half a pitch. The 0 column electrodes, which are shifted horizontally and repeat B, R, G t, are arranged so as to connect the pixels of the filter of the same color, and as shown in the figure, DP (1) (P-R,
The column electrodes transmitting the G, B) signals are placed in pixels shifted by 1.5 pitches in even-numbered rows. In Fig. 27, the data aS of the shift register is 2 of the clock (CL, CCLo).
Each output of the shift register has a pulse width equivalent to a period of the clock, and sequentially outputs a signal shifted by a clock period with a pulse width equivalent to two clock periods as DsR(1), DsG(1), Ds'(1).
~DsB(N), and the image data is sampled each time it is output, but in Figure 26, the pixels in the even rows are shifted by 1.5 pitches, so 1
．． Image data at a time point shifted by five clocks is sampled. In other words, for data Do of equal period regardless of odd or even rows, aS becomes high (Voo) or low (Vss) depending on the evenness of the rows, and when H is low, it becomes Do. Same signal, when H is high, than Do
The signal is shifted by 1.5 clocks, and the clock GL
When H is high, it becomes an inverted signal. In FIG. 28, the clock CL is output from an exclusive OR (53) with respect to the reference clock CLo so that H is in the same phase when it is low and out of phase when it is high. When it is high, it indicates that the clock CLo is shifted by 1.5 bits, that is, by the delay circuit (54) of 1.5 clocks of the clock CLo. - If the image data of a certain column is sampled and the time interval between sampling the image data of the next column is To, then if the pixels are shifted by X pitch depending on the row, the data flow S that enters the shift register, Both the clock OL and the clock OL should be signals that are shifted by XTo. When To is one clock cycle, the clock should be inverted when the pixel shift is 0.5 or 1.5 pitches, and when 0 is half a clock cycle, the clock should be inverted. , delay the clock by 174 clocks with 0.5 pitch.

It is sufficient to invert at 1 pitch and delay by 3/4 clock at 1.5 pitch, that is, delay by '/4 clock after inversion.

FIG. 29 is a pixel arrangement diagram of a liquid crystal display of a ninth embodiment of the image display device of the present invention, FIG. 30 is a timing chart of signals input to column electrodes in the pixel arrangement of FIG. 29, and FIG.
FIG. 1 is a circuit diagram configuring clock and data signals of a shift register in a peripheral circuit. In Figure 29, R, G
, H, the pixels having filters of the three primary colors are arranged so that the pixels of the filters of different colors are adjacent to each other as shown in FIG.
), DG (I), and DB (1) signals,
From the other side D' B(1), D' R(1), 0
'If you input the G(I) signal and look at one row of pixels in the row direction, you will see R, B, G, R, B.

DR(I) and D'8(I
).

[IG(1), D' R(I), 09(1), D'
A G(I) signal is input, and the side to which the signal is input is distinguished based on the parity of one column. Each signal 0P(I), D'
Q(I)(P-R,G,B.

Q-B, R, G) are located in pixels that are shifted by 1.5 pitches in even rows, and the pixels that receive the signals of DP (I) and [)'Q (1) are adjacent to each other, and the interval is 1 pitch. It is. 30th
In the figure, the clock OL and data Ds are signals of a shift register, DsR(1), and DsG(1) in a peripheral circuit that receives the DP(1) signal from one side of the liquid crystal display.

[]5B(1) to DsB(N) are the outputs of the shift register, including clock CL', data O9', D'5B
(1).

D' 5R (1), D' 5G (D ~ D's' (
N) are signals of a shift register in a peripheral circuit that receives the D'Q(1) signal from the other side of the liquid crystal display. The data Us and Ds' of the shift register are clock CL.

It has a pulse width of two periods of CL', and each output of the shift register sequentially outputs a signal shifted by a clock period with a pulse width of two periods of the clock. In Figure 29, the pixels that receive the same signal are shifted by 1.5 pitches in even rows, and D
'0(I) is a signal one pitch horizontal to DP(1),
Since G(I) is a signal two pitches to the side of DB(1), the TO mentioned earlier is a clock half cycle, and in FIG. 31, CL is in phase with respect to the reference clock CLo in odd rows where H is low. , in even numbered rows where H is high, the signal is delayed by 1/4 clock after inversion, and CL' is Os for data Do of equal period regardless of the parity of row 0 which is inverted with respect to CL. is the same signal when H is low, and CLo when H is high.
The signal is delayed by 3/4 of the clock. this is(
55) is a one-clock delay circuit for OL, and the hole is for CL.
This is because the signal is delayed by 38 clocks with respect to CLo, that is, the signal is shifted by 1 1/4 clocks from CLo. O5' shifts the clock and data of the shift register by placing a 0 pixel that is shifted by half a clock from ns by the half clock delay circuit (58) of CL.
The image data that is transferred and sampled over a uniform chronological passage of time is configured to represent data of pixels located at distances proportional to the passage of time in a uniform plane of one display. When H is high, DsR(1), Ds'(1), UsQ(
1) ~Ds8(N), D' 5B(1), D'
s”(1), D'5G(1) ~D'5G(N)
The configuration is such that the signal is output and data is captured in pixels shifted by 1.5 pitches in even-numbered rows.

FIG. 32 is a peripheral circuit diagram of the 10th embodiment of the image display device of the present invention, FIG. 33 is a signal timing chart, and FIG. 34 is a configuration of the shift register clock and image data selection signal of the peripheral circuit. Circuit diagram, Figure 35, Figure 3B
The figure is a circuit diagram configuring an image data selection circuit and signals of the peripheral circuit. (57) is a shift register that shifts the signal DS entering the data input terminal D1 to the clock CL (OL), and sequentially shifts the signal DS to the clock CL (OL), DsR (1), 0s (1).
, Os8(1) to port 5e(Y) are output. (
58) turns on the data switch by the output, and the image data D+lI, DIG, DI that passed through the selection switch
B is sampled, data capacity 0R (1), CG (1
), CB(1) to CB(Y) and DR(1) to the capacitance associated with the column electrodes of the liquid crystal display.

Stores signals of DG(1) and DB(1) to DB(Y).

(59) is a shift register with the same function as (57), which takes a signal equivalent to Ds' (Y) as data input, and follows DsB (Y) with <DsR (YΦ1), Ds' (YΦ1),
◆1).

Outputs signals DSB(Y+1) to DsB(2Y). (eo) is a sample/hold circuit similar to (58), DR (Y+1), DG (Y+1), DB
It outputs signals of (Y +l) to 08 (2Y).
(81) and (132) also have the same configuration as (59) and (H), and DR (2Y◆1) and DG (2Y-
1).

Signals DB(2Y+1) to 08 (3Y) are supplied to the column electrodes.

(57) and (58) constitute one semiconductor integrated circuit having a 3Y output signal terminal that outputs to the column electrode, and the peripheral circuits are (59), (80), (131), and ([12)]. The 3Y signal is output from three parts. 33rd
In the figure, the subscript Z indicates the order of the semiconductor integrated circuits, and Z-1 is (
57), (58), Z-2 is (59), (130)
, Z-3 is (fll).

(62). As shown in FIG. 34, shift registers (57), (59), and (81) take in consecutive clocks CL as clocks GLZ from the time when data DI becomes high (Vo -1)Y+1), 0sG((Z
-1)Y+1), 0sB((Z-1)Y◆1)~Ds
Reset signal R1 that becomes high after outputting the B (ZY) signal
closes the OL gate and lowers CL2 to low (Vss)
(85) is the gate of CL,
(fi3) and (84) are NORs that input DZ and R2 and form a flip-flop. When the output O7 of the flip-flop is low and the gate (85) is open, the gate (66) by Noah is opened, and when the selection input So is low, SDZ is high and S, Z t-low, (58) ,
(Go), (82) image data [JR, [lG,
Turn on the selection switch for passing [1B, turn off the selection switch for passing constant potential vO, and turn on the data line signal DzR, [17
G.

[ ] 2 [1 is DR, D', DBa: 6 *
Oz cover (Tet* Image data selection signals S and Z are low, 9vZ is high, and the signal Dz that has passed through the selection switch
R, DZG, and DZB are constant potentials vO. A clock signal is input to the semiconductor integrated circuit that is to sample the serially transferred image data, and the SDI is set high to input image data and put into operation, and the clocks of the semiconductor integrated circuits of other peripheral circuits are set to low and the data is set to Line signal, P (P
- R, G, B) are brought close to the static state to distribute the capacity of the data line that transfers one image data,
Consumption type, flow is reduced When ESO is high, SDI is low.

SvZ becomes pi, and 1) zP becomes yo. vO can take, for example, a potential that changes periodically depending on the method of driving the liquid crystal display. The reset signal R2 is a signal Ds' (I) which is output in duplicate in multiple columns of semiconductor integrated circuits in an operating state, and a signal Ds6 (ZY
), and when the operation is transitioning to the primary semiconductor integrated circuit, DsB (ZY) changes from high to low and is then output. It is constructed by differentiating the delayed signal of DsB(ZY), but if the pulse width of Os'(1) is α cycle of clock CL, it is reset to the initial state at the rising edge of DI, and the clock is changed to (3Y+α). ) It may be configured by a counter that outputs a differential signal after counting.

Also, image data can be distinguished and selected depending on the parity of the rows of the liquid crystal display, and in FIG. ' By l5Vz, (QR, [lG
.

DB) I(Fl, F21F3), (Vl, V21V
3). 0 as shown in Figure 36
2. If the output of the NOR (8B) inputting So is gated with the signal H indicating the parity of the rows to create the selection signals of Soz and SFz, (F' +F2+F3) becomes (Qa, Qg,
pli), So, 01 is low, H is rote and (87) (7) outputs S, Z are high and (Dz', DI2.DI3) are (rJR9[]G,
[]B), and when H is high, the output S of AND (88)
, 2 becomes high (Dz '-022+ Dz 3)
is (D'+D'+06), and the signal input to the data line is switched depending on the parity of the rows. O1 or SO is high! Sv'17) Signal technology (Dll, DI
2. DI3) becomes a potential signal of (v'tv2.v3). To switch the image data in every second row of the liquid crystal display using the H signal, one signal indicating the row is added, and as shown in FIG.
Image data can be switched in every third row in the same manner as in the configuration of FIGS. 35 and 38 for MS 34.

(Vl, V2, %13) Image data input card 1. ,
Image data for each row may be switched by combining So and H, and the same operation method as the peripheral circuit shown in FIG. 32, that is, the chip enable function for each semiconductor integrated circuit, is applied to the embodiments already described. can do.

[Effects of the Invention] The image display device of the present invention has novel features in the configuration and drive method of the peripheral circuit connected to the liquid crystal display, and has a margin in timing for sampling image data that is serially transferred. The data line that transfers the 0 image data is the #i failure line, and the image data that is transferred to multiple data lines at the same time is set by turning on the data switch and overlapping the period in multiple lines. Since the data switch is turned off and finalized just before the image data moves from the column to be transferred to the next image data, compared to the conventional example, the pulse width that is sampled when the data switch is turned on can be multiple times. It's doubled. If a transfer switch, which is turned on by an enable signal and transfers sampled data in parallel, is configured on the display substrate in the same way as the transistors of each pixel of a liquid crystal display, the semiconductor integrated circuit of the peripheral circuit and the display can be connected. It has the excellent effect of reducing the number of connection terminals and parts, and reducing current consumption by having a chip enable function for each semiconductor integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image display device of the present invention, and FIG. 2 is a timing chart showing its operation. 3 is a timing chart showing the operation of the first embodiment of the image display device of the present invention, FIG. 4 is a circuit diagram showing the configuration of a shift register in the peripheral circuit of the image display device, and FIGS. 5 and 6 is a circuit diagram of a clock-controlled inverter used in a shift register. FIG. 7 is a peripheral circuit diagram of a second embodiment of the image display device of the present invention, and FIGS. 8 and 9 are circuit diagrams of a data switch or transfer switch used in a sample hold circuit that constitutes the peripheral circuit. , FIG. 10 is a circuit diagram showing the output portion of the shift register of the peripheral circuit. FIG. 11 is a peripheral circuit diagram of the third embodiment of the image display device of the present invention, FIG. 12 is a timing chart showing its operation, and FIGS. 13 and 14 are diagrams of sample and hold circuits used in the peripheral circuit. It is a circuit diagram. FIG. 15 is a peripheral circuit diagram of the fourth embodiment of the image display device of the present invention, FIG. 18 is a timing chart showing its operation, and FIG. 17 is a circuit of a buffer amplifier used in the sample and hold circuit of the peripheral circuit. It is a diagram. FIG. 18 is a peripheral circuit diagram of a fifth embodiment of the image display device of the present invention, and FIG. 13 is a signal timing chart. FIG. 20 is a peripheral circuit diagram of the sixth embodiment of the image display device of the present invention, and 21st VgJ is a signal timing chart. FIG. 22 is a peripheral circuit diagram of the seventh embodiment of the image display device of the present invention, FIG. 23 is a circuit diagram of a buffer amplifier used in the sample/hold circuit of the peripheral circuit, and FIG. 24 is a constant potential voltage applied to the buffer amplifier. Bias circuit diagram for inputting, No. 25
The figure is a signal timing chart. FIG. 28 is a pixel arrangement diagram of a liquid crystal display of the eighth embodiment of the image display device of the present invention, FIG. 27 is a timing chart of signals input to column electrodes in the pixel arrangement of FIG.
FIG. 8 is a circuit diagram configuring the clock and data signals of the shift register of the peripheral circuit. FIG. 29 is a pixel arrangement diagram of a liquid crystal display of a ninth embodiment of the image display device of the present invention, FIG. 30 is a timing chart of signals input to column electrodes in the pixel arrangement of FIG. 28, and FIG. 3
FIG. 1 is a circuit diagram configuring clock and data signals of a shift register in a peripheral circuit. FIG. 32 is a peripheral circuit diagram of a tenth embodiment of the image display device of the present invention, FIG. 33 is a signal timing chart, and FIG.
FIG. 4 is a circuit diagram configuring the shift register clock and image data selection signal of the peripheral circuit, and FIGS. 35 and 3θ are circuit diagrams configuring the image data selection circuit and signal of the peripheral circuit. FIG. 37 is a block diagram of a conventional image display device, and FIG. 38 is a timing chart of each signal. (1): Shift register (2): Data switch (3): Shift register (4): Liquid crystal display

Claims (3)

[Claims] (1) In an image display device that performs display using a liquid crystal sandwiched between a substrate on which a plurality of column electrodes are formed and a counter substrate, there is a shift register and image data that is turned on by the output of the shift register and transferred in series. , the output of the shift register is sequentially applied to the data switch while having an overlapping period in multiple columns, and data is supplied from the peripheral circuit to the column electrodes in parallel. Image display device. (2) The peripheral circuit includes a shift register, a data switch that is turned on by the output of the shift register and samples image data to be transferred in series, and a sample/hold circuit that has a transfer switch that transfers the sampled data in parallel. An image display device according to claim 1. (3) The image display device according to claim 2, wherein the sample and hold circuit has a buffer amplifier with a gain of approximately 1.