JPS63188905A - Composite chip ceramic electronic component - Google Patents
Composite chip ceramic electronic componentInfo
- Publication number
- JPS63188905A JPS63188905A JP2069587A JP2069587A JPS63188905A JP S63188905 A JPS63188905 A JP S63188905A JP 2069587 A JP2069587 A JP 2069587A JP 2069587 A JP2069587 A JP 2069587A JP S63188905 A JPS63188905 A JP S63188905A
- Authority
- JP
- Japan
- Prior art keywords
- varistor
- laminate
- ceramic sheet
- capacitor
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims description 36
- 239000002131 composite material Substances 0.000 title claims description 18
- 239000003990 capacitor Substances 0.000 claims description 21
- 239000000203 mixture Substances 0.000 claims description 11
- 239000002243 precursor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002003 electrode paste Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- ZKATWMILCYLAPD-UHFFFAOYSA-N niobium pentoxide Chemical compound O=[Nb](=O)O[Nb](=O)=O ZKATWMILCYLAPD-UHFFFAOYSA-N 0.000 description 2
- KKCBUQHMOMHUOY-UHFFFAOYSA-N Na2O Inorganic materials [O-2].[Na+].[Na+] KKCBUQHMOMHUOY-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Thermistors And Varistors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［発明の目的１
（産業上の利用分野）
本発明は、バリスタ特性と］ンデンサ特性の複合機能を
有する複合チップ型セラミック電子部品に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention 1 (Field of Industrial Application)] The present invention relates to a composite chip type ceramic electronic component having a composite function of varistor characteristics and capacitor characteristics.
（従来の技術）
従来、バリスタ特性とコンデンサ特性の複合機能を有す
る容量性バリスタとしての電子部品としては、特開昭５
８−１６５０４号公報、または特開昭５８−９１６０２
号公報によって開示されるものがある。 これら公報に
開示された技術は、Ｓｒ丁：０３からなる６ｔｌａＳを
第１成分としたものにＮｂ２Ｏ５などの半専体化に寄与
する第２成分とサージに対する劣化防止するＮａ２Ｏか
らなる第３成分を添加混合し、還元雰囲気で焼結するこ
とによってＮａを粒界に拡散することによって得られる
ものである。(Prior art) Conventionally, as an electronic component as a capacitive varistor having a combined function of varistor characteristics and capacitor characteristics,
Publication No. 8-16504 or JP-A-58-91602
There is something disclosed by the publication No. The techniques disclosed in these publications include a first component of 6tlaS made of Sr-03, a second component such as Nb2O5 that contributes to semi-exclusive use, and a third component of Na2O that prevents deterioration against surges. It is obtained by adding and mixing Na and sintering it in a reducing atmosphere to diffuse Na into the grain boundaries.
しかして、上記構成になるバリスタ特性とコンデンサ特
性の複合機能を有する電子部品は、バリスタ特性および
コンデンサ特性ども焼結体の粒界に存（Ｅｉｉる構造と
なっている。寸なわら、焼結体の微細構造を模式的にす
ると粒界がシリーズに接合したものとなっている。Therefore, an electronic component having a composite function of varistor characteristics and capacitor characteristics with the above structure has a structure in which the varistor characteristics and capacitor characteristics exist in the grain boundaries of the sintered body. If we look at the microstructure schematically, we can see that grain boundaries are joined in a series.
そのためバリスタ電圧を高くするためには粒界のシリー
ズ接合数を多くする必要があるが、しかし、反面粒界の
コンデンサ特性、すなわち静電容量成分しシリーズ接合
となっているため、電圧を高くづると静電容量ｔｉｔ減
少する関係にある。Therefore, in order to increase the varistor voltage, it is necessary to increase the number of series junctions at the grain boundary, but on the other hand, the capacitor characteristics of the grain boundary, that is, the capacitance component and the series junction, make it possible to increase the voltage. There is a relationship in which the capacitance tit decreases.
したがって、」−記構酸になる容量性バリスタ（よ、バ
リスタ電圧と静電容量の任意な組合せはできず、必要と
１６高周波ノイズの吸収とり゛−ジ抑１ｂｌｌ ｉ能を
同時に実現できるものどはならず、結局はノイズ吸収用
にアクロスコンをサージ抑制用にバリスタをイれぞれ別
個に接続しているのが現状である。Therefore, it is not possible to use a capacitive varistor (as shown in the figure below) to create an arbitrary combination of varistor voltage and capacitance. The current situation is that the across condenser for noise absorption and the varistor for surge suppression are connected separately.
（発明が解決しようとする問題点）
以上のように上記構成になる容量性バリスタは、バリス
タ電Ｉｔと静電容量は反比例の関係にあり、実用上用途
も制限される状況にあった。(Problems to be Solved by the Invention) As described above, in the capacitive varistor having the above structure, the varistor voltage It and the capacitance are in an inversely proportional relationship, and the practical use of the capacitive varistor is limited.
本発明は、上記の点に鑑みてなされたしので、バリスタ
電圧と静電容量の任Ｑな組合せを可能としたバリスタ特
性とコンデンサ特性の複合機能を有する複合チップ型セ
ラミック電子部品を提供することを目的とするｂのであ
る。The present invention has been made in view of the above points, and an object of the present invention is to provide a composite chip-type ceramic electronic component having a composite function of varistor characteristics and capacitor characteristics, which enables arbitrary combinations of varistor voltage and capacitance. The purpose is b.
「発明の構成１
（問題点を解決するための手段）
本発明の複合チップ型ｐラミック電子部品は、複数の積
層した誘電体セラミックシー１〜間に内部電極を交互に
反対方向外周辺まで延ばし形成したコンデンサ積層休と
、複数の積層したそれ自体が非直線性を有する非直線抵
抗体はラミックシート間に内部電極を交互に反対方向外
周辺まで延ばし形成したバリスタ積層体との間に前記誘
電体セラミックシートと非直線抵抗体しラミックシート
を構成する両者の組成を主成分として混合した混合組成
物からなる前記両シー１〜より厚い混合セラミックシー
］・を介在し、前記コンデンサ積層体の内８１５電極と
バリスタ積層体の内部電極露出部を同一方向にして熱圧
谷一体化した焼成複合素体の両端部に、前記コンデンサ
ｆ？ｉ Ｆ、Ｙ体の内部電極とバリスタ！？１層体の内
部電極露出部の同一方向毎を連結した外部電極を形成し
てなることを特徴とするものである。``Structure 1 of the Invention (Means for Solving the Problems) The composite chip type p-ramic electronic component of the present invention has internal electrodes alternately extending in opposite directions to the outer periphery between a plurality of laminated dielectric ceramic sheets 1. The dielectric layer formed between the formed capacitor laminated layer and the varistor layered body formed by extending internal electrodes alternately in opposite directions to the outer periphery between lamic sheets and a plurality of laminated non-linear resistors each having non-linearity. The inside of the capacitor laminate is interposed between the above-mentioned thicker mixed ceramic sheets 1 to 1, which are made of a mixed composition mainly consisting of the compositions of both the non-linear resistor and the non-linear resistor lamic sheet. The internal electrodes of the capacitor f? The device is characterized in that external electrodes are formed by connecting the internal electrode exposed portions in the same direction.
（作用）
以上の構成になる複合チップ型しラミック電子部品にＪ
：れば、コンデンサ特性としての静電台Ｖおよびバリス
タ特性としてのバリスタ電圧は、ぞれぞれ単独で設定で
きるため必要に応じた静電台ｆｉｔ Ｊ３Ｊ、びバリス
タ電圧の組合せを適宜設定づるのみで静電容量とバリス
タ電圧の任意の組合ＩｌＮ能が得られる。また両者の一
体化仲介物として両省の組成を主成分としてｎ２合した
混合組成物で構成した混合セラミックシートを用いてい
るため、両者の熱圧着一体化は良好である。(Function) Composite chip type with the above configuration and J
:The electrostatic stand V as the capacitor characteristic and the varistor voltage as the varistor characteristic can be set independently, so you can set the electrostatic stand V as needed and the combination of the varistor voltage as appropriate. Any combination of capacitance and varistor voltage IIN capability can be obtained. Furthermore, since a mixed ceramic sheet made of a mixed composition in which n2 is combined with the compositions of both materials as main components is used as an intermediary for integrating the two, the thermocompression bonding of the two is good.
（実施例）
以下、本発明の実施例について説明する。ターなわら、
第２図に示すように公知の手段で表面に一辺を外周辺ま
で延ばし電極ベース１へを印刷−乾燥し内部電極１を形
成した誘電体上ラミックシー１・２と、第３図に示ずよ
うに前記同様表面に一辺を外周辺まで延ばし電極ペース
トを印１６１１−乾燥し内部２を極３を形成した焼結体
自体が非直線性を示づ゛非直線抵抗体セラミックシー１
〜４と、第４図に示すように前記誘電体セラミックシー
ト２を構成する組成と前記非直線抵抗体セラミックシー
ト４を構成する混合した混合物をドクターブレード法で
形成した混合セラミックシー］−５を準備する′す゛な
お、この混合セラミックシート５の厚さは、前記誘電体
上ラミックシー１〜２および非直線抵抗体セラミックシ
ート４厚さより厚く形成する。(Example) Examples of the present invention will be described below. Tarnawara,
As shown in FIG. 2, one side of the surface is extended to the outer periphery by printing and drying on the electrode base 1 to form the internal electrode 1 on the dielectric layer 1 and 2, and as shown in FIG. In the same way as above, extend one side to the outer periphery and mark the electrode paste on the surface 1611 - Dry and form the pole 3 inside 2. The sintered body itself exhibits nonlinearity.Nonlinear resistor ceramic sheet 1
~4, and a mixed ceramic sheet]-5, which is obtained by forming a mixture of the composition constituting the dielectric ceramic sheet 2 and the composition constituting the nonlinear resistor ceramic sheet 4 by a doctor blade method, as shown in FIG. The thickness of the mixed ceramic sheet 5 is made thicker than the thickness of the lamic sheets 1 and 2 on the dielectric material and the nonlinear resistor ceramic sheet 4.
つぎに、第１図に示すように内８１！電極１が交互に相
対向端面に導出されるよう前記誘電体セラミックシート
２を複数積層したコンデンサ積層に６と、内部電極３が
交互に相対向端面に導出されるよう非直線抵抗体セラミ
ックシート４を複数積層したバリスタ積層体７間に、前
記混合セラミックシート５を少なくとも１枚介在し前記
内部電極１と内部電極３導出部を同一方向にして加熱圧
着一体化し、しかるのち焼成し焼成複合索体８を得る。Next, as shown in Figure 1, 81! A laminated capacitor 6 is formed by laminating a plurality of the dielectric ceramic sheets 2 so that the electrodes 1 are alternately led out to opposite end faces, and a non-linear resistor ceramic sheet 4 is installed so that the internal electrodes 3 are alternately led out to opposite end faces. At least one of the mixed ceramic sheets 5 is interposed between the varistor laminates 7 in which a plurality of varistor layers are laminated, and the internal electrodes 1 and the internal electrodes 3 are integrated by heating and pressing so that the lead-out portions of the internal electrodes 1 and 3 are in the same direction, and then fired to form a fired composite cable. Get 8.
つぎに、前記内部電極１および内部電極３導出両端面に
内部電極１および内部電極３を連結した外部型！（ｉ９
．１０を形成してなるものである。Next, an external type in which the internal electrode 1 and the internal electrode 3 are connected to both end surfaces from which the internal electrode 1 and the internal electrode 3 are led out! (i9
．． 10.
以上のように構成してなる複合チップ型セラミック電子
部品によれば、各種必要電子機器に組込み使用した場合
に外部電極９，１０から得られる特性は、外部電極９．
１０がコンデンサ積層体６とバリスタ積層体７それぞれ
の内部電極１および内部電極３と連結した構造となって
いるため、コンデンサ積層体６のもつ静電容量特性とバ
リスタ積層体７のもつバリスタ電圧特性を兼ね備えたも
のとなる。したがって、それぞれの必要とする特性値設
定を任意に設定し得ることが可能となり、必要に応じた
最適な静電容量とバリスタ電圧を容易に選ぶことができ
る。According to the composite chip-type ceramic electronic component configured as described above, the characteristics obtained from the external electrodes 9 and 10 when incorporated into various necessary electronic devices are as follows.
10 is connected to the internal electrodes 1 and 3 of the capacitor laminate 6 and the varistor laminate 7, respectively, so that the capacitance characteristics of the capacitor laminate 6 and the varistor voltage characteristics of the varistor laminate 7 are It will be a combination of the following. Therefore, it is possible to arbitrarily set the characteristic value settings required for each, and it is possible to easily select the optimum capacitance and varistor voltage according to the needs.
また、コンデンサ積層体８とバリスタ積層体９の結合一
体化のための仲介物としてそれぞれを構成する組成を主
成分として混合した混合物からなる混合セラミックシー
ト５を用いているため、コンデンサ積層体６とバリスタ
積層体７の結合一体化が容易であり、結合度合良好な焼
成複合素体８を得ることができる。In addition, since the mixed ceramic sheet 5 made of a mixture of the compositions of the capacitor laminate 8 and the varistor laminate 9 as main components is used as an intermediary for the integration of the capacitor laminate 8 and the varistor laminate 9, the capacitor laminate 6 and the varistor laminate 9 The varistor laminate 7 can be easily bonded and integrated, and a fired composite body 8 with a good degree of bonding can be obtained.
なお、上記実施例では内部電極１および内部電極３形成
手段として、誘電体セラミックシート２および非直線抵
抗体セラミックシート４にあらかじめ電極ペーストを印
刷したものを例示して説明したが、コンデンサ特性を有
する誘電体セラミックシートおよびバリスタ特性を有す
る非直線抵抗体セラミックシート上に焼成によって焼失
するか、溶剤によって溶失する材料からなるスリット前
駆ペーストを印刷してスリット前駆膜を形成し前記同様
それぞれを複数Ｍ４層し、それぞれの積層体間に混合セ
ラミックシーＩ・を介在して熱圧着一体化した後、前記
スリット前駆膜を除去して積層化されたスリットを形成
し、しかるのち焼成し焼成複合素体を得る。In the above embodiments, as the means for forming the internal electrodes 1 and 3, the dielectric ceramic sheet 2 and the non-linear resistor ceramic sheet 4 are printed with electrode paste in advance. A slit precursor film is formed by printing a slit precursor paste made of a material that is burnt out by firing or melted away by a solvent on a dielectric ceramic sheet and a nonlinear resistor ceramic sheet having varistor characteristics, and a plurality of M4 slits are formed in the same manner as above. After the laminates are layered and integrated by thermocompression with a mixed ceramic sheet I interposed between each laminate, the slit precursor film is removed to form a laminated slit, and then fired to form a fired composite body. get.
つぎに、前記スリット導出端面に多孔質外部電極を形成
した後、この多孔質外部電極を通し前記スリットに溶融
金属を圧入し内部電極としたちのであっても同効である
。Next, after forming a porous external electrode on the lead-out end face of the slit, the molten metal may be press-fitted into the slit through the porous external electrode to serve as the internal electrode, and the same effect can be obtained.
［発明の効果］
本発明によれば、コンデンサ特性とバリスタ特性の任意
な組合せ機能を兼ね備えた実用的価値の高い複合チップ
型セラミック電子部品を得ることができる。[Effects of the Invention] According to the present invention, it is possible to obtain a composite chip-type ceramic electronic component of high practical value, which has the functions of arbitrary combinations of capacitor characteristics and varistor characteristics.
第１図〜第４図は本発明の一実施例に係り、第１図は複
合チップ型セラミック電子部品を示す正断面図、第２図
は第１図を構成する誘電体セラミックシー］へを示す平
面図、第３図は第１図を構成する非直線抵抗体セラミッ
クシートを示す平面図、第４図は第１図を構成する混合
セラミックシートを示Ｊ平面図である。
１・・・・・・内部電極
２・・・・・・誘電体セラミックシート３・・・・・・
内部電極
４・・・・・・非直線抵抗体セラミックシート５・・・
・・・混合セラミックシート
６・・・・・・コンデンサ積層体
７・・・・・・バリスタ積層体
８・・・・・・焼成複合素体
９・・・・・・外部電極
１０・・・・・・外部電極
特 許 出 願 人
マルコン電子株式会社1 to 4 relate to an embodiment of the present invention, in which FIG. 1 is a front sectional view showing a composite chip type ceramic electronic component, and FIG. 2 is a dielectric ceramic sheet configuring FIG. 1. 3 is a plan view showing the non-linear resistor ceramic sheet forming the structure shown in FIG. 1, and FIG. 4 is a plan view showing the mixed ceramic sheet forming the structure shown in FIG. 1. 1... Internal electrode 2... Dielectric ceramic sheet 3...
Internal electrode 4...Non-linear resistor ceramic sheet 5...
... Mixed ceramic sheet 6 ... Capacitor laminate 7 ... Varistor laminate 8 ... Fired composite element 9 ... External electrode 10 ... ...External electrode patent application Hito Marukon Electronics Co., Ltd.
Claims (1)
を交互に反対方向外周辺まで延ばし形成したコンデンサ
積層体と、複数の積層したそれ自体が非直線性を有する
非直線抵抗体セラミックシート問に内部電極を交互に反
対方向外周辺まで延ばして形成したバリスタ積層体との
間に前記誘電体セラミックシートと非直線抵抗体セラミ
ックシートを構成する両者の組成を主成分として混合し
た混合物からなる混合セラミックシートを介在し、前記
コンデンサ積層体の内部電極およびバリスタ積層体の内
部電極露出部を同一方向にして熱圧着一体化した焼成複
合体からなり、この複合体の両端面に形成した前記コン
デンサ積層体の内部電極とバリスタ積層体の内部電極露
出部の同一方向毎を連結した外部電極を具備したことを
特徴とする複合チップ型セラミック電子部品。A capacitor laminate is formed in which internal electrodes are alternately extended between a plurality of laminated dielectric ceramic sheets to the outer periphery in opposite directions, and an internal electrode is formed between a plurality of laminated nonlinear resistive ceramic sheets that themselves have nonlinearity. A mixed ceramic sheet consisting of a mixture of the compositions of both the dielectric ceramic sheet and the non-linear resistor ceramic sheet as main components is interposed between the varistor laminate formed by extending the varistor layers alternately to the outer periphery in opposite directions. The interior of the capacitor laminate is formed on both end faces of the composite, and is made of a fired composite body in which the internal electrodes of the capacitor laminate and the exposed internal electrodes of the varistor laminate are integrated by thermocompression in the same direction. A composite chip type ceramic electronic component characterized by comprising an external electrode that connects the electrode and the internal electrode exposed portion of the varistor laminate in the same direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2069587A JPS63188905A (en) | 1987-01-31 | 1987-01-31 | Composite chip ceramic electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2069587A JPS63188905A (en) | 1987-01-31 | 1987-01-31 | Composite chip ceramic electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63188905A true JPS63188905A (en) | 1988-08-04 |
Family
ID=12034288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2069587A Pending JPS63188905A (en) | 1987-01-31 | 1987-01-31 | Composite chip ceramic electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63188905A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01283915A (en) * | 1988-03-28 | 1989-11-15 | American Teleph & Telegr Co <Att> | Multilayer device and its manufacture |
| JPH02137212A (en) * | 1988-11-17 | 1990-05-25 | Murata Mfg Co Ltd | Composite electronic component |
| JP2017507473A (en) * | 2014-11-20 | 2017-03-16 | アモテック シーオー，エルティーディー | ELECTRIC SHOCK PROTECTION ELEMENT AND PORTABLE ELECTRONIC DEVICE HAVING THE SAME |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57187929A (en) * | 1981-05-15 | 1982-11-18 | Tdk Electronics Co Ltd | Method of producing solid state composite part |
| JPS5848907A (en) * | 1981-09-18 | 1983-03-23 | 松下電器産業株式会社 | Ceramic laminate |
| JPS6332911A (en) * | 1986-07-26 | 1988-02-12 | ティーディーケイ株式会社 | Noise absorber |
-
1987
- 1987-01-31 JP JP2069587A patent/JPS63188905A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57187929A (en) * | 1981-05-15 | 1982-11-18 | Tdk Electronics Co Ltd | Method of producing solid state composite part |
| JPS5848907A (en) * | 1981-09-18 | 1983-03-23 | 松下電器産業株式会社 | Ceramic laminate |
| JPS6332911A (en) * | 1986-07-26 | 1988-02-12 | ティーディーケイ株式会社 | Noise absorber |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01283915A (en) * | 1988-03-28 | 1989-11-15 | American Teleph & Telegr Co <Att> | Multilayer device and its manufacture |
| JPH02137212A (en) * | 1988-11-17 | 1990-05-25 | Murata Mfg Co Ltd | Composite electronic component |
| JP2017507473A (en) * | 2014-11-20 | 2017-03-16 | アモテック シーオー，エルティーディー | ELECTRIC SHOCK PROTECTION ELEMENT AND PORTABLE ELECTRONIC DEVICE HAVING THE SAME |
| US10222838B2 (en) | 2014-11-20 | 2019-03-05 | Amotech Co., Ltd. | Electric shock device and portable electronic device including the same |
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