JPS63187612A - Method of forming laminated layers of laminated unit - Google Patents
Method of forming laminated layers of laminated unitInfo
- Publication number
- JPS63187612A JPS63187612A JP62019533A JP1953387A JPS63187612A JP S63187612 A JPS63187612 A JP S63187612A JP 62019533 A JP62019533 A JP 62019533A JP 1953387 A JP1953387 A JP 1953387A JP S63187612 A JPS63187612 A JP S63187612A
- Authority
- JP
- Japan
- Prior art keywords
- laminated
- dielectric
- metal foil
- ceramic
- paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title description 23
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 239000011888 foil Substances 0.000 claims description 18
- 239000003989 dielectric material Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- 239000003985 ceramic capacitor Substances 0.000 description 8
- 238000007639 printing Methods 0.000 description 7
- 239000011230 binding agent Substances 0.000 description 6
- 239000000843 powder Substances 0.000 description 5
- 229910052742 iron Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- -1 iron and nirakera Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 240000008168 Ficus benjamina Species 0.000 description 1
- 240000005499 Sasa Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、エレクトロニクス分野で広く使用される電子
部品、例えば、積層セラミックコンデンサ、積層型圧電
素子等のセラミック誘電体と内部電極とを層状に積層し
た積層体の積層成形法に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is an electronic component widely used in the electronics field, such as a multilayer ceramic capacitor, a multilayer piezoelectric element, etc., in which ceramic dielectrics and internal electrodes are layered. The present invention relates to a method for laminating a laminated body.
従来、」二足積層体の一例である積層セラミックコンデ
ンサの製造方法として数多くの発明が提案されているが
、それらを分類すると、セラミック誘電体の成形法とし
ては、(1)グリーンシート法、(2)印刷法があり、
内部電極の成形法としては、(3)ペースト法、(4)
注入法があり、それぞれは実用化されている。In the past, many inventions have been proposed as methods for manufacturing multilayer ceramic capacitors, which are an example of bipedal laminates, but they can be categorized into: (1) green sheet method; 2) There is a printing method;
The internal electrode molding methods include (3) paste method, (4)
There are injection methods, each of which has been put into practical use.
上記成形法の中で、(1)と(3)を組合わせた、いわ
ゆるグリーンシート法は、セラミック粉末と有機バイン
ダとを混合してスラリを作り、これをドクタブレード等
を用いたキャスティング法によって成形したグリーンシ
ート上に金属粉末と有機溶剤、バインダとを混合したペ
ーストを印刷し、積層圧着するようにしたものである。Among the above molding methods, the so-called green sheet method, which is a combination of (1) and (3), mixes ceramic powder and an organic binder to create a slurry, which is then cast using a doctor blade or the like. A paste made of a mixture of metal powder, an organic solvent, and a binder is printed on a formed green sheet, and the sheets are laminated and pressed together.
またいわゆる印刷法はセラミック粉末とa機溶媒、バイ
ンダを混合した誘電体ペーストと金属粉を含宵した内部
電極ペーストを交互に印す11するようにしたものであ
る。In the so-called printing method, a dielectric paste containing ceramic powder, a solvent, and a binder and an internal electrode paste containing metal powder are alternately printed.
従来の製造方法による積層セラミックコンデンサは、エ
レクトロニクス分野の飛W的発展の原動力の1つであり
極めて有用であった。Multilayer ceramic capacitors manufactured using conventional manufacturing methods have been one of the driving forces behind the rapid development of the electronics field and have been extremely useful.
しかしそれらには一長一短があり、必ずしも満足のいく
製造方法ではない。その中で解決すべき重要な問題点に
、安価で、かつ導電性の高い内部電極成形法がある。こ
の内部電極の問題を詳細に説明すると、(1)導電性、
融点、反応性の点で白金、パラジウムあるいはこれらの
含有率の高い高価な材料を使用する、(2)印刷厚さに
起因する電極切れ、静電客足のバラツキ、デラミネーシ
ョン、クラックが生じる、(3)鉄、ニラケラ等安価な
金属を使用する場合、金属粉の酸化防止のための還元性
、不活性、中性ガス等高価なガスを使用しなければなら
ない等である。However, these methods have advantages and disadvantages, and are not necessarily satisfactory manufacturing methods. Among these, an important problem to be solved is a method of forming internal electrodes that is inexpensive and highly conductive. To explain the problems of this internal electrode in detail, (1) conductivity,
(2) Using platinum, palladium, or expensive materials with a high content of these in terms of melting point and reactivity; (2) electrode breakage, variations in electrostatic customer traffic, delamination, and cracks due to printing thickness; ( 3) When using cheap metals such as iron and nirakera, it is necessary to use expensive gases such as reducing, inert, and neutral gases to prevent oxidation of the metal powder.
〔問題点を解決するための手段及び作用〕本発明は上記
のことにかんがみなされたもので、鉄、ニッケル、調停
安価な金属箔を内部電極材料に使用でき、しかも均一な
厚さで、かつ導電性に優れた内部電極を得ることができ
、性能が優れていると共に、全体としてコストダウンを
図ることができるようにした誘電体と内部電極からなる
積層体の積層成形法を提供しようとするもので、誘電体
上にシート状の金属箔を接石してからこの金属箔の必要
箇所に誘電体をマスキングし、その後金属箔の不要部分
をエツチング処理し、さらにこれのエツチング処理した
部分を含む全面に誘電体を積層し、この各工程を順次必
要回数繰り返すようになっている。[Means and effects for solving the problems] The present invention was conceived in view of the above-mentioned problems, and it is possible to use iron, nickel, and inexpensive metal foil as the internal electrode material, and to have uniform thickness and An object of the present invention is to provide a method for laminated molding of a laminate consisting of a dielectric material and internal electrodes, which can obtain internal electrodes with excellent conductivity, have excellent performance, and reduce the overall cost. In this method, a sheet of metal foil is placed on a dielectric material, the dielectric material is masked in the necessary parts of the metal foil, the unnecessary parts of the metal foil are etched, and the etched parts are etched. A dielectric material is laminated on the entire surface including the substrate, and each step is sequentially repeated as many times as necessary.
本発明の実施態様を図面に基づいて説明する。 Embodiments of the present invention will be described based on the drawings.
第1図は本発明方法にて積層成形された積層セラミック
コンデンサを示すもので、この構成は他の積層成形法に
て成形された従来のものと同じであり、図中1はセラミ
ック誘電体、2は内部電極、3は外部電極である。外部
電極3はセラミック誘電体の両外側に固着されており、
積層された複数個の内部電極2が交互に上記両性部電極
3,3に接続されている。そして両性部電極32.3に
図示してない導線がハンダ付けにて接続される。FIG. 1 shows a multilayer ceramic capacitor formed by the method of the present invention. This structure is the same as that of conventional capacitors formed by other multilayer forming methods. In the figure, 1 indicates a ceramic dielectric, 2 is an internal electrode, and 3 is an external electrode. The external electrodes 3 are fixed to both outer sides of the ceramic dielectric,
A plurality of stacked internal electrodes 2 are alternately connected to the bipolar electrodes 3, 3. A conducting wire (not shown) is then connected to the bisexual part electrode 32.3 by soldering.
以下に上記積層セラミックコンデンサの本発明法による
積層成形法を第2図から第5図を参照して説明する。The method of laminating the multilayer ceramic capacitor according to the present invention will be explained below with reference to FIGS. 2 to 5.
まず予め用意したグリーンシート4にニラケラ箔等のシ
ート状の金属箔5を接着剤にて貼り付け、その後この金
属箔5の表面に、第1図に示した製品の内部電極2と同
一寸法のセラミック誘電体6をセラミックペーストを用
いた印刷法によりマスキングする(第2図)。第5図は
上記セラミック誘電体6のマスキングした状態を示す平
面図である。First, a sheet metal foil 5 such as Nirakera foil is pasted on the green sheet 4 prepared in advance with adhesive, and then a sheet of metal foil 5 of the same size as the internal electrode 2 of the product shown in Fig. 1 is attached to the surface of the metal foil 5. The ceramic dielectric 6 is masked by a printing method using ceramic paste (FIG. 2). FIG. 5 is a plan view showing the ceramic dielectric 6 in a masked state.
乾燥後、酸、アルカリ溶液等のエツチング液に浸漬して
マスキングしてない部分の金属箔5を溶解処理し、乾燥
して所定の内部電極寸法を得る(第3図)。After drying, the unmasked portion of the metal foil 5 is immersed in an etching solution such as an acid or alkaline solution to dissolve it, and then dried to obtain a predetermined internal electrode size (FIG. 3).
ついでグリーンシート4を含む全表面に、上記印刷法に
よりセラミック誘電体7を、金属油5の上面に所定の厚
さとなり、かつ上面か平面となるように積層し、乾燥し
て誘電体内に内部電極を封入した第1層目を得る。Next, on the entire surface including the green sheet 4, a ceramic dielectric 7 is laminated by the above-described printing method on the top surface of the metal oil 5 to a predetermined thickness and so that the top surface is flat, and is dried to form an internal layer inside the dielectric. A first layer encapsulating the electrode is obtained.
上記第1層目の上面に再び上記工程を数回繰り返してセ
ラミック誘電体と内部電極となる金属箔を順次積層し、
最上層部にグリーンシート4を積層し、その後全体を加
圧、加熱により圧着成形する(第4図)。The above steps are repeated several times on the top surface of the first layer to sequentially laminate the ceramic dielectric and the metal foil that will become the internal electrodes.
A green sheet 4 is laminated on the top layer, and then the whole is pressurized and heated to form a bond (FIG. 4).
この工程において、積層される金属箔は奇数層と偶数層
毎と、一方に交互にずらしてあり、上記圧着成形後、第
4図に鎖線で示すように各金属箔が交互に露出する位置
で切断する。In this process, the metal foils to be laminated are alternately shifted to one side, each odd-numbered layer and every even-numbered layer, and after the above-mentioned pressure forming, the metal foils are alternately exposed at positions as shown by the chain lines in Figure 4. disconnect.
その後、脱バインダをしてから大気中で焼結を行ない、
冷却後従来の方法で外部電極を焼付けして第1図に示す
チップ型の積層セラミックコンデンサを得る。After that, the binder is removed and sintering is performed in the atmosphere.
After cooling, the external electrodes are baked by a conventional method to obtain the chip-type multilayer ceramic capacitor shown in FIG.
本発明方法によれば、内部電極2に金属箔を使用してい
るため、脱バインダ、焼結工程における酸素分圧の高い
大気中加熱でもこれの導電性の劣化を防止できる。また
内部電極2に安価な鉄、ニッケル等を使用でき、製造コ
ストの低減を図ることができる。According to the method of the present invention, since metal foil is used for the internal electrode 2, deterioration of the conductivity of the internal electrode 2 can be prevented even when heated in the atmosphere with high oxygen partial pressure during the binder removal and sintering steps. In addition, inexpensive iron, nickel, etc. can be used for the internal electrodes 2, and manufacturing costs can be reduced.
上記実施例の工程をさらに詳細に説明する。The steps of the above embodiment will be explained in more detail.
グリーンシート4は主成分のBaO,TiO2にCab
、SnO2、B12O3、PbOを添加したものか用い
られ、その大きさは50mmx50mmxQ、 2m
mであり、これに片面か1.+−磯接接着剤コートされ
た50mmX50mmX3μmのニッケル箔を貼り付け
、スクリーン印刷機にセントする。Green sheet 4 has main components BaO, TiO2 and Cab.
, SnO2, B12O3, and PbO are used, and its size is 50 mm x 50 mm x Q, 2 m.
m, and one side or 1. +- Paste a 50 mm x 50 mm x 3 μm nickel foil coated with iso adhesive and insert into a screen printing machine.
ここで300メソンユのステンレススクリーンにより、
8mmX9mmX約15μmのグリーンート4と同一の
セラミック組成のセラミックペーストを第5図に示すよ
うに印刷する。Here, with a 300 mesonyu stainless steel screen,
A ceramic paste measuring 8 mm x 9 mm x about 15 μm and having the same ceramic composition as Green Route 4 is printed as shown in FIG.
ついて乾燥後20%塩酸溶液に20m1n浸請して不要
なニッケル箔部を完全に溶解し、乾燥し、この上に30
0メンンユのステンレススリーンにより50mmx50
mmx約15μmのセラミックペーストを印1i1し、
乾燥して第1層目を得る。After drying, soak in 20ml of 20% hydrochloric acid solution to completely dissolve unnecessary nickel foil, dry, and add 30ml of nickel foil on top.
50mm x 50mm by 0mm stainless steel screen
Mark 1i1 with ceramic paste of mm x about 15 μm,
Dry to obtain the first layer.
第2層]二1以降の偶数層口は1回目のセラミックペー
ストの印刷位置より一方へ、例えば第5図において下方
へ1mmずらしてセラミックペーストを印刷し、奇数層
目は第1層目と同一位置に印刷し、合計10層積層した
後にを機接着剤により上記1層]1のグリーンシート4
と同一のグリーンシートを接台した。2nd layer] For the even-numbered layers after 21, print the ceramic paste one side from the first ceramic paste printing position, for example, by shifting 1 mm downward in Figure 5, and print the ceramic paste for the odd-numbered layers at the same level as the first layer. After printing on the position and laminating 10 layers in total, apply the above 1 layer with adhesive to the green sheet 4
The same green sheet was attached to the table.
このようにして得られた試料を金型にセットし、ホット
プレスにより約80°C130k g /cm2で30
m i n処理後放冷し、第4図に示すように切断した
。The sample thus obtained was set in a mold and heated at about 80°C and 130kg/cm2 for 30 minutes using a hot press.
After the min treatment, it was allowed to cool and was cut as shown in FIG.
その後550°Cで1時間脱バインダをし、大気中、1
150℃て45m1n焼結し、端面に外部電極を塗布、
焼付は後リード線をI\ンダ付けして、端子間の導電性
を測定した。After that, the binder was removed at 550°C for 1 hour, and the
Sintered 45m1n at 150℃, applied external electrode to the end surface,
After baking, the lead wires were soldered and the conductivity between the terminals was measured.
その結果、導1”i率は25個の試料のいずれも従来法
である金属粉末ペースト使用の場合の平均値(n−25
)の5〜10倍であり、導電性に優れていることかわか
った。As a result, the conductivity 1"i ratio was the average value (n-25
), indicating excellent conductivity.
本発明によれば、鉄、ニンケル、調停安価な金属箔を内
部電極として使用でき、しかも均一な厚さて、かつ導電
性に優れた内部電極を得ることかでき、性能か優れてい
ると共に、全体としてコストダウン図ることかできる。According to the present invention, iron, nickel, and inexpensive metal foils can be used as internal electrodes, and internal electrodes with uniform thickness and excellent conductivity can be obtained, and the performance is excellent and the overall It is possible to reduce costs as a result.
第1図は積層セラミックコンデンサの断面図、第2図、
第3図、第4図は成形工程を示す説明図、第5図は印j
σ11された誘導体の平面図である。
1はセラミック誘電体、2は内部電極、3は外部電極、
4はグリーンシート、5は金属箔。
出願人 株式会社 小 松 製 作 所代理人 弁
理士 米 原 圧 章
弁理士 浜 本 、1まi
第1図 第2図
第3図 第4図
笹 5 回Figure 1 is a cross-sectional view of a multilayer ceramic capacitor; Figure 2 is a cross-sectional view of a multilayer ceramic capacitor;
Figures 3 and 4 are explanatory diagrams showing the molding process, and Figure 5 is marked j.
FIG. 2 is a plan view of a derivative subjected to σ11. 1 is a ceramic dielectric, 2 is an internal electrode, 3 is an external electrode,
4 is a green sheet, 5 is a metal foil. Applicant: Komatsu Seisakusho Co., Ltd. Agent: Patent attorney: Akira Yonehara Patent attorney: Hamamoto, 1 Mai Figure 1 Figure 2 Figure 3 Figure 4 Sasa 5 times
Claims (1)
上にシート状の金属箔を接着してからこの金属箔の必要
箇所に誘電体をマスキングし、その後金属箔の不要部分
をエッチング処理し、さらにこれのエッチング処理した
部分を含む全面に誘電体を積層し、この各工程を順次必
要回数繰り返すことを特徴とする積層体の積層成形法。In a laminate consisting of a dielectric and internal electrodes, a sheet of metal foil is bonded onto the dielectric, the necessary parts of the metal foil are masked with the dielectric, and then unnecessary parts of the metal foil are etched, Furthermore, a dielectric material is laminated on the entire surface including the etched portion, and each step is sequentially repeated a necessary number of times.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62019533A JPS63187612A (en) | 1987-01-29 | 1987-01-29 | Method of forming laminated layers of laminated unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62019533A JPS63187612A (en) | 1987-01-29 | 1987-01-29 | Method of forming laminated layers of laminated unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63187612A true JPS63187612A (en) | 1988-08-03 |
Family
ID=12001967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62019533A Pending JPS63187612A (en) | 1987-01-29 | 1987-01-29 | Method of forming laminated layers of laminated unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63187612A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991003064A1 (en) * | 1989-08-24 | 1991-03-07 | Murata Manufacturing Co., Ltd. | Laminated capacitor and method of producing the same |
JP2004096071A (en) * | 2002-03-18 | 2004-03-25 | Seiko Epson Corp | Method of manufacturing piezoelectric actuator and liquid jetting head, and actuator mother member |
JP2012216874A (en) * | 2003-02-24 | 2012-11-08 | Epcos Ag | Electrical multilayered component and layer stack |
-
1987
- 1987-01-29 JP JP62019533A patent/JPS63187612A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991003064A1 (en) * | 1989-08-24 | 1991-03-07 | Murata Manufacturing Co., Ltd. | Laminated capacitor and method of producing the same |
GB2242070A (en) * | 1989-08-24 | 1991-09-18 | Murata Manufacturing Co | Laminated capacitor and method of producing the same |
US5144527A (en) * | 1989-08-24 | 1992-09-01 | Murata Manufacturing Co., Ltd. | Multilayer capacitor and method of fabricating the same |
GB2242070B (en) * | 1989-08-24 | 1994-01-19 | Murata Manufacturing Co | Multilayer capacitor and method of fabricating the same |
JP2004096071A (en) * | 2002-03-18 | 2004-03-25 | Seiko Epson Corp | Method of manufacturing piezoelectric actuator and liquid jetting head, and actuator mother member |
JP2012216874A (en) * | 2003-02-24 | 2012-11-08 | Epcos Ag | Electrical multilayered component and layer stack |
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