JPS6318723A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To quicken the phase synchronizing speed and to widen the synchronization pull-in range by allowing a phase difference arithmetic circuit to form a control signal changing a time base control interval in response to the quantity of phase difference between an input signal and an output clock pulse. CONSTITUTION:An input signal is A/D-converted by using a local clock, and the polarity change point of the input signal is obtained by the arithmetic operation depending on the input signal amplitude subjected to A/D conversion at present point of time and the input signal amplitude subjected to A/D conversion by the clock just before. Thus, the phase difference between the input signal and the output clock is calculated to control the phase of the output clock based on the information. The phase synchronizing circuit constituted in this way applies A/D conversion to the input signal, obtains the phase lead/lag of the phase between the input signal and the output clock and its phase difference through the arithmetic operation based on the adjacent input signal amplitude and controls the frequency of the phase control depending on the quantity of the phase difference.

Description

Detailed Description of the Invention B) Industrial Application Field The present invention is used in equipment that handles digital signals, such as magnetic or optical recording and reproducing equipment, and synchronizes the local clock of the equipment with an external signal. This relates to a phase-locked circuit for

10) Prior Art In general digital data transmission, if it is desired to include a clock component in the transmitted data, the reproduction detection system must extract the clock component from the transmitted data.

A phase-locked circuit (PLL circuit) has this function.
There is. This phase-locked circuit has conventionally been constructed using anamig circuit technology, but with the development of digital signal processing technology, a digital phase-locked circuit in which the phase-locked circuit is entirely digitalized has been proposed based on the following rationale.

■ The bandwidth and center frequency of the phase synchronization system can be easily varied.

■ Since a voltage controlled oscillator and low-pass filter are not used, loop dependence on temperature and power supply voltage fluctuations can be reduced.

Conventionally, a system shown in FIG. 4 has been reported as this all-digital phase synchronization circuit. (Journal of the Institute of Electronics and Communication Engineers 73/1
2 Vol 56-A No 12 Binary titanization all-digital phase synchronization system) In this method, the phase difference between the input signal and the output clock pulse is converted into a binary digitization system, and the output clock pulse is determined by digitally integrating the phase difference between the input signal and the output clock pulse. The circuit performs discrete frequency control, and as shown in the fourth factor, the circuit has an input signal source aη,
It is composed of an oscillation circuit (181), a time axis control circuit C (5), a phase comparison circuit (2b), and an output terminal e41.The phase comparison circuit 126+ includes a bivalent phase comparator ■ and a reversible counter. The comparator ■ is provided with an input (no. 8) and an output clock pulse, and if the output clock pulse rises earlier than the input signal, it is an advance signal a1, and if it rises later than the input signal, it is a delay signal a1. The signal b1 is output to the reversible counter CD.This reversible counter (21) adds 1 if the input signal ' is a leading signal a1, and subtracts 1 if it is a delayed signal.This counter is set to the initial value N. When the count value is counted up by 21LK, the determination circuit outputs a positive control signal a2, and when the count value is counted down to zero, the determination circuit outputs a negative control signal b.
2 is output to the time axis control circuit (251).

Then, this control circuit receives the positive control signal a2 and removes one pulse of the oscillation signal from the oscillation circuit (181).
In response to the negative control signal b2, the oscillation signal from the oscillation circuit U is set to 1.
Add pulse. In either case, after this addition or removal control is completed, the counter (2υ is reset) (M number (271
The initial value NK is reset again.

The control [il path] includes a 2M frequency divider circuit 01, and the output of this frequency divider circuit is used as an output clock pulse to output terminal (24
) and to the comparator Q1.

Through the above closed loop control, the output clock pulse is synchronized with the rising edge of the input signal.

(c) Problems to be solved by the invention In the digital phase-locked circuit described above, since the phase comparator is constructed using a binary quantized phase ratio oscillator, the phase comparison information is the phase difference between the input and output. It is binary information of lead or lag, and the phase cannot be controlled by the size of the phase difference. Therefore, when the circuit starts operating, or when the in-phase 1 goes out due to input signal dropout, etc., the input/output position may change. It cannot be said that the synchronization pull-in speed is necessarily sufficient when the phase difference is large.

The present invention overcomes the above-mentioned drawbacks and provides a phase synchronized circuit which calculates the phase difference between input and output by calculation and controls the phase of the output signal based on the calculation result.

(Means for Solving Problem 1) The present invention converts an input signal from analog to digital using a local clock,
The phase difference between the input signal and the output clock is calculated by calculating the polarity change point of the input signal from the current A/D converted input signal amplitude at one interval and the A/D converted input signal amplitude at the previous clock. This is a phase synchronization circuit that calculates the following information and controls the six phases of the output signal based on this information.

(E) Function The present invention is configured as described above, converts an input signal from analog to digital, and calculates the phase lead or delay between the input signal and the output clock and the phase shift thereof based on the amplitude of adjacent input signals. The phase difference can be used to control the frequency of phase control depending on the magnitude of the phase difference.

(f) Embodiment FIG. 1 is a block diagram of one embodiment of the circuit of the present invention. In the figure, (1) is an input signal source, (2) is an oscillation circuit,
(3) is a time axis control circuit, (4) is a frequency dividing circuit, (5) is a sample quantization circuit, (61Fi polarity inversion position detection/calculation circuit, (71 is an accumulation calculation control circuit, (81 is an output terminal) be.

The input signal source (1) is applied to the sample quantization circuit (5) as a full input of an NRZ signal with a minimum inversion interval of T (maximum inversion frequency f (Hzl=〒)), for example.

The oscillation circuit (2) applies a square wave of 2xMxf (Hz) to the time axis control circuit (3). This signal is applied to the frequency dividing circuit (4) after the time axis control circuit (3) controls the addition or removal of pulses on the time axis.

In the frequency divider circuit (4), the time-axis controlled clock pulse is first divided by M in the M frequency divider circuit (9), and further divided by 2 in the 2 frequency divider circuit (1), and output as an output clock pulse. (8).

In addition, the output of the M frequency divider circuit (9) is used as the A/D sampling clock to be used as the A/D sampling clock included in the sample quantization circuit (5).
A conversion converter is provided, and the output of the divide-by-2 circuit section is provided to an accumulation calculation circuit a included in an accumulation calculation control circuit (71) to select a phase control direction.

In the sample quantization circuit (5), a low-pass filter (12
1, the signal is applied to the A/D converter (1) 1 after removing input signal components of fHz or higher, which is A of the sampling frequency of 2 fHz of the A/D converter (01).

In the A/D converter tl1), it is sampled by the output clock of the M frequency divider circuit (9), and the A/D converted result is applied to the polarity inversion position detection/arithmetic circuit (6).

The polarity reversal position detection/calculation circuit (6) consists of a delay circuit α3 that delays data by one sampling clock and a polarity reversal position calculation circuit (14). It detects whether or not a polarity reversal has occurred between the data delayed by 10 minutes, calculates the distance from the sampling point to the polarity reversal point (71) only when there is a polarity reversal, and uses the result as An example of the calculation of the polarity reversal point at this time will be explained using FIG.

The points at which the input signal limited to the fHz band is sampled at an average rate of 2fH2 are denoted as ■, ■, and ◎, and the A/D at that time is
The converted quantized amplitudes are expressed as 7 people, yB, y(l
shall be. Comparing 7 people and VB, we can see that there is a polarity reversal between 0 points and ■sei, as the signs are different. Therefore, if the point of polarity reversal is set to 0, the distance between ■ and ■ can be expressed by the following equation by Iwagumi approximation between ■ and ■.

I X-B1 = 1yB1°1B A I ,,,<
Formula 1) % Formula % The distance lX-B1 from this sampling point ■ to the polarity reversal point ■ is quantized to lX-B1, and then the distance IX-A from the sampling point ■ to the polarity reversal position ■
l (-1B-1)=IX-81) and is applied to the cumulative calculation control circuit (7).

The cumulative calculation control circuit (7) includes a cumulative calculation circuit t151 and
It consists of a determination circuit αD.

Accumulation calculation circuit (ISl is a polarity inversion position detection/calculation circuit (
Input lX-B1 and lX-Al, which are the outputs of 6), and
The output of the frequency dividing circuit αa controls whether the input signal 1X-81 is cumulatively subtracted or the input signal 1X-Al is cumulatively added. A control signal C1 is output, and when the internal value of the cumulative calculation circuit becomes 0 or less, an advance control signal C2 is outputted and the contents of the cumulative calculation circuit are set to an initial value N.

This operation will be explained using FIG. 3.

After the input signal passes through the LPF, it is sampled at the rising and falling points of the output clock pulse and is sent to the A/D.
converted. As an example, consider a case where the A/D-converted amplitude value yB and the amplitude value 7A delayed by -sample at that time are as shown in FIG.

When the distance IB-A1 between sampling points is 16 and the division ratio M is 16, if the values of yB and yA are substituted into C equation 1) and quantized, lX-Al and lX-1) are obtained as shown in Figure 3. It is required as follows.

In other words, when comparing the amplitude value yB and 7 people to determine whether or not the sign is reversed, there is a sign reversal for 7 people and 7B in ■, ■, ■. It can be seen that the amplitude crosses the zero level. Therefore, using the interval ■ as an example and calculating using (Equation 1), it becomes 13x16 +w13, and lX-B1 is 13.1γ-A1 x 16-IX-B
The result will be 1-3. In the calculation of 01, the phase difference with the output clock is obtained in the same manner.

Next, when considering the case where the falling edge of the output clock and the zero level of the input signal are synchronized, information on the advance and lag of the zero point of the input signal with respect to the output clock can be obtained from the information of the interval where the zero cross point of the input signal exists. Among them, when the output clock is at a LOW level, the input zero cross phase is delayed with respect to the output clock in the section (2), and conversely, in the section @ where the output clock is at a high level, it is advanced.

To be careful, the zero-crossing point of the input signal with respect to the falling point of the output clock has a delayed phase of 17i1 in the sections .

7, the accumulator is 1X-AI for the incoming phase.
, and conversely, subtract 1y=1) for the leading phase.

When the result of this accumulator becomes 2N, an advance control signal C1 is outputted, and when the result becomes reverse KOK:, a delay control signal 02 is outputted and the interior of the accumulator is reset to N. For example, if N is set to 4 in Fig. 3, the contents of the cumulative AT calculator become 4-7 at ■, and 7-9 at ■, exceeding 8 of 2N, so a delay control signal is given to the time axis control circuit and Reset the contents of the accumulator to 4.

In the time axis control circuit, the delay fj which is the output of the cumulative calculation circuit
The period of the output clock is varied by the iJ control signal C1 and the lead control signal C2. The phases are synchronized by increasing the width of the output clock of the oscillation circuit by the oscillation period of 2M/min.

On the other hand, when the advance control signal is output, by adding one pulse to the output pulse of the inverse VC oscillation circuit, it works to reduce the pulse width after 4 minutes by 〒.

(g) Effects of the Invention Since the present invention is configured as described above, time axis control is frequently performed when the phase difference between input and output is large;
When the phase difference is small, time axis control becomes sparse, and as a result,
It is possible to increase the phase synchronization pull-in speed and widen the synchronization pull-in range.

Therefore, the reliability of a transmission system employing this circuit can be improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram of an embodiment of the circuit of the present invention, Fig. 2 is an explanatory diagram of the calculation of the zero loss point of the same circuit, Fig. 3 is a time chart diagram of an example of the operation of the same circuit, and Fig. 4 is a diagram showing the operation example of the circuit. This is a conventional phase-locked circuit. (1), (171... input signal source, (2), (1g
l...Oscillation circuit, (3)...Time axis control circuit,
(8), c24+-...output terminal, (51...sample filtering circuit, 41...polarity reversal position calculation circuit,
(151... Accumulation calculation circuit, 珀... Judgment circuit. Fig. 1

Claims (2)

[Claims] (1) An input signal source, an oscillation circuit that generates an oscillation signal with a constant period, an oscillation signal and a control signal from the oscillation circuit, and the time axis of the oscillation signal is controlled by the control signal to output a clock pulse. a time axis control circuit that outputs the output clock pulse; a phase difference calculation circuit that calculates the phase difference between the input signal from the input signal source and the output clock pulse to form the control signal; and an output terminal that outputs the output clock pulse. In the phase-locked circuit that reproduces an output clock pulse synchronized with the input signal, the phase difference calculation circuit changes the time axis control interval according to the magnitude of the phase difference between the input signal and the output clock pulse. A phase synchronized circuit configured to form a control signal. (2) The phase difference calculation circuit includes a sample quantization circuit that samples an input signal from the input signal source using the output clock pulse, A/D converts the sampled value, and outputs a digital amplitude; If a polarity change occurs between the digital amplitudes at adjacent sampling points by inputting , a polarity reversal position calculation is performed to calculate the distance between the polarity reversal point and the adjacent sampling point in the sampling period that causes this polarity change. a cumulative calculation circuit that inputs the output of the polarity reversal position calculation circuit and adds or subtracts an initial value N; and a determination circuit that determines the output of the cumulative calculation circuit and provides a control signal to the time axis control circuit. Claim No. 1 (1) characterized by
) The phase-locked circuit described in section 2.