SU1716616A1 - Digital demodulator of signals of phase-different modulation - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase noise immunity when the signal frequency deviates from the nominal value. The digital demodulator contains limiter-shaper 1, generator 2, phase-to-digital converter 3, shaper of 4 clock pulses, compensating adder 5, multichannel delay line 6, phase-discriminator 7, decisive block 8, averager 9 consisting of pulse sensor 10 and reversible counter 11, a low pass filter 12 and a second phase difference calculation unit 13. The goal is achieved through the implementation of automatic compensation of the parasitic phase shift using a phase self-tuning ring containing an adder 5, a discriminator 7 and an averager 9. 3 Il. .

Description

cl

WITH

oh oh

IS

The invention relates to radio engineering and can be used in output devices for demodulating signals.

The purpose of the invention is to increase noise immunity when the signal frequency deviates from the nominal value.

FIG. Figure 1 shows the structural electrical circuit of the proposed digital demodulator; Figures 2 and 3 show tables explaining the operation of the digital discriminator and the compensating adder.

The digital demodulator contains a limiter-shaper 1, a generator 2, a phase-to-digital converter 3, a 4-clock pulse generator, a compensating adder 5, a multichannel delay line 6, a phase-digit discriminator 7, a decisive block 8, an averager 9, consisting of a sensor 10 pulses and a reversible counter 11, a low-pass filter 12, a block 13 for calculating a second phase difference.

The digital demodulator works as follows.

The input sinusoidal signal with the second-order phase-difference modulation (FRM-2) is fed to the input of the limiter —former 1, where it is limited and the pulse sequence is formed. During positive half-periods of the signal, the amplitude of the pulses becomes equal to a logical one, and during negative periods to a logical zero. From the output of the limiter - former 1, the limited and generated signal is fed to one input of the phase-to-digital converter 3, to the other input of the same phase-to-digital converter 3 pulses are received from the generator 2 with frequency f0, and the control input receives the clock pulses from the 4 clock pulse former. At the outputs of the phase-to-digital converter 3, at the time of the leading edge of each clock pulse, a certain binary number is set, numerically equal to the number of periods of the frequency fo, received on the phase-converter converter 3 during the time interval that began at the moment when the trailing edge of the previous clock pulse was established and ended at the moment of the next clock the leading edge of the pulse signal.

This binary number at the output of the phase-to-digital converter 3 will be proportional to the current instantaneous phase value of the bounded and generated signal, measured at the time of the clock pulse.

The maximum value of the binary number, equal to 2P, corresponds to the maximum value of the signal phase, equal to 2n (360 °). Consequently, the accuracy of Yes, the change in the instantaneous value of the phase of the signal is equal to

ten

Yes

360 ° 2

The number n bits of the binary number selected from. conditions of required accuracy; Yes, the measurement of the instantaneous value of the signal phase is determined by the ratio

, g ..

where Yes, the accuracy of the measurement of the instantaneous value of the signal phase, expressed in degrees, is necessary.

The frequency fo of generator 2 is determined from the ratio

f About 2 fcHOM,

where sleep is the nominal frequency of the signal,

The clock select frequency fT is determined by the allowable telegraph distortion that the demodulator receives and the nominal frequency fc of the signal

100 n fcHOH

FT

to

where K 2, 3, 4;

T - the duration of the elementary parcel, p.

With a nominal signal frequency and no phase shift manipulation, instantaneous

the value of the current phase of the signal at the output of the phase-to-digital converter takes a random value that does not change from one clock cycle to another.

Current instantaneous phase value

the signal is fed to the inputs of a multichannel delay line 6, in each channel of which the corresponding binary number is delayed by an amount equal to the duration T of one

elementary parcel.

At the nominal frequency of the TCHOM signal and the oscillation phase of the compared (neighboring) parcels being equal, the parasitic phase shift DN, equal to the difference between the instantaneous values of the current and delayed phases of the signal, is zero, and the instantaneous values of these phases are the same and unchanged. If the deviation A f of the signal frequency from the nominal value differs from zero, then the instantaneous value of the current and delayed phases of the signal will slowly change with a repetition frequency of A f, and the parasitic phase shift A. p will remain unchanged and be determined by

  2L Af T,

where Af is the frequency deviation of the signal from the nominal value, Hz;

T - the duration of the elementary parcel.,

The presence of a parasitic phase shift A (f between the current and delayed values of the signal phases leads to a significant deterioration in the noise immunity of the autocorrelation demodulator.

Therefore, in order to improve the noise immunity of the digital demodulator of the second-order phase-difference modulation signals, it automatically performs the parasitic phase shift compensation using the phase-locked loop containing the compensating adder 5, the phase-discriminator 7 and the averager 9 consisting of connected sensor 10 pulses and reversible counter 11.

Ring phase locked loop works as follows.

The current value of the phase of the signal from the output of the phase-to-digital converter 3 is fed to the first inputs of the compensating adder 5. The second inputs of the same adder 5 receive the correction code generated by the series-connected phase-discriminator

7 and the averager 9. When adding a binary number corresponding to the current value of the phase of the signal and a binary number corresponding to the correction code, the current value of the phase of the signal gets such an increment of phase at which Doway's parasitic phase shift is compensated.

The adjusted value And the current phase of the signal from the outputs of the compensating adder 5 is fed to one of the inputs of the phase-digital discriminator 7 and the decision block 8, to the other inputs of the phase-digital discriminator 7 and the decision block

8 delayed value of B phase

signal from the outputs of the multichannel line 6 delay.

The phasocyte discriminator 7 is a device in which each pair of binary n-bit numbers A and B arriving at its inputs corresponds to a certain (n-1) -bigth binary number Z at its output. This number Z remains unchanged for a period of time equal to the period of the clock frequency FT, and can change only at the instant of action of the clock pulses. The most significant (p − 1) bit of this number Z is a sign-controlling bit, indicating the need to increase or decrease the correction code. The remaining bits (Cu, Q2 ... Qi ... Qn-2) determine the magnitude of the phase mismatch AZ in the form of (n-2) - bit binary number. The circuit implementation of the phase-discriminator 7 can be represented as a programmable memory or as a combination circuit.

The principle of operation of the phase-digit discriminator 7 can be clarified using table-1 located in FIG. 2, which shows the state of the outputs of the phase-to-digital discriminator 7 depending on the size of four-bit (p 4) binary

the numbers A and B. The state of the highest (n-1) bit is indicated by + or - signs, the O sign corresponds to the O sign, and the 1 sign corresponds to the phase mismatch At is represented in the decimal code.

The output of the phase-digital discriminator 7 is connected to the input of the averager 9, which consists of a sensor 10 pulses and a reversible counter 11. The sensor 10 pulses in

the time of arrival of each clock pulse forms a pulse sequence (burst) consisting of pulses, the number of which is numerically equal to the value of phase mismatch AZ. Wherein

pulse repetition frequency should be such that the maximum number of pulses in a packet equal to (), can be formed and arrive at the counting input of the reversible counter 11 during

a length of time equal to the duration

one period frequency FT clock pulses.

From the output of the sign-guiding (p-1) bit of the phase-discriminator 7 on

the control input of the reversible counter 11 receives a signal (O or 1), which determines the direction of counting in the reversing counter 11. At the signal O, which corresponds to the + sign, the number recorded in the reversing counter 11 will add up to the number of pulses received at its counting input, and at 1, corresponding to the sign, the number of pulses received at the counting input of the reversing counter 11 will be subtracted from the number written in the reversing counter 11. Therefore, the number recorded in the reversing counter 11 will increase or decrease Depending on whether an increase or decrease in the correction code is required in order to compensate for the parasitic phase shift.

The high bits of the multi-bit output of the reversible counter 11, on which the correction code is formed, are connected respectively to the second inputs of the compensating adder 5. The larger the bits in the reversing counter 11, the greater the binary number can be written at its output, the potentials of the older ones will change less often. bits, and consequently, a higher averaging can be obtained when forming a correction code, but the ring phase-locked loop will be more inertial. Therefore, the number of bits of the reversible counter 11 is determined by the maximum allowable time for the phase locking ring to synchronize.

When the phase-locked loop is operating, on one of the inputs of the compensating adder 5, a correction code is automatically set such that the phase shift D between the values of phase A and B tends to 0 or l. When one of these two points of stable equilibrium is reached, the phase-to-digital discriminator 7 will start to give out zero values of the phase mismatch D2, and the correction code will remain unchanged, therefore, the phase-locked loop will go into synchronism.

The corrected value A of the current signal phase arrives at some inputs of the decision block 8, the delayed value B of the phases of the same signal is fed to the other inputs.

Decision block 8 performs actions on binary n-bits A and B, which result in each pair of binary numbers corresponding to a certain state of O or 1 output, decision block 8. The principles of operation of decision block 8 can be changed using Table 2, located in fig. 3, where the state of its output is shown depending on the values of four-bit binary numbers A and B arriving at its inputs.

A schematic implementation of a decision block 8 can be represented as a programmable storage device or as a combinational circuit.

Output of the decision block 8 through the low pass filter 12; providing filtering of high-frequency components,

connected to the input of the second phase difference calculating unit 13, which eliminates the ambiguity of the solutions in the output pre-modulated signal and ensures the formation of output pulses.

The use of a phase locked loop containing a compensating adder 5, a phase-discriminator 7 and

averager 9, consisting of series-connected sensor 10 pulses

and reversible counter 11, provides increased noise immunity of the digital demodulator of the second-order phase difference modulation signals when the signal frequency deviates from the nominal value

and reduces the stability requirement of the signal delay due to the automatic compensation of the parasitic phase shift Ay, arising between the current and delayed values of the signal phase.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION A second order digital demodulator of phase difference modulation signals comprising a limiter driver, a generator, a clock pulse generator whose input is connected to the generator output, a phase-digital converter whose first input is connected to the generator limiter output, the second input is connected to the generator output , and the control input is connected to the output of the clock pulse generator, a multi-channel delay line, the inputs of which are connected to the corresponding outputs The converter input and control input are connected to the output of the clock pulse generator, the decision unit, the first inputs of which are connected to the corresponding outputs of the multichannel delay line, the second phase difference calculation unit, the input of which is connected to the output of the low-pass filter, the input connected to the output a decision block, characterized in that, in order to increase the noise immunity when the signal frequency deviates from the nominal value, a phase-digit differential screader, averager, a compensating adder, stems whose inputs are connected to respective outputs fazotsifrovogo transducer fazotsifrovogo discriminator first inputs connected to respective outputs of the offset adder and the second inputs of decision block, the second discriminator fazotsifrovogo inputs connected to respective outputs of a multichannel delay line averager comprises sensor pulses and reversing schetchiFig 2 The sensor pulse inputs are connected to the corresponding outputs of the phase-digital discriminator, the control input of the pulse sensor is connected to the output of the clock pulse generator, and the output is connected to the counting input of a reversible counter, the control input of which is connected to the sign output of the phase-discriminator discriminator, and the outputs of the higher bits of the reversible counter are connected to the second inputs of the compensating adder. h Јig.Z