JPS6318664A - Charge transfer type solid-state image sensing element - Google Patents

Abstract

PURPOSE:To enhance the numerical aperture to a large extent, by expanding gate electrodes, which are formed at an n-th layer, into an area other than a vertical CCD, i.e., an area, in which insulating isolation is required, and providing two functions of a CCD electrode and an insulating and isolating electrode in this layer. CONSTITUTION:A vertical shift resistor 20 is constituted by gate electrodes 21-a, 22-a and 23-a. The electrodes 21-a and 22-a are connected to, e.g., interconnections 21-b and 22-b, which are provided in the horizontal direction. The electrodes are further connected to common interconnections 51 (phi1) and phi2), to which, e.g., clock voltages in first and second phases are applied, and which are provided at the right end. An insulating and isolating plate electrode 23-b is provided between optical diodes 5 or between the optical diode and a CCD and connected to the gate electrode 23-a. The electrodes 23-a and 23-b are connected to a common interconnection 53 (phi3), which supplies a clock voltage. A CCD electrode and the insulating and isolating functions are provided in an area, in which insulation and isolation are required.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention uses a charge transfer device (Charge T) to extract optical information from a photoelectric conversion device provided on a semiconductor substrate.
The invention relates to a solid-state image sensor using a transfer device.

[Conventional technology]

Solid-state imaging devices require an imaging plate with a resolution comparable to that of the imaging electron tube used in current television broadcasting, and for this reason, 500 pieces in the vertical direction and 800 to 1 piece in the horizontal direction are required.
A matrix of 000 picture elements (photoelectric conversion elements) and a corresponding scanning element are required. therefore,
The above-mentioned solid-state image sensing device is manufactured using MO3 large-scale circuit technology that requires high integration, and generally uses a CCD, a MOS transistor, or the like as a component.

Figure 2 shows the basic configuration of a CCD type solid-state image sensor, which is characterized by low noise (for example, Origuchi et al., "Study of Vertical Overflow Structure CCD Image Sensor," Proceedings of the 1981 Television Society National Conference, pp. 57-58. ). 1 is a photoelectric conversion element consisting of a photodiode, 2a, 2b, 2
c and 2d are vertical CCD shift registers for transferring optical signals accumulated in the photoelectric conversion element group in the vertical direction V;
3 is a horizontal shift register for taking out the signals from each vertical CCD shift register to the output terminal 4-2 of the signal detection circuit 4-1. 5-1.5-2.6-1.6-2 is a clock pulse generator for producing clock pulses for driving each vertical shift register and horizontal shift register. Further, numeral 7 represents a transfer gate which sends the charge N-multiplied by the photodiode 1 to the vertical shift register 2.

In its current form, this element becomes a monochrome image sensor, and by stacking a color filter on top of the photoelectric conversion element, each photodiode accumulates color information and becomes a color field image element.

□ As is well known, solid-state imaging devices have many advantages over electron tubes, such as being small, lightweight, maintenance-free, and low power consumption, and are expected to have a promising future as imaging devices.

However, conventional CCD type image sensors have had the following problems.

(1) Interlaced scanning is performed in the vertical direction, but 1
In this image sensor, for example, the pixels in the odd rows (1, 3, 5, . . . , 2N-1) in the first field are the pixels in the even rows (2, 4°6, . . . 2N-1) in the second field. ) are read out. As a result, in the first field of the next frame, the signals from the rows that were not read in the previous field (that is, the odd rows) are added to the new signals and read out (this phenomenon is generally called afterimage). ).

(2) As mentioned above, in each field, pixel signals are read only in every row. For this reason, in the case of a color element, restrictions are imposed on the arrangement of color filters and signal processing, and a resolution corresponding to only half of a pixel in the vertical direction can be obtained.

As a method for solving the above two problems, the inventors have previously applied for a CCD type image pickup device as shown in FIG. 3 (Japanese Patent Application No. 174923/1982).

FIG. 3 is a diagram showing the configuration of this device. The difference from the conventional device shown in FIG. 2 is the vertical CCD shift register and the horizontal CCD shift register.

In FIG. 3, the vertical CCD shift register 20 has a gate ffi! with wiring in the horizontal direction. 21 and 22, and a gate electrode 23 extending vertically so as to cover the shift register 20. This shift register 20 has three electrodes 21. ．． 23a.

22 by Schiff l-Register 1 pit 1~force” 4ff
will be accomplished. As a result, the signal charge accumulated in the photodiodes in each row is 1, which corresponds to the photodiode pitch in the vertical direction.
Bits make it possible to transfer signal charges independently for each row, making it possible to read out information from all rows of photoelectric conversion elements in each field (conventional jump readout of elements can be changed). ). Along with this, horizontal CC
The D shift register also requires a transfer method that sends twice as much information as conventional elements.

FIG. 4(a) is a plan configuration diagram showing an enlarged part of the vertical COD shift 1 noister distribution area. 21° 22 are the wiring 21b (not shown) and the electrode (22b) which also serves as
1 is the first layer, 22 is the second layer made of polycrystalline silicon, for example), 23a is the third layer electrode 23,
In order not to cross the photodiode area, the photodiode area is laid out vertically.
It is a cross-sectional structural diagram cut along the -x' plane. 10 is a thick oxide film for electrically insulating and separating the photodiode 1d and the vertical CCD or photodiode; 9 is an active region (CO
A thin oxide film for forming the D region or transfer gate region 70), 23 indicates a third layer electrode running vertically. Figure 4(c) is a cross-section of landscaping taken along the y-y' plane of Figure 4(a), and 21°22.23 are the electrodes of the first, second, and third layers. It shows. Further, 20d is a buried channel layer (for example, the second conductivity type, which is the same type as a photodiode) formed on the substrate 8 (for example, the first conductivity type). (not necessary). Here, the vertical CCD 20 has a three-phase driving force type, but if you are willing to increase the number of phases, then the n-phase (
n>3). Further, although the horizontal CCD is also shown to be a three-phase driving force type, it is only necessary to be able to send two rows of optical signals, and it may be m-phase (m>2).

[Problem that the invention seeks to solve]

This solid-state imaging probe with a three-phase structure solves the above two problems and has many practical advantages. Furthermore, in order to improve the photosensitivity, which is another important performance of this image sensor, from the current level, it is desirable to adopt a planar structure that maintains this three-layer structure and does not create irregularities in the oxide film. In other words, when attempting to provide electrical insulation between photodiodes or between a photodiode and an OZCD using a thick oxide film as shown in FIG. Dig into it.

This reduces the area of the CCD and photodiode.

If the area of the COD is designed to be large in advance in consideration of this decrease, the aperture area (area that is illuminated by light) will decrease and the photosensitivity will decrease. This decrease in aperture area will become significantly larger in the future if the number of pixels is increased to improve resolution, which is a problem.

In order to prevent the aperture ratio from decreasing, as mentioned above, 9 pixels per C,! It is possible to consider adopting a planar structure (a structure without thick oxide film regions) in which each region of the edge is formed of a flat thin oxide film. In order to realize this planar structure, a new insulation isolation structure that does not rely on oxide films is required.

An object of the present invention is to provide a CCD type image sensor that achieves a dielectric isolation structure.

[Means for solving problems]

The present invention extends the gate electrode formed in the n-th layer (for example, the first layer) to a region other than the vertical CCD, that is, a region that requires insulation isolation, in a vertical COD for charge transfer of a solid-state image sensor. In this layer, the CCD electrode and insulation separation 1
It is designed to have two functions as a 1i pole.

[Effect]

The present invention provides a CCD electrode with a function as an electrode for insulation separation. Thereby, the overall structure of the element can be made into a planar structure, and the aperture ratio can be significantly improved.

〔Example〕

Hereinafter, the present invention will be explained in detail using Examples.

FIG. 1 is an embodiment showing the structure of an element which is the gist of the present invention. In FIG. 1, 20 is a vertical CCD shift register, 30 is a horizontal CCD shift register, and 70 is a transfer gate. The vertical CCD shift register 20 is
Electrodes 21-a, 22-a.

23-8, electrodes 21-a and 22-a
For example, the arrangement 21-b runs in the horizontal direction.

22-b. For example, a common wiring 51 provided at the right end for applying the first phase and second phase clock voltages.
(φt) and 52 (φ2). 23
-b is an insulating plate electrode provided in a region between the photodiodes or between the photodiodes and the CCl, and is connected to the gate 'GL' pole 23-a. These g-poles 23a, 23-b are connected to, for example, a third electrode provided at the upper end.
They are commonly connected to a common wiring 53 (φ3) to which the phase clock voltage is applied.

FIG. 5 shows an example of the planar layout configuration of the electrode 23, which is a feature of this embodiment (for simplicity, an example of 3×3 pixels is shown).

In this embodiment, the gate electrode 23-a and the plate electrode 23-a
b are arranged in a mesh pattern, and a clock wiring 53 (φ8
)It is connected to the.

6(a) is a diagram showing the planar layout configuration of the constituent unit of the element shown in FIG. 1, that is, a pixel, and FIG. 6(b) is a cross-sectional structure of FIG. 6(a) taken along the Xl-X1' plane. The figure (C) is a cross-sectional structural diagram of the same figure (a) taken along the X2-X2' plane, and the same figure (d) is a cross-sectional structural diagram of the same figure (a) taken along the Each is shown below. In Figure 6 (,), 1
200 is a photodiode region, 200 is a vertical CCD shift register region, 700 is a transfer gate region, 210-a, 220
-a, 230-a is a gate electrode region, 210-b.

220-b is a wiring area. Further, 230-a is a gate electrode region, and 230-b is an insulating separation plate electrode region. Here, insulating separation plate electrode region 230-b
are arranged between the vertical C0D2oO and the photodiode region 1 and between the photodiode regions, but the photodiode regions are separated using the electrodes of the wiring regions 210-b and 220-b. Also, or this wiring area 21
A barrier made of impurities may be provided on the surfaces of the substrates 0-b and 220-b to separate them. At this time, 230-b does not necessarily need to be provided. The plate electrode region 230-b between the photodiodes may be thinner than the wiring region 210-b.

In the same figure (b), 1-a is a photodiode (semiconductor layer of a second conductivity type different from the substrate 8 of the first conductivity type, e.g. n-type), and 200-c is an impurity layer that makes the vertical CCD 200 a buried channel type. (For example, n-type, the wood chips may be omitted if a vertical COD surface channel type is used), and 9o is an active (gate) oxide film. Reference numeral 23o denotes a bottom layer electrode that also serves as a gate electrode 230-a, a separation plate electrode 230-b, and a transfer gate electrode 700-b (here, the transfer gate is also the electrode 230-a, 230-b).
Although the transfer gate is formed as the lowest layer electrode, it is also used as the electrode 230-a, 230-b, etc.
(The electrode may be formed as the first layer, and the transfer gate may be formed using mVA as the second layer.)

330 is an impurity layer provided under the separation plate electrode 230-b. A layer 330 is of the same type as the substrate (for example, p-type) and has a higher impurity concentration than the substrate, and serves to increase the threshold voltage under the plate electrode. Impurity layer 330
The photodiodes, the photodiodes and the vertical CODs, or the vertical CCDs and the horizontal CCDs are electrically isolated (in a state where no charge or current is exchanged) by the plate electrodes.

Here, for example, if the impurity concentration of the substrate is high and a predetermined threshold voltage can be obtained, the impurity layer 330 may be omitted, and in this case, insulation isolation can be performed only with the plate electrode.

In FIG. 6(Q), 210-a is a gate electrode constituting a vertical CCD, and 330 is an impurity layer which is integrated with the isolation plate electrode 230-b to provide insulation between the photodiodes and between the photodiode and the COD. Perform separation.

FIG. 6(d) shows a cross-sectional structure of the vertical CCD 200 taken in the vertical direction. 230-a is a gate electrode formed in the first layer, 210-a is a gate electrode formed in the second layer (or third layer), and 220-a is a gate electrode formed in the third layer (or second layer). The gate electrode was formed using For these gate electrodes, for example, polycrystalline silicon may be used, heat-resistant metals such as Mo and W, or silicides of these metals may be used. Here, the plate electrode 230 is supplied with, for example, I#H+1 from the pulse generator 53 (φ8).
A pulsed voltage consisting of three values: (high), "M" (medium), and "L" (low) is applied.

The gate electrode 230-a is driven by "H" and "L +t, and the separation plate electrode 23 is driven by the 11 M I+ voltage.
It is conceivable to place the area under 0-b in an insulating and isolated state.

FIG. 7 shows the electrodes constituting the vertical CCD 200 at the top.

When distinguishing between middle and lower gate electrodes, the upper gate electrode 210'-
a is formed with the electrode of the bottom layer (first layer), the lower gate electrode 1220-a is formed with the electrode of the second layer, and the middle gate electrode 230'-a is formed with the electrode of the third layer. This is an example in which it is formed by Here, the transfer gate 700 is also formed in the first layer. 210'-b is a separation plate electrode formed in the first layer. Therefore, the wiring 230'-b of the gate electrode 230'-a is connected to the gate electrode 21
It runs above the first layer wiring that constitutes 0'-a.

FIG. 8 shows an embodiment in which the transfer gate is not formed in the first layer as in FIG. 7, but is formed in the same layer as the gate electrode 230'-a. Since the gate electrode 210'-a and the isolation plate electrode 210'-b are connected in the region 210'-b', the transfer gate region (700 part)
In this case, they are not connected as shown in Figure 7. Sunaochi, 1st
Since the electrode in the layer 700 does not exist in the part 700, the electrode 230'-700' in the same layer as the gate electrode 230'-a
will form a transfer gate.

In the above embodiment, the common wiring for supplying voltage to the electrodes 210-a and 220-a was provided at the right end, but it may be arranged at the opposite left end. Further, although the common wiring 530 that supplies voltage to the electrode 230-a is shown as being provided at the upper end, it may be arranged at the lower end (for example, the vertical C
It may be arranged between the CD and the horizontal CCD, or it may be arranged below the horizontal CCD, jumping over the horizontal CCD).

In the embodiment of FIG. 1, the wiring 53' of the electrode 23 is provided on the upper side, but as shown in the embodiment of FIG.
' may be installed, for example, on the left side, wiring 52', for example, on the right side, and wiring 51', for example, on the upper side.
Further, as shown in the embodiment of FIG. 10, the vertical CCD 2
The separation plate electrode 230 may be divided into separate electrodes on the left and right sides of 00. 230-R is a six-separation plate electrode 230 connected to the gate electrode 230-a of the vertical CCD and the transfer gate electrode 700, as in the case of FIG.
-The other is a plate electrode specializing in separation. One end of these electrodes is a common wiring 530-R.

530-L, and a predetermined voltage is applied to each wiring. Here, since the wiring @230-L is specialized in separation and has no other functions, the intermediate voltage (11M +
+), or it may be lowered to a reference voltage (for example, ground voltage) for the element. Alternatively, plate electrode 12
30-L may also have a function other than separation, for example, plate 1 and the pole may be used to absorb excess charge generated when intense light is incident. Charge absorption is commonly referred to as overflow drain).

Although the configuration and structure of the present invention have been described above using examples, it is possible to consider configurations and structures of word types in addition to the examples other than those described above.

For example, min@1! The pole may be formed using the first layer and the second layer (therefore, the number of electrode layers forming the element is n layers [n is an integer of 3 or more]).

An oxide film with the same thickness as that under the gate electrode has been used under the separation electrode, but it does not have to be exactly the same thickness as the gate electrode, and may be slightly thinner than under the gate electrode, or It is also possible to make it thicker.

Further, as shown in FIG. 11, a thick oxide film may be formed in some regions as in the case of the conventional element, and a structure may be adopted in which both a thin oxide film and a thick oxide film are used.

This example is a diagram corresponding to the structure cut along the X2-X2' plane shown in FIG. 6(Q), where 100 is a thick oxide film, 33
0' is an impurity layer (for example, p-type with higher concentration than the substrate) formed under the thick oxide film.

This impurity layer is used to increase the threshold voltage and improve insulation isolation as described above, but this impurity layer may be omitted if there is no problem in isolation. In this structure, the aperture ratio is slightly lower than when all thin oxide films are used as shown in the embodiment of FIG. Compared to this, the aperture ratio is several tens of percent higher and has great practical value.

The isolation structure of the present invention is highly effective in pixel regions (regions composed of vertical CCDs, photodiodes, etc.) that are subject to size constraints both vertically and horizontally, that is, in two-dimensional directions. A horizontal CCD is subject to size constraints in the horizontal direction, but is not subject to size constraints in the vertical direction, so it can take up a sufficient area. Further, since the signal detection circuits 4-1 are not arranged in an array, but are usually one to three, a sufficient area can be allocated in both the vertical and horizontal directions. Taking advantage of these locational characteristics, as shown in FIG. 12, the separation of the pixel area 2000 is made up of a thin oxide film and a separating plate electrode as shown in FIG. 1, and the horizontal CCD area 3000 is ．． Signal detection circuit area 4. OOO, horizontal CCD and vertical CCD open area 5
Separation of 000, etc. may be performed using a thick oxide film similar to the conventional one, or may be performed by adding a plate electrode for separation to the thick oxide film, or an oxide film slightly thinner than the conventional one may be used for separation. This may be done by adding a plate electrode.

Furthermore, in the above embodiments, the case where the horizontal CCD shift register is in one column is illustrated, but when the amount of information transferred is large,
Or, if the scanning speed increases due to high resolution in the future, 2.
A column (Q is an integer of 2 or more) may be provided. When arranging multiple horizontal CCDs in this way, horizontal CCD
A dividing plate electrode may be placed between the horizontal CCDs as described above to provide insulation separation between the horizontal CCDs.
Since there is ample space in the area, a thick oxide film may be used to separate the horizontal CCDs as in the conventional case.

As explained above, according to this embodiment, the three layers (first layer, second layer, third layer) constituting the CCO shift register
In addition to its original role as the gate tx pole for the shift register, one of the conductors in the second layer (layer) has electrical isolation (separation between pixels, separation between two pixels and vertical CCD shift register, vertical CCD Since the receiver can play an important role (such as separating the horizontal CCD shift register and the horizontal CCD shift register), the following effects can be obtained.

Dimensions required for insulation separation (because the area can be significantly reduced,
(1) The opening area can be expanded.

(2) The pixel size can be reduced; (3) CCD
The amount of charge that the shift register can carry can be expanded. These effects bring about improvements in photosensitivity, resolution, dynamic range, etc., and the present invention has great practical value.

〔Effect of the invention〕

According to the present invention, since the entire solid-state imaging probe can have a planar structure, there is an effect that the aperture ratio of the photoelectric conversion section can be increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a conventional solid-state image sensor, and FIG. 4 is an enlarged view of a part of the solid-state image sensor in FIG. 3. , FIG. 5 is a diagram showing a part of FIG. 1 extracted. FIG. 6 is an enlarged view of a part of FIG. 1, FIGS. 7 and 8 are views showing other embodiments of the present invention, and FIGS.
11 and 12 are diagrams showing still another embodiment of the present invention. Agent: Patent Attorney Katsuo Ogawa) 1.・-1 1st concave 210-Q, 220-α, 250-α・・kettodenju 210-b, 220-to・nishi otsu, (zao-b
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Claims (1)

[Claims] 1. A solid-state imaging device consisting of a plurality of photoelectric conversion elements provided on the same semiconductor substrate and a group of charge transfer elements that transfer signal charges accumulated in the photoelectric conversion elements toward output. wherein the gate electrode constituting the charge transfer element group is formed of n conductor layers (n is an integer of 2 or more), and
1. A charge transport type solid-state image sensor, characterized in that an electrode of the layer closest to the substrate among the n layers is provided at least in a pixel separation region between the charge transport element and the photoelectric conversion element, and serves as an electrode for insulation separation. 2. A charge transport type solid-state imaging device according to claim 1, characterized in that the insulation separation electrode is also provided in a pixel separation region between the photoelectric conversion elements.