JPS6318560A - Head switching signal generating circuit for helical scan system tape reproducing device - Google Patents

Abstract

PURPOSE:To facilitate adjusting work by reproducing the leaked part of a reference signal recorded by a first head by a second head, and discriminating the time difference between a head switching signal and the generation timing of a reproduced signal obtained from a second head based on the formerly said reproduced signal of the leaked part. CONSTITUTION:The first head 19 supported by a drum records a reference signal KCK for head switching signal generation in a tape, and the second head 18 reproduces the reference signal KCK leaked from the track corresponding to the first head 19. Based on thus obtained reproduced signal, the time difference between the head switching signal HDCKP and the generation timing of a reproduced signal obtained from the second head 18 is discriminated in order to adjust the generating timings of the head switching signal HDCKP and the generation timing of a reproduced signal obtained from the second head 18. In such a way, the head switching signal HDCKP and the generation timing of a reproduced signal obtained from the respective heads 18 and 19 are automatically adjusted. As a result, the adjusting work is made easier.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a helical scan type tape playback device such as a rotary head type digital audio tape recorder, and particularly relates to a helical scan type tape playback device such as a rotary head type digital audio tape recorder. The present invention relates to a head switching signal generation circuit that generates a head switching signal for selecting each obtained reproduction signal.

(Conventional Technique v/A) As is well known, in the field of sound quality equipment, information signals such as audio signals are processed using PCM (Pulse Code Modulation) in order to record and reproduce information with as high density and high fidelity as possible. ) technology, digital recording and reproducing systems that convert data into digitized data, record it on a recording medium, and reproduce it are becoming widespread.

Among these, those that use magnetic tape as a recording medium are called digital audio chip recorders.
For example, there are fixed head types with multiple heads arranged in the width direction of the tape, and helical scans in which the tape is wound around a cylindrical drum with heads that rotate along the circumference. There is also a rotating head type.

Here, FIG. 11 shows the overall configuration of the rotary head type digital audio chip recorder.

That is, reference numerals 11 and 12 in the figure denote a pair of reel stands, which are each rotated counterclockwise in the figure by reel motors 13 and 14, so that the tape 15 is run in the direction indicated by arrow a in the figure. being done.

Further, a cylindrical drum 16, a capstan 17, and a pinch roller (not shown) are arranged between the pair of reel stands 11 and 12.

Among these, the drum 16 has a pair of recording/reproducing heads (hereinafter referred to as heads) facing outward from each other with the center of rotation in between.
18.19 is supported. Also, this drum 16
is rotated counterclockwise in the figure by a drum motor 20.

During recording and reproduction, the tape 15 is placed on the drum 16 within an opening angle range of 90' from the center of the drum 16, as shown in the figure.
It is wound diagonally around the circumferential side of 6 with a certain inclination. Further, the capstan 17 is connected to a capstan motor 21.
The pinch roller is rotated counterclockwise in the figure at a constant speed, and the pinch roller is pressed against the tape 15, so that the tape 15 is run at a constant speed. Therefore, on the tape 15, tracks corresponding to the head 18 and tracks corresponding to the head 19 are alternately formed with a constant inclination.

In this case, the head 18 is supported by the drum 16 at an azimuth angle of +20° with respect to the track forming direction, and the head 19 is supported at an azimuth angle of +20° with respect to the track forming direction.
It is supported by the drum 16 with an azimuth angle of 0°.

Next, the recording/reproducing operation will be explained. First, at the time of recording, digitized data D is obtained by converting the information signal into PC~1.
ATAR is provided to input terminal 22 . Then, the digitized data DATAR is added with various control data D outputted from the clock generation circuit 24 and described later by the adder circuit 23, and then sent to the head 18. 19.

Here, the clock generation circuit 24 generates the control data D and other clock signals to be described later, based on a system clock signal SC of a constant frequency supplied to the system clock signal input terminal 28.

The switch circuit 25 also includes a clock generation circuit 24.
Switching is controlled based on the recording head switching signal (hereinafter referred to as recording head clock signal)-IDcKR output from the recording head switching signal (hereinafter referred to as recording head clock signal). That is, the switch circuit 25 uses the recording clock signal HDCKR to control the period adding circuit 23 during which the head 18 is in contact with the tape 15.
The adding circuit 2 is switched to lead the output data to the head 18, and the period when the head 19 is in contact with the tape 15
It can be switched so that the output data of No. 3 is guided to the head 19.

Further, the gate circuits 26 and 27 have a recording/reproducing mode input terminal 29 to which an H level signal is supplied in the recording mode and a threshold level signal in the reproducing mode.
State where H level signal is supplied (that is, recording mode)
At this point, the gate is opened, and the output data of the adder circuit 23 is supplied to the heads 18 and 19.

Therefore, in the recording mode, the digitized data DATAR supplied to the input terminal 22 is alternately supplied to the heads 18 and 19, and the digitized data DATAR is recorded onto the tape 15 here. be.

Furthermore, during reproduction, the reproduced signals RF obtained from each head 18 and 19 are taken out via capacitors C1 and C2, amplifiers 30 and 31, equalizer circuits 32 and 33, and switch circuit 34, respectively, and are supplied to data slice circuit 35. be done. This switch circuit 34 uses a reproduction head switching signal (hereinafter referred to as a reproduction head clock signal) HDCKP output from a position signal detection control circuit 36 to be described later.
The switching is controlled based on the following.

That is, the switch circuit 34 is switched to guide the reproduction signal RF of the head 18 to the data slice circuit 35 during the period when the head 18 is in contact with the tape 15 by the reproduction RAD clock signal HDCKP, so that the head 19 is connected to the tape 15. The reproduction signal RF of the head 19 is switched to be guided to the data slice circuit 35 during the period when the head 19 is in contact with the head 19 . Therefore, the data slice circuit 35 is alternately supplied with reproduced signals @RF obtained from each head 18 and 19.

Here, the data slice circuit 35 waveform-shapes the input reproduction signal RF and converts it into digitized data DATAP.
is generated. The generated digitized data DATAP is supplied to a demodulation/reproduction circuit system (not shown) via an output terminal 37.

In addition, the above digitized data DATAP is processed by PLL (
The clock signal PLGK is supplied to a phase-locked loop (phase locked loop) circuit 38 to generate a data handling clock signal PLGK.

This data extracting clock signal PLCK is supplied to the to+i reproducing circuit system via the output terminal 39 and tl
1 replay operation is performed, and the data recorded on the tape 15 is played back.

Next, the drum motor 20 is controlled by a drum servo circuit described below so that its rotational speed is constant. That is, in the vicinity of the drum 16, there are a head 40 for frequency detection and a head 4 for position detection.
1 is installed. Among these, the head 40 is a rotating body (not shown) that is rotated together with the drum 16 and has an alternating pattern (FG pattern) for frequency detection formed thereon.
It generates a frequency signal pFG corresponding to the rotational speed of the drum 16.

Then, the frequency signal DFG obtained from the head 40 is
is connected to an automatic frequency comparison circuit (hereinafter referred to as A) via an amplifier 42.
The clock signal AFCCK is supplied to an FC circuit (referred to as an FC circuit) 43, and is compared in frequency with a reference clock signal AFCCK output from the clock generation circuit 24. This AFC circuit 43 generates a voltage signal according to the frequency difference between the frequency signal DFG and the reference clock signal AFCCK, and outputs it to the adder circuit 44.

On the other hand, the heads 41 are installed facing a rotating body (not shown) that rotates together with the drum 16 and has a magnetization pattern for position detection formed thereon, and each head 18. A position signal DPG is generated as a reference for determining the position of 19.

Then, the position signal DPG obtained from the head 41 is transmitted to the position signal detection control circuit 36 via the amplifier 45.
supplied to This position signal detection control circuit 36 detects the input position signal DPG and generates a phase signal MDPG. And the position signal detection device m+ circuit 36
The phase signal MDPG obtained from the automatic phase comparison circuit (
The signal is supplied to an APC circuit (hereinafter referred to as an APC circuit) 46, and is compared in phase with a reference zero clock signal APCCK output from the zero clock generation circuit 24. This APC circuit 46 generates a voltage signal according to the phase difference between the phase signal MDPG and the reference clock signal APCCK, and outputs it to the addition circuit 44.

Therefore, the adder circuit 44 is connected to the AFC circuit 43 and the AFC circuit 43.
The voltage signals respectively output from the PC circuit 46 are added. The voltage signal output from the adder circuit 44 is supplied to the drum motor 20 via an equalizer circuit 47 and a drive circuit 48, so that the drum motor 20 is controlled to have a constant rotational speed. Here, the rotational speed of the drum 16 is controlled to be constant (100/3 Hz).

Here, in the drum servo circuit as described above, A
FC circuit 11343 generates frequency signal DFG and standard O
The APC circuit 46 is controlled so as to be driven in a state in which the frequency difference with the check signal AFCCK is within a certain range.

The position signal detection control circuit 36 also controls the head 4.
Based on the position signal DPG obtained from 1, a reproducing RAD clock signal HDCKP for switching the switch circuit 34 is generated.

Next, the rotational speed of the capstan motor 21 is controlled by a capstan servo circuit described below. That is, a frequency detection head 49 is installed near the capstan 17. This head 49 is installed opposite to a rotating body (not shown) which is rotated together with the capstan 17 and has an AC magnetization pattern (FG pattern) for frequency detection formed thereon, and the rotation speed of the capstan 11 is Frequency signal CF corresponding to
It generates G.

Then, the frequency signal CFG obtained from the head 49 is
is connected to the capstan servo circuit 51 via the amplifier 50.
supplied to This capstan servo circuit 51 is in a state in which an H level signal is supplied to a recording/reproduction mode input terminal 52, which is supplied with an H level signal in the recording mode and an L level signal in the reproduction mode. In other words, in recording mode), the frequency signal CFG and the reference clock signal SCK output from the clock generation circuit 24 are compared in frequency, a voltage signal corresponding to the frequency difference is generated, and the frequency signal CFG is divided. The phase of this signal and the reference clock signal SCK are compared, a voltage signal corresponding to the phase difference is generated, and these two voltage signals are added and output.

The voltage signal output from the capstan servo circuit 51 is supplied to the capstan motor 21 via an equalizer circuit 53 and a drive circuit 54, thereby controlling the capstan motor 21 to a constant rotation speed. In the recording mode, the rotational speed of the capstan 17 is constant, that is, the running speed of the tape 15 is constant (
8,150+v+/S).

In addition, in the state FJ in which an L level signal is supplied to the recording/reproduction mode input terminal 52 (that is, reproduction mode), the capstan servo circuit 51 receives the frequency signal CFG and the reference signal output from the clock generation circuit 24. The frequency is compared with the clock signal SCK to generate a voltage signal according to the frequency difference, and the phase of the tracking error signal TE output from the ATF circuit 55, which will be described later, is compared with the reference clock signal SCK to determine the phase difference. It generates a voltage signal according to the voltage signal, adds these two voltage signals, and outputs the result. This voltage signal is then supplied to the capstan motor 2.0 via the equalizer circuit 53 and the drive circuit 54, so that the rotational speed of the capstan 17, that is, the running speed of the tape 15 is controlled here in the playback mode. It is something that becomes.

Here, the ATF circuit 55 includes the switch circuit 3.
4, the reproduction head clock signal HDCKP output from the position signal detection control circuit 36, and the digitized data DATAP output from the data slice circuit 35. is supplied. Although the detailed operation will be described later, this ATF circuit 55 uses the rad clock signal HDCKP and the digitized data DATAP for reproduction while the tape 15 is being reproduced, and utilizes the ATF signal included in the reproduction signal RF. A tracking error signal TE corresponding to the tracking deviation between each head 18, 19 and each track formed on the corresponding tape 15 is generated.

Therefore, in the playback state, the capstan motor 2
1, the rotational speed is controlled based on the tracking error signal TE, and the running speed of the tape 15 is controlled.
At this point, tracking servo is performed to eliminate the above-mentioned tracking deviation and to ensure that each head 18, 19 accurately traces the center of the corresponding track.

Further, the reel motors 13 and 14 receive a reel motor control signal RMS output from the clock generation circuit 24.
1. RMS2 is rotationally driven at a predetermined rotational speed by being supplied via drive circuits 56 and 57, respectively,
Supply of tape 15 from reel stand 11 and reel stand 12
The tape 15 is wound up by the following steps.

Next, FIG. 12 shows the format of tracks formed on the tape 15. In other words, one track consists of 196 blocks, with 1 block in the center.
2870 blocks are the data area in which digitized data converted into PCM is stored. Further, the control data D is recorded on both sides of this data area.

Here, the control data D is 1 from the upper side in FIG.
1 block margin data MARGIN.

2 blocks of PLL data, 8 blocks of subcode data, 5UB1.1 block of postamble data PA
, 3 blocks of IBG data, 5 blocks of ATF data, 370 blocks of IBG data and 2 blocks of PLL
Data is recorded in order.

Further, the control data D is 11 from the upper side in FIG.
In the following order: Margin data of block MARGIN, 1 block of postamble data PA, 8 blocks of subcode data 5UB2.2 blocks of PLL data, 3 blocks of 18G data, 5 blocks of ATF data, and 3 blocks of 18G data. recorded.

Then, in the above data area, the digitized data is converted from 8 bits to 10 bits and converted to NRZ (non-return l).
・UzeO) It is modulated and recorded.

Further, the subcode data 5UBI and 5IJB2 are information signals indicating the song number, absolute time, etc. Roughly speaking, the above PLL data is the above subcode data 5UB1.5
This is an information signal for generating UB2 and the data extraction clock signal PLCK, and is a single wave of fch/2 (fch is a data rate of 9,408 M lx ).

Further, the margin data MARGIN and postamble data PA are f ch/2, respectively, and IBG
The data is a single wave of f ch/6.

Here, the above 1 block consists of 3 blocks as shown in FIG.
It consists of 6 symbols. Of these, the central 2
The 8 symbols are a data area in which digitized data is stored. Also, on the left side of this data area in the diagram,
Four symbols of 1Ii device'fJ data are recorded, and four symbols of parity data pa are recorded on the left side of the data area in the figure.

The above one symbol consists of 8 bits,
As shown in FIG. 14, the four-symbol device I control data consists of one symbol of sync data 5YNC, two symbols of words W1 and W2, and one symbol of parity data pb. Here, word W1 indicates the number of channels, emphasis, track pitch width, etc., and word W2 indicates a block address.

Further, the ATF data is transmitted to the track corresponding to the head 18 by a synchronization (SYNC) signal 5, as shown in FIG.
1 (fch/18) and a pilot signal (shown in a grid pattern in the figure) P (single wave of fch/72) are formed, and a synchronizing signal 32 is sent to the track corresponding to the head 19.
(fch/12) and a pilot signal (shown in a grid pattern in the figure) P.

In FIG. 15, arrows C indicate the moving direction of the heads 18 and 19, and arrow C indicates the running direction of the tape 15.

Next, the tracking servo will be explained. This tracking servo is generally an area-divided ATF.
(Automatic Track Finding) system is adopted, and among these, a 4-track self-contained system is actually used.

That is, consider that the head 19 traces the second track from the top in FIG. First, when one head reaches the recording portion of the synchronization signal S2, the ATF circuit 55 activates the above position! ! Based on the reproduction head clock signal HDCKP output from the signal detection 11ti11 circuit 36, it is determined that the reproduction signal RF from the head 19 is supplied, and the data slice circuit 3
The synchronization signal S2 is detected based on the digitized data DATAP outputted from the synchronization signal S2.

Then, the ATF circuit 55 detects the level at which the head 19 reproduces the pi zero bit signal P leaking from the adjacent track (the top track in FIG. 15) at the timing when the synchronization signal S2 is detected. do. Next, the above ATF
The circuit 55 connects the adjacent trunk (the first
The level at which the head 19 reproduces the pilot signal P leaking from the third track from the top in FIG. 5 is detected. Then, the ATF circuit 55 calculates the difference in the level of leakage between the detected pilot signals, and calculates the difference in level of leakage between the detected pilot signals, which corresponds to which side of the adjacent track the head 19 is biased toward from the center of the track to be traced. A tracking error signal TE is generated.

Thereafter, the capstan motor 21 is controlled as described above based on the tracking error signal @TE generated as described above, and the running speed of the tape 15 is adjusted to lit.
By doing so, tracking servo is applied.

Next, the relationship between the reproduction clock signal HDCKP and the reproduction signal RF obtained from the heads 18 and 19 will be explained. In other words, Fig. 16 (
16(b), the switch circuit 34 converts the reproduction signal RFa obtained from the head 18 into data during the period when this signal is at H level. The switch circuit 34 is switched so as to guide the reproduced signal RFb obtained from the head 19 to the data slice circuit 35 during the L level period.

Then, 1 of the reproduction head clock signal 1-lDCKP
The period corresponds to one rotation of the drum 16, and the reproduction signals RFa and RFb from each head 18° 19 are obtained approximately at the center of the H level and L level periods of the reproduction RAD clock signal HDCKP. It is done like this.

Note that the recording clock signal H[)CKR is also connected to a switch circuit 25 so as to supply digitized data to the head 18 at its H level gate.
At the same time, the switch circuit 25 is switched so that the digitized data is supplied to the head 19 during the L level period. Then, the recording head clock signal @HDCKR and the head 18
．． The relationship with the digitization data supplied to the respective terminals 19 is also substantially the same as described above.

Here, the position signal @OPG for determining the position of each head 18, 19 is rotated integrally with the drum 16, as shown in FIG. The head 41 is placed opposite the formed rotating body 59, and as the rotating body 59 rotates, the magnetization pattern 58 approaches the head 41, thereby generating the magnetic pattern. In this case, the position signal DPG
It is possible to determine which head 18, 19 is in contact with the tape 15 based on the elapsed time since the occurrence of the error, and thereby the head position can be determined.

Therefore, based on the position signal DPG, the position signal detection control circuit 36 operates as shown in FIG. 16(a).

As shown in (b), the reproduction head clock signal HDCKP can be generated in accordance with the generation timing of the reproduction signals RFa and RFb from each head 18 and 19.

However, in the above-described conventional means for generating the reproduction RAD clock signal HDCKP, an error occurs in the mounting position of the head 18, 19 on the drum 16 and the formation position of the magnetization pattern 58 on the rotating body 59. , RAD clock signal for reproduction) (H level and L level periods of DCKP and generation timings of reproduction signals RFa and RFb from each head 18 and 19 are shown in FIG. 16(a).
, (b) is very difficult, and the problem arises that the adjustment work for positioning the heads 18, 19 and the magnetization pattern 58 becomes troublesome.

(Problems to be Solved by the Invention) As described above, the conventional playback RAD clock signal HDC
The KP generation means generates a RAD clock signal HDC for reproduction.
KP H level and L level period and each head 18.1
The reproduced signal RFa- from 9.

There is a problem in that it is very difficult to synchronize the generation timing of RF b.

Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to automatically adjust the head switching signal and the generation timing of the reproduction signal obtained from each head, and to achieve an extremely good helical scan that can simplify the adjustment work. An object of the present invention is to provide a head switching signal generation circuit for a tape playback device based on the present invention.

[Structure 1 of the Invention (Means for Solving Problems) That is, the head switching signal generation circuit of the helical scan type tape playback device according to the present invention generates a head switching signal to the tape by a first head supported by a drum. In addition to recording the reference signal for generation, a second head supported by the drum reproduces the reference signal leaking from the track corresponding to the first head, and based on the reproduced signal obtained from the second head. The head switching signal and the generation timing of the reproduction signal obtained from the second head are determined by determining the difference between the generation timing of the head switching signal and the reproduction signal obtained from the second head, and the head switching signal and the generation timing of the reproduction signal obtained from the second head are adjusted. .

(Function) According to the above configuration, the second head reproduces the leakage of the reference signal recorded by the first head, and the head is regenerated based on the reproduced signal obtained from the second head. The difference between the switching signal and the generation timing of the reproduction signal obtained from the second head is determined, and the head switching signal and the generation timing of the reproduction signal obtained from the second head are adjusted. M work can be made easier.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as the eleventh factor are shown with the same symbols, and only the different parts will be explained here. That is, the reproduced signal RF from each head 18 and 19 selectively guided by the switch circuit 34 is sent to the data slice circuit 3 described above via the connection terminal 60.
The position detection signal PK
used for the production of

The position detection signal PK output from the position detection circuit 62 is supplied to a delay circuit 63 to generate a recording/reproduction data start signal @RPC, and is also supplied to the clock generation circuit 24.

Further, the recording/reproducing data start signal RPD outputted from the delay circuit 63 has a timing 6111111 circuit 64.
supplied to This timing control circuit 64 generates the above-mentioned digitized data DATAR for recording based on the above-mentioned recording/reproduction data start signal RPC, and also generates a fixed O-switch signal KCK for generating a head switching signal, which will be described later. It is something to do.

Then, the digitized data DATAR and the fixed clock signal KCK generated by the timing control circuit 64 are transferred to the switch circuit 25 via the switch circuit 65 controlled by the switching signal K output from the clock generation/circuit 24. It is designed to be guided selectively.

The clock generation circuit 24 also outputs a recording head clock signal HDCKR and a reproduction head clock signal HDCKP for switching and controlling the switch circuits 25 and 34.
is generated, and gate signals RAO and RBO for controlling opening and closing of the gate circuits 26 and 27 are also generated.

Further, the black 9/9 generation circuit 24 adjusts the reproducing head clock signal HDCKP by being supplied with the position detection signal PK.

The operation of the above configuration will be described below with reference to the flowchart shown in FIG. 2 and the timing chart shown in FIG. 3. However, in this case, as shown in FIG. 4, the tape 15 is wound around the drum 16 within an opening angle range of 90' from the center of the drum 16, and the magnetization pattern 58 faces the head 41! In your condition, head 1
8 is the rotation angle of the drum 16, and it is assumed that the drum 16 is located in front of the tape 15 by θ (0<θ<π/2). First, when the digital audio tape recorder is started (step 31), in step S2, the above-described drum servo and capstan servo are performed, and the drum 16 is rotated and the tape 15 is run. Next, in step s3, the digital audio tape recorder is forced into playback mode. At this time, the clock generation circuit 24 is connected to the gate circuit 2.
6. Gate signals RAO and RBO that close both 27
At the same time, a rad floater signal 1-IDcKP for reproduction as shown in FIG. 3(a) is generated.

The frequency of this reproduction RAD clock signal HDCKP is
It is 100/3-, which is the same as the rotational speed of the drum, and the H level period and L level period are made equal. Further, as shown in FIG. 3(b), this reproduction RAD clock signal HDCKP is generated when the device signal @DPG consisting of the head 41 is at H level (that is, when the magnetization pattern 58 is closest to the head 41). It is formed so that it has a rising edge at (when).

That is, the reproduction clock signal HDCKP is generated in synchronization with the reference clock signal APCCK output from the clock generation circuit 24, and the phase of this reference clock signal @APCCK and the position signal DPG is adjusted by the APC circuit 46. Since they are synchronized, the reproduction RAD clock signal HDCKP and the position signal DPG are phase-synchronized.

Next, in step S4, the digital audio recorder determines whether the tape 15 is a recorded tape. And if it is not a recorded tape (No)
, in step S5, the clock generation circuit 24 generates the recording head clock signal HDCKR, the gate signal RBO which opens the gate circuit 21, and the fixed clock signal KC generated from the timing control circuit 64.
A switching signal K is generated to switch the switch circuit 65 so as to introduce K to the switch circuit 25. Here, the recording clock signal HDCKR has a phase opposite to that of the reproduction clock signal HDCKP.

Therefore, the fixed output signal KCK output from the timing control circuit 64 is transmitted to the tape 15 via the head 19.
The reproduced signal RFa from the head 18 is supplied to the low-pass filter circuit 61 via the switch circuit 34. In this case, since it is a non-recorded tape, the head 18 detects the fixed clock signal KCK that is omitted from the track adjacent to the track of the tape 15 that the head 18 traces (that is, the track on which the fixed clock signal KCK is recorded by the head 19). will be played.

Here, the fixed clock signal KCK is, for example, 100
Since a low frequency of about kHz is used, each head 1
This allows the head 18 to easily reproduce the missing part of the fixed clock signal KCK recorded by the head 19 without being affected by the difference in azimuth angle of 8.19.

Therefore, the relationship between the timing at which the reproduction signal of the fixed clock signal KCK is obtained from the head 18 and the timing at which the fixed 0 clock signal KCK is recorded by the head 19 is as shown in FIG. 3(C). That is, the reproduction signal of the head 18 is generated with a delay of a time corresponding to the above θ after the position signal DPG becomes H level. Here, the above τ is τ-(392/BF) (θ/π) (However, BF is the block frequency of 9.408M) t
z/360. ) becomes.

Next, in step S6, the reproduced signal obtained from the head 18 is supplied to the low-pass filter circuit 61, and as shown in FIG.
), after the frequency component is removed, the signal is supplied to the position detection circuit 62. This position detection port 1'g62 is
As shown in FIG. 3(e), a position detection signal PK which becomes H level at the temporal center of the reproduced signal is generated.

Here, as described above, the tape 15 is wound around the drum 16 within an opening angle range of 90' from the center of the drum 16, and the heads 18 and 19 are arranged oppositely to each other with the center of the drum 16 in between. Therefore, if one period of the reproduction RAD clock signal HDCKP is 2π, the third
The reproduction time, recording time, and time between reproduction and recording shown in 1/(C) are each π/2. Therefore, the time from when the position detection signal PK becomes H level until the next recording operation by the head 19 is performed is 3π/
There will be 4.

Therefore, the position detection signal PK is transmitted to the delay circuit 63 by 3π/
By generating H level signals at the time when the reproduction signal is extended for 4M and at the first time when the reproduction signal is obtained from the head 18, the recording and reproduction data start signal RPC is generated as shown in FIG. 3(f). will be generated.

Further, as shown in FIG. 3(Q), the clock generation circuit 24 generates π from the time when the position detection signal PK becomes H level.
/2i1! At the point when
1l11! so that the phase of the reproduction RAD clock signal HDCKP is shifted so that the polarity of KP is inverted. ll
do. Then, the reproduction signal from the head 18 can be stably obtained at the center of the H level am of the reproduction head clock signal HDCKP (that is, the state in which the switch circuit 34 is switched so as to guide the reproduction signal from the head 18). At this point, the RAD clock signal HDCKP for reproduction is automatically adjusted.

After that, in step S7, it is determined whether the recording mode has been requested by an external operation, and if it has been requested (YE
S) In step S8, the digital audio tape recorder is set to recording mode, and the recording operation described above is performed. If the recording mode is not requested in step S7 (No), the playback mode is continued in step S9, and the above-described playback operation is performed.

Note that if it is determined in step S4 that the tape is a recorded tape (YES>, then in step 810 head 1 is
A recording/reproduction data start signal is generated from the reproduction signal obtained from 8.19, and the process proceeds to step S7.

Next, as shown in FIG. 5, the tape 15 is wound around the drum 16 within an opening angle range of 180° from the center of the drum 16, and the head 18 is placed on the drum with the magnetization pattern 58 facing the head 41. θ with a rotation angle of 16
The operation when the tape 15 is located in front of the position where it is contacted by the tape 15 by (0<θ × π) will be described.

In this case as well, from the clock generation circuit 24 as shown in FIG.
At the same time, the head 41 generates a position signal DPG as shown in FIG. 6(b).

Then, the head 19 records the fixed clock signal KCK, and the head 18 reproduces the missing portion.

At this time, the relationship between the timing at which the reproduction signal of the fixed clock signal KCK is obtained from the head 18 and the timing at which the fixed clock signal KCK is recorded by the head 19 is as shown in No. 61 (C). That is, the reproduction signal of the head 18 is generated with a time delay corresponding to the above-mentioned θ after the position signal DPG becomes H level.

Thereafter, the reproduced signal obtained from the head 18 is supplied to a low-pass filter circuit 61 to remove high frequency components as shown in FIG. As shown in e), the position detection signal PK which is at H level is generated in the first part of the reproduced signal.

Here, as described above, the tape 15 is wound around the drum 16 within an opening angle of 180 degrees from the center of the drum 16, and the heads 18 and 19 are arranged oppositely to each other with the center of the drum 16 in between. Therefore, if one period of the reproduction RAD clock signal HDCKP is 2π, then
The playback time and recording time shown in FIG. 6(C) are each π
It is one by one. Therefore, there is a period of n from when the position detection signal PK becomes H level until the next recording operation by the head 19 is performed.

Therefore, the leak generation circuit 24 is configured as shown in FIG.
As shown in FIG.
The phase of the reproduction RAD clock signal HDCKP is shifted 611111 so that the polarity of KP is inverted. Then, the H of Radclock signal @HDCKP for playback
During the level period (that is, the state in which the switch circuit 34 is switched so as to guide the reproduction signal of the head 18), the reproduction signal from the head 18 can be stably obtained, and the self-vJ adjustment of the rad float signal HDCKP for reproduction is now performed. It is done.

In addition, by generating an H level signal at the time when the position detection signal PK is delayed by π in the delay circuit 63 and at the first time when the reproduction signal is obtained from the head 18, it is possible to generate an H level signal, respectively, as shown in FIG. As shown in FIG. 2, a recording/reproducing data start signal RPD is generated.

Next, FIG. 7 shows another embodiment of the present invention. That is, the clock generation circuit 24 generates the head clock signal HDCK for the switch circuit 25.34, and also generates the head clock signal )-IDcK.
A delay circuit 6 controlled by a clock generation circuit 24
The reference clock signal KO of the APC circuit 46 is supplied through the APC circuit 6. In this case, the switch circuit 25.34
are controlled to switch in opposite directions depending on the polarity of the head clock signal HDCK. That is, if the switch circuit 34 is in the switching state corresponding to the head 18 as shown in the figure when the head clock signal HDGK is at H level, the switch circuit 25 is in the switching state corresponding to the head 19 as shown in the figure. It is.

Furthermore, the reproduced signal guided by the switch circuit 34 is supplied to the position detection circuit 68 via the fixed clock extraction circuit 67, and is used to generate the position detection signal PK.
The generated position detection signal PK is sent to the clock generation circuit 24.
is supplied to control the delay circuit 66.

Furthermore, the clock generation circuit 24 generates the fixed clock signal KCK. The fixed clock signal KCK and the digitized data DATAR supplied to the input terminal 69 are selectively guided to the switch circuit 25 via the switch circuit 65.

The operation of the above configuration will be described below with reference to the flowchart shown in FIG. 8 and the timing chart shown in FIG. 9. However, in this case, as previously shown in FIG. 4, the tape 15 is wrapped around the corners and each head 18.
19. Magnetization pattern 58. A case where the positional relationship of the heads 41 is set will be explained.

First, when started (step 511), step 31
At step 2, the clock generation circuit 24 generates a head clock signal HDCK as shown in FIG. 9(a). Next, in step S13, the digital audio chip recorder performs the above-described drum servo and capstan servo, causing the drum 160 to rotate and the tape 15 to run. Thereafter, in step S14, the digital audio tape recorder is forced into playback mode. At this time, the clock generation circuit 24 is connected to the gate circuit 2.
6. Gate signals RAO and RBO that close both 27
occurs.

The frequency of this head clock @HDCK is 100/3 Hz, which is the same as the rotational speed of the drum, and its H level period and L level period are made equal. In addition, this head clocking @HDCK occurs when the device signal DPG constituted by the head 41 is at H level (that is, when the magnetization pattern 58 is closest to the head 41), as shown in FIG. 9(b). It is formed to have a rising edge.

That is, the head clock signal HDCK is the reference clock signal APCCK output from the clock generation circuit 24.
It is generated in synchronization with this reference clock signal! A
Since PCCK and the position signal DPG are phase-synchronized by the A P'C circuit 46, the head clock signal HD
GK and position signal DPG are phase synchronized.

Next, in step 315, when the digital audio tape recorder confirms that the tape 15 is not a recorded tape, in step 516, the clock generation circuit 24 generates a gate signal RBO and a fixed clock signal that closes the gate circuit 27. A switching signal K is generated to switch the switch circuit 65 so as to guide KCK to the switch circuit 25.

Therefore, the fixed clock signal KCK is recorded on the tape 15 via the head 19, and the reproduction signal RF of the head 18 is
a is now supplied to the fixed clock widening circuit 67 via the switch circuit 34. In this case, as described above, since it is a non-recording tape, the head 18 will reproduce the missing part of the fixed clock signal KCK recorded by the head 19.

Therefore, the relationship between the timing at which the reproduction signal of the fixed clock signal KCK is obtained from the head 18 and the timing at which the fixed clock signal KCK is recorded by the head 19 is as shown in FIG. 9(C). That is, the reproduction signal of the head 18 is generated with a delay of a time corresponding to θ after the position signal DPG becomes H level.

Next, in step 817, the reproduced signal obtained from the head 18 is supplied to the fixed clock post-pickup circuit 67, and the ninth
As shown in Figure (d), after the high frequency components are removed,
The signal is supplied to the position detection circuit 68. This position detection circuit 68
As shown in FIG. 9(e), the position detection signal PK is generated to be at H level at the central portion of the reproduced signal.

Here, the clock generation circuit 24 first generates the position signal DPG.
The time (τ+τO) from when the position detection signal PK becomes H level until the position detection signal PK becomes H level is measured. In this case, the time τO from when the reproduction signal shown in FIG. 9(d) is generated until the position detection signal DPG becomes H level is:
Since it is determined in advance by calculation (96/BF), the above-mentioned τ is calculated from this.

Here, the above-mentioned time τ indicates the time from when the position signal DPG becomes H level until the reproduction signal is obtained from the head 18. What value should this time τ be for the reproduction signal? The entire head blackout signal HDCK
The theoretical value ζ1 for stable generation during the H level period of can also be determined in advance.

For this reason, in step 818, the overclock generation circuit 24 controls the delay circuit 66 in accordance with the difference between τ1 and τ. Then, the reference clock signal KC obtained by delaying the head clock signal HDOK as shown in FIG. 9(f) can be obtained from the delay circuit 66. This reference clock signal KC is the reference clock signal APC.
It is now supplied to the APC circuit '46 instead of CK.

Therefore, the rotational speed of the drum 16 is controlled based on the above-mentioned reference clock signal @KC, and the timing when the reproduction signal of the fixed clock signal @KCK is obtained from the RAD 18 and the head 19 is controlled. The relationship with the timing at which the fixed zero check signal KCK is recorded is shown in Figure 9 (1).
It becomes as shown in .

Therefore, the reproduced signal from the head 18 can be stably obtained in the center of the H level period of the head clock signal HDOK (that is, the state in which the switch circuit 34 is switched so as to guide the reproduced signal from the head 18).

After that, in step S19, it is determined whether the recording mode has been requested by an external operation, and if it has been requested (Y
ES), the digital audio tape recorder is set to the recording mode in step S20, and the recording operation described above is performed below. Further, if the recording mode is not requested in step S19 (No), the reproduction mode is continued in step 321, and the aforementioned reproduction operation is performed.

Next, as shown in FIG. 5, the case where the winding of the tape 15 is set at a corner and each head 18, 19, 1ii pattern 58° positional relationship of the head 41 will be described. In this case as well, the first
The head clock signal HDCK shown in FIG. 10(a) is generated, and the position signal DPG shown in FIG. 10(b) is also generated from the head 41.

Then, the head 19 records the fixed 0-check signal KCK, and the head 18 reproduces the leaked signal.

At this time, the relationship between the timing at which the reproduction signal of the fixed clock signal KCK is obtained from the head 18 and the timing at which the fixed clock signal KCK is recorded by the head 19 is as shown in FIG. 10(C). That is, the reproduction signal of the head 18 is generated with a delay of time τ corresponding to the above θ after the position signal DPG becomes H level.

Thereafter, the reproduced signal obtained from the head 18 is supplied to a fixed clock extracting circuit 67 to remove high frequency components as shown in FIG. 10(d), and then supplied to a position detection circuit 68, as shown in FIG. As shown in (e), the position detection signal @PK which becomes H level in the first part of the reproduced signal is generated.

Here, the clock generation circuit 24 generates a position detection signal PIH.
After reaching the level, the head clock signal @HDCK becomes L.
Measure the time until the level is reversed. Since this time originally corresponds to π, the delay circuit 66 is controlled according to the difference between π and the measured time. Then, the reference clock signal @KC obtained by delaying the head clock signal 1-ID CK as shown in FIG. 10(f) can be obtained from the delay circuit 66. Then, this reference clock signal KC is supplied to the APC circuit 46 instead of the reference clock signal APCCK.

For this reason, the rotation speed of the drum 16 is changed to ill 10 based on the reference clock signal KC, and the timing at which the reproduced signal of the fixed clock signal KCK is obtained from the head 18 and the fixed zero clock signal K
The relationship with the timing at which CK is recorded is shown in Figure 10 (Q
). Therefore, the head clock signal H
A reproduced signal from the head 18 can be stably obtained during the H level period of DCK.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] According to the present invention, as detailed above, it is possible to automatically adjust the head switching signal and the generation timing of the reproduction signal obtained from each head, and the DI! 11. It is possible to provide an extremely good head switching signal generating circuit for a helical scan type tape reproducing device that can facilitate the operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the head switching signal generation circuit of a helical scan type tape playback device according to the present invention, and FIGS. 2 and 3 are flowcharts for explaining the operation of the embodiment, respectively. and timing diagrams,
4 and 5 are configuration diagrams showing the positional relationship of the drum, tape, and head, respectively; FIG. 6 is a timing diagram for explaining the operation in the state shown in FIG. 5; and FIG. 7 is a diagram of the present invention. Block configuration diagrams showing other embodiments, FIGS. 8 to 10
11 is a block diagram showing a head switching signal generation circuit of a conventional helical scan type tape playback device, and FIGS. The figures are diagrams for explaining the format of data recorded on each track, Figure 15 is a diagram showing details of ATF data, and Figure 16 is a diagram for explaining the format of data recorded on one track, and Figure 16 is a diagram showing the details of ATF data. Timing diagram showing the relationship, No. 17
The figure is a configuration diagram showing a position signal generating means. 11, 12... Reel stand, 13.14... Reel motor, 15... Tape, 16... Drum, 17...
・Capstan, 18°19...Head, 20...
Drum motor, 21... Capstan motor, 22...
...Input terminal, 23...Addition circuit, 24...Clock generation circuit, 25...Switch circuit, 26.27...
・Gate circuit, 28... System clock signal input terminal, 29... Recording/reproduction mode input terminal, 30.31.
...Amplifier, 32, 33...Equalizer circuit, 34.
...Switch circuit, 35...Data slice circuit, 3
6... Position signal detection 1 device NID circuit, 37... Output terminal, 38... PLL circuit, 39... Output terminal,
40.41...Head, 42...Amplifier, 43...
・AFC circuit, 44...Addition circuit, 45...Amplifier, 46...APC circuit, 47...Equalizer circuit,
48... Drive circuit, 49... Head, 50... Amplifier, 51... Capstan servo circuit, 52...
Recording/reproducing mode input terminal, 53... Equalizer circuit,
54... Drive circuit, 55... ATF circuit, 5[i,
57... Drive circuit, 58... Magnetization pattern, 59
...Rotating body, 60...Connection terminal, 61...Low pass filter circuit, 62...Position detection circuit, 63...
Delay circuit, 64... Timing control circuit, 65...
Switch circuit, 66... Delay circuit, 67... Fixed clock extraction circuit, 68... Position detection circuit, 69.
...Input terminal. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 4 (d) -e1 volume■Plate',
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Claims (1)

[Claims] a drum having first and second heads disposed along its circumferential side and driven to rotate; a tape that is in contact with the circumferential side of the drum and with which the first and second heads are alternately contacted; and switching means for selectively guiding each reproduction signal obtained from the second head to a signal processing system for reproduction, wherein the first and second heads alternately contact the tape in response to a head switching signal. In the helical scan type tape playback device, the switching operation of the switching means is controlled in accordance with the timing when the switching means is switched, and the first head records a reference signal for generating a head switching signal on the tape, and the second head records a reference signal for generating a head switching signal on the tape. recording and reproducing means for reproducing the reference signal leaking from the track corresponding to the first head; and recording and reproducing means for reproducing the reference signal leaking from the track corresponding to the first head; The apparatus is characterized by comprising a control means for determining a difference between the generation timing of the reproduction signal obtained from the second head and adjusting the head switching signal and the generation timing of the reproduction signal obtained from the second head. A head switching signal generation circuit for a helical scan tape playback device.