JPS63185319U - - Google Patents
Info
- Publication number
- JPS63185319U JPS63185319U JP7589687U JP7589687U JPS63185319U JP S63185319 U JPS63185319 U JP S63185319U JP 7589687 U JP7589687 U JP 7589687U JP 7589687 U JP7589687 U JP 7589687U JP S63185319 U JPS63185319 U JP S63185319U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- pulse width
- data latch
- gate circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
- Selective Calling Equipment (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7589687U JPS63185319U (pt) | 1987-05-20 | 1987-05-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7589687U JPS63185319U (pt) | 1987-05-20 | 1987-05-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63185319U true JPS63185319U (pt) | 1988-11-29 |
Family
ID=30922466
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7589687U Pending JPS63185319U (pt) | 1987-05-20 | 1987-05-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63185319U (pt) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0746125A (ja) * | 1993-07-28 | 1995-02-14 | Nec Corp | Pll回路 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58100533A (ja) * | 1981-12-10 | 1983-06-15 | Fujitsu Ltd | チヤタリング防止回路 |
-
1987
- 1987-05-20 JP JP7589687U patent/JPS63185319U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58100533A (ja) * | 1981-12-10 | 1983-06-15 | Fujitsu Ltd | チヤタリング防止回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0746125A (ja) * | 1993-07-28 | 1995-02-14 | Nec Corp | Pll回路 |
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