JPS63185161A - Memory controller - Google Patents

Abstract

PURPOSE:To reduce an overhead at the time of extending a memory space by providing a net counter for counting the generations and the cancellations of a supervisor state and generating the switching timing of a register and a memory address extending register at the time of the multiple generation of the supervisor state. CONSTITUTION:A multiplexer 4 selects the outputs of both the registers 1, 2 according to the output of the nest counter 3. The nest counter 3 and an up down counter are provided and at the time of a system generation, a '0' is cleared. Then, when a system enters the supervisor state (state controlled by OS) according to a interrupting processing during a task operation or the generation of a system macro or the like, a supervise start signal SST from a software is received to count up and a supervise (end signal SEN is received issued from the software according to the end of the supervisor state to count down. This nest counter 3 operates so as to select the output of the register 3 by the multiplexer 4 when it is in a supervisor state.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory management device for expanding memory space.
In particular, 8-bit CPUs used in small facsimile machines, etc.
The present invention relates to a memory management device.

[Conventional technology]

In order to make devices such as facsimile machines multi-functional, a program memory is required. A method of configuring this memory with a RAM and loading program data to be used from an external magnetic storage device or the like into the RAM as needed is expensive. For example, Japanese Patent Application Laid-Open No. 61-58372 describes a technique for making the facsimile machine multi-functional by connecting a data processing device to the outside of the facsimile machine and inputting data required by the facsimile machine from the data processing device. ing.

[Problem that the invention seeks to solve]

As mentioned above, since the conventional technology is expensive, it becomes necessary to expand and utilize memory space, especially in 8-bit CPUs used in small devices.

An 8-bit CPU has only 64 bytes of memory space,
This is the supervisor area and task area.

It is divided into RAM areas and used. For facsimile machines, etc., the RAM area contains image line memory, coding buffer, communication result buffer, and system station data, so together with the program work area, the RAM area is 1
About 6 bytes are required.

In addition, although the supervisor area is small in O5 itself, in order to speed up interrupt processing, a large number of small programs are used depending on the situation, and together with periodic processing, 3
I use about 2 part-time jobs. Therefore, currently there is only 1 remaining
6 bytes are multiplexed and assigned to the task system. However, in the future, in order to introduce the CCITY half-duplex retransmission method and to realize various communication modes (Gl to G3) with the same model, it will be necessary to expand the RAM area and supervisor area. Therefore, in the future, the allocated area for tasks will decrease, and a situation will arise where a program will no longer be able to be stored. Therefore, the memory space is expanded by arranging the supervisor area and the task area at the same address and using the real area while switching.

The above true area switching is performed by rewriting the memory address extension register (hereinafter referred to as the plane cutting register) using software, reading and saving the old task plane,
If the number of nests in the supervisor state is counted by software, in facsimile machines, etc., where several interrupts of 1 m5 ec or less to 2 m5 ec occur, the overhead will increase, the processing capacity will decrease, and there is a possibility that the machine will become inoperable. .

An object of the present invention is to provide a memory management device that reduces overhead when expanding memory space.

[Means for solving problems]

The above purpose is to specify one fixed plane among the multiplexed addresses in the supervisor state in an 8-bit CPU system that uses memory space multiplexing and is equipped with a memory address extension register that places different programs at the same address in the memory space. This is achieved by providing a register for controlling the supervisor state and a nest counter for counting occurrences and cancellations of the supervisor state and generating a switching timing signal between the register and the memory address extension register when multiple supervisor states occur.

[Effect]

The count value of the nest counter determines when the supervisor state is entered and when it ends, and the task area and supervisor area of the multiplexed memory space are switched based on the count value, thereby reducing overhead.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

The figure is a block diagram of a memory management device according to an embodiment of the present invention. In figure 0, 1 is a task face-off register;
During system generation, a value that specifies the task memory containing the initial task is written by the program. 2 is a supervisor designation register, into which a value designating the supervisor memory is written by a program during system generation. The outputs of these registers 1.2 are selected by a multiplexer 4, the selected signals are decoded by a decoder 5, and the memories 6.7. . . . becomes a selection signal for n. In this embodiment, the memory 6 is a shared memory for supervisor programs and tasks, and the memories 7, . . . , n are dedicated memories for tasks, and are arranged on the same address plane. Note that the RAM area is not shown.

The multiplexer 4 selects the outputs of both registers 1 and 2 based on the output of the nest counter 3. It consists of a nest counter 3 and an up/down counter, and is cleared to "0" during system generation. Then, when the system enters the supervisor state (state managed by O3) due to interrupt processing or system macros occurring during task operation, the system receives a supervisor start signal SST from the software, counts up, and enters the supervisor state. It counts down upon receiving the supervision end signal SEN issued from the software upon completion of the state. This nest counter 3 operates so that the multiplexer 4 selects the output of the register 2 when in the supervisor state.

With this configuration, when interrupt processing A enters during task operation, the nest counter 3 counts up and its contents become "
1". As a result, multiplexer 4 selects the output signal of register 2, and decoder 5 selects the output signal of register 2, and decoder 5 selects the output signal of register 2.
The task shared memory 6 is selected and interrupt processing A is executed. At this time, when interrupt processing B is further entered, the nest counter 3 counts up and its content becomes "2", and interrupt processing B using memo +J6 is executed. After interrupt processing B is completed, the software sends the supervisor end signal SEN.
is issued, the content of the nest counter 3 becomes "1".

As a result, interrupt processing A is executed, and when interrupt processing A is completed, the content of nest counter 3 becomes "0" in response to supervisor's end signal SEH. When the content of the nest counter 3 becomes "0", the multiplexer 4 returns the selection to the task face selection register 1 and returns to the original task operation.

In this way, according to this embodiment, a system can be realized in which the supervisor state and task state can be processed in the same address space by adding software processing of several microseconds.

〔Effect of the invention〕

According to the present invention, since the memories for the supervisor program and the task program can be located at the same address, multi-functionality can be realized even in a system with a small memory space such as an 8-bit CPU. Furthermore, by controlling only the face cutting register,
Compared to the case of memory switching, there is no need to read, save and restore the face-cut register and the associated staff operations, so the complexity of the program can be eliminated.
In devices such as facsimiles that require real-time processing, the overhead associated with memory control can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a memory management device according to an embodiment of the present invention. 1... Task cutting register, 2... Supervisor specification register, 3... Nest counter, 4... Multiplexer, 5... Decoder, 6... Shared memory,
7~n...Task memory.

Claims (1)

[Claims] 1. In an 8-bit CPU system that is equipped with a memory address extension register that places different programs at the same address in the memory space and that uses multiplexed memory spaces, it specifies one fixed plane among the multiplexed addresses when in the supervisor state. A memory management device comprising: a register; and a nest counter that counts occurrences and cancellations of supervisor states and generates a switching timing signal between the register and the memory address extension register when supervisor states occur multiple times. Device.