JPS6318391B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a television receiver that projects images of two channels simultaneously on one cathode ray tube screen. In a television receiver that simultaneously displays television signals of two different channels on one cathode ray tube screen, two tuners are used, one tuner transmits the first television signal, and the other tuner transmits the second television signal. For each television signal, the image of the other television signal is compressed into a part of the image based on the other television signal and inserted as a sub-screen so that they can be displayed at the same time. If either or both of the second television signals has a significantly weak electric field (including empty channels), the other or both images will be extremely unsightly. In particular, if the image that becomes the child screen is disturbed, there is a problem in that it greatly affects the image on the main screen, making it difficult to see the main screen. In view of the above-mentioned problems, the present invention attempts to always obtain a high-quality image by switching the channel of the sub-screen when the received electric field strength of the television signal forming the sub-screen is weak. In order to achieve the above object, the present invention provides a detection circuit for detecting the received electric field strength of the television signal that creates the sub-screen, and provides a detection circuit that detects the received field strength of the television signal that creates the sub-screen. When the received electric field strength of the television signal is weak, the detection output of the detection circuit operates a channel selection circuit that selects the television signal of the sub-screen, and a television signal with a strong electric field is obtained from the channel of the sub-screen. It is designed so that the channel can be switched. Further, the present invention is characterized in that at this time, the detection output of the detection circuit is supplied to either the channel up terminal or the channel down terminal of the channel selection circuit to perform channel switching. Therefore, according to the present invention, when the received electric field strength of the television signal on the sub-screen becomes weak, it is detected and the channel is automatically switched, so that it is possible to obtain a high-quality image that is easy to view. . An embodiment of the present invention will be described below with reference to the drawings. As a method of projecting images of two channels A and B on the same projection surface, the method shown in FIG. 2 can be considered. In other words, the B channel is approximately 1/1 vertically of the entire screen.
2. The width is 1/2 and the area is 1/4 and is projected in the lower right corner of the screen. The basic idea of this method is that every other horizontal scan of the B channel, samples are stored in the memory circuit corresponding to that scanning line every other picture element (sample points necessary to reproduce an image) during one horizontal scan. The horizontal scan of channel A is stored as B in Figure 2.
When sweeping a portion, the image signal of the B channel is displayed in the portion B of Fig. 2 as an image compressed to approximately 1/2 in length and width by reading out the contents of the memory circuit at twice the writing speed. It is based on the principle of releasing. Fig. 1 shows the specific configuration, in which 1 is an antenna, 2 and 6 are tuners that receive broadcasts on different channels A and B, respectively, 3 and 7 are video intermediate frequency amplification circuits, and 4 and 8 are video Detection circuit, 5,
9 is a video amplifier circuit; 10 is a synchronization signal generation circuit that generates the vertical synchronization signal V _B and horizontal synchronization signal H _B of channel B; and 11 is a synchronization circuit that generates the vertical synchronization signal V _A and horizontal synchronization signal H _A of channel A. This is a signal generation circuit. 12 is a flip-flop that inverts its state every time the horizontal synchronization signal H _B is generated and generates an output signal d; 13 is a signal to be added.
A signal selection circuit that selects one of the inputs p, q, r, and s according to N ₁ , N ₂ , N ₃ , and C and generates an output at the output terminal 23 operates as shown in FIG. . Note that the mark in the middle of the figure may be optional. 14 and 17 are RS flip-flops each having a reset terminal and a set terminal, and outputs a,
generate b. 15 and 16 are counters, and 18 is a gated oscillator that stops oscillation while the horizontal synchronizing signal H _A is being generated, and makes the phase relationship of its output pulses with respect to the horizontal synchronizing signal H _A the same in any horizontal scan. be able to. A gated oscillator 19 generates an output and has a similar relationship to the horizontal synchronizing signal H _B. 20 is a control circuit including a memory circuit for writing and reading image information;
The circuits shown in FIGS. 5, 7, 8, and 9 are included. 21 and 22 are AND gates. Detection circuits 24 and 25 detect the electric field levels of both signals from the output signals of the video amplification circuits 5 and 9. The output voltages of the detection circuits 24 and 25 are supplied to the channel selection circuits 26 and 27, respectively, and when the electric field level of the output of the video amplification circuits 5 and 9 is weak, the channels of the respective channel selection circuits 26 and 27 are changed by one station. Connected to make it work. Tuning circuit 26, 2
7 supplies tuners 2 and 6 with voltage for tuning. Detection circuits 24, 25, tuning circuits 26, 27
is the detection circuit 24 for switching channel A.
The channel selection circuit 26 is not necessarily required. The oscillation frequency of the gated oscillator 18 described above is 450 _H [Hz] when the number of picture elements per horizontal scan is 450, and the horizontal scanning frequency is _H.
The oscillation frequency of gated oscillator 19 is 1/2 of that.
It is 225 _H [Hz]. The counter 15 is a counter of 525/2×2=132 [bits] for the number of horizontal scans of one field, 525/2, and 132 horizontal synchronizing signals H _A
is counted, the flip-flop 14 is set and the output a goes to a high potential state. Counter 15 and flip-flop 14 receive vertical synchronization signal V _A
It is reset by . The counter 16 is a counter of 450/2=225 [bits] for 450 picture elements during one horizontal scan, and when it counts 225 output pulses of the gated oscillator 18, it sets the flip-flop 17. , its output b is in a high potential state. Counter 16 and flip-flop 17 are reset by horizontal synchronization signal _HA . With this configuration, when sweeping the portion B shown in FIG. 2, the outputs a and b are in a high potential state, and the output of the oscillator 18 appears at the output e of the AND gate 22. Next, the operation of the embodiment configured as above will be explained. The broadcast signal of channel A selected for reception by tuner 2 is transmitted to the fourth channel via circuits 3, 4, and 5.
The signal is applied to the signal selection circuit 13 as a video signal P shown in FIG. Also, the broadcast signal of channel B selected for reception by tuner 6 is applied to control circuit 20 via circuits 7, 8, and 9. This control circuit 20 samples the video signal V of channel B as shown in FIG. 4B, stores each sample value, and reads out the stored signal at twice the sampling speed. Then the fourth
As shown in Figure C, a video signal whose time axis is compressed to 1/2 is obtained. This video signal appears as q, r, and s for each field. Signal selection circuit 1
In step 3, the signals p, q, r, and s are selected and switched appropriately, and the video signal of channel A and the video signal of channel B are combined as shown in FIG. It appears on 23. Next, the circuits included in the control circuit 20 will be explained. FIG. 7 shows a ring counter, and if the vertical synchronization signal V _B triggers these flip-flops FF1 to FF3 several times from any state of each flip-flop FF1, FF2, FF3,
The outputs M ₁ , M ₂ , and M ₃ repeat the state shown in FIG. 11 every time the synchronizing signal V _B arrives. These outputs M ₁ , M ₂ , and M ₃ are used as signals for selecting the write circuit. FIG. 8 shows a circuit that obtains signals N ₁ , N ₂ , _{N 3} from the signals M ₁ , M ₂ , M ₃ obtained by the circuit shown in FIG. It is configured with FF4 to FF6 as the main circuit. N ₁ , N ₂ , N ₃ are signals for selecting the readout circuit and signals p,
It is used as a signal to select any one of q, r, and s. Further, FIG. 9 shows that either the output e of the oscillator 18 or the output of the oscillator 19 is selected via the AND gate 22 by the signals M ₁ , M ₂ , M ₃ , N ₁ , N ₂ , and N ₃ . Therefore, it is a circuit for obtaining a write clock or a read clock for each write/read circuit. FIG. 5 shows an embodiment of a memory circuit included in the control circuit 20 and a circuit for writing and reading image information therein. 206 is a memory circuit, 205 is a shift circuit;
It is a register. 502 and 503 are circuits having the same configuration as 501, and M ₁ ,
For N ₁ and U ₁ , circuits 502 and 503 become M ₂ , N ₂ , M ₃ , N ₃ and U ₃ respectively. When (M ₁ , M ₂ , M ₃ ) = (1, 0, 0), the circuit 501, when (M ₁ , M ₂ , M ₃ ) = (0, 1, 0), the circuit 502, (M ₁ , M ₂ , M ₃ )=(0,
0, 1), writing is performed in the circuit 503, respectively. Also, (N ₁ , N ₂ , N ₃ )=(1,0,
0), the circuit 501 calculates (N ₁ , N ₂ , N ₃ )=
(0, 1, ₀ ), the circuit 502
When N ₂ , N ₃ )=(0, 0, 1), circuit 503 is read. As can be seen from Figure 8, Mi≠
It is Ni. The write and read operations of the circuit 501 will be described. When M ₁ =1, AND gates 201 and 203 are open, and AND gates 202 and 203 are open.
204 is closed. Therefore, in shift register 205, the flip-flop at the first stage is set and the other flip-flops are reset by the synchronizing signal _VB . In other words, the state becomes 10...0. Due to the signal d, this state becomes 010...0,
0010...Changes to 0. U ₁ is equal to the output of oscillator 19, which creates the write clocks φ ₁ and φ ₂ to storage circuit 206. Since d shifts the shift register 205 every other horizontal scan of the synchronization signal H _B , information for every other horizontal scan is stored in each storage circuit. V is a video signal. When N ₁ =, AND gates 201, 203
is closed, and AND gates 202 and 204 are open. At this time, the shift register 205 is set to the state of 100...0 by V _A , and by H _A
The state changes from 0100...0 to 0010...0.
U ₁ is equal to the output e of the AND gate 22, which corresponds to the read clocks φ ₁ and φ ₂ from the storage circuit 202.
Create. The read speed is equal to the oscillation frequency of the oscillator 18. FIG. 3 shows the relationship between the vertical synchronizing signal of the A channel, the vertical synchronizing signal of the B channel, and the writing and reading of image information of the B channel. In other words, the part with the number B ₁ is connected to the circuit 501, and the part with the number B ₁ is connected to the circuit 501.
That of B 3 goes to circuit 502, and that of B ₃ goes to circuit 503.
, and it will be read in the corresponding numbered part of the A channel. The dotted line in the figure means that on the right side, the horizontal sweep is performed in the part B of FIG. 2. FIG. 6 shows an embodiment of the memory circuit. The shift signals φ ₁ and φ ₂ are composed of rectangular waves having mutually opposite phases. The voltages on the capacitors are V ₁ , V ₂ , and V ₃ . The sample value of the signal is Uk. When the base of the transistor reaches the voltage U, the transistor starts conducting, and current flows from the capacitance immediately following it until the capacitance of the previous stage reaches U. The voltage of its own stage momentarily becomes 2U, and charge transfer takes place until its voltage becomes U+Uk. Therefore, the information contained in this stage is transmitted to the next stage. Note that G is a gate signal. In the above embodiment, a case has been described in which another channel is displayed in the lower right corner of the screen of the television receiver at a size of 1/2 in the vertical and horizontal directions.
Its size can be changed in various ways by changing the count value of , and by replacing the flip-flop 12 with a counter having an appropriate count value. The position to be displayed is not limited to the lower right corner, but may also be the upper right corner, the upper left corner, or the lower left corner. In the above embodiment, while the broadcast signal of channel A is received by the tuner 2 and displayed, the broadcast signal of channel B is received by the tuner 6, and this channel B image is used as a sub-screen to display a part of the channel A image. Although we have described the case where the screen is inserted into the channel A and projected, it would be very convenient if the projection position of the screen of the same channel B could be changed using the above configuration. That is, if the signals of the two channels are exchanged by a switch or the like before the circuits 10 and 11 that separate the horizontal synchronization signal and vertical synchronization signal of each channel, the switch will exchange the output of the amplifier circuit 5 and the output of the amplifier circuit 9. By doing so, the screen of the channel that was previously displayed in a small size can be immediately enlarged and viewed, which is very practical. FIG. 12 shows a specific circuit example of the detection circuits 24 and 25. Obtain the input video signal from A, and connect it to the resistor R ₁ ,
Through an emitter follower consisting of a transistor Q ₁ and a resistor R ₂ , a capacitor C ₁ , a diode D ₁ and a resistor are connected.
When clamped with a clamp circuit consisting of _R3 , the cathode side of diode _D1 becomes high level when there is an input signal. Connect this to transistor Q ₂ ,
Invert and amplify with resistor R ₄ , transistor Q ₃ , resistor R ₆ ,
Through a peak hold circuit consisting of a diode D ₂ , a capacitor C ₂ , and a resistor R ₇ , the anode side of the diode D ₂ becomes a low level in a strong electric field and a high level in a weak electric field _.
It passes through an emitter follower consisting of a resistor _R8 , passes through a resistor _R9 , is inverted by a resistor _R10 and a transistor _Q5 , and is supplied as an output from a terminal B. With this configuration, a low level signal can be obtained as an output at terminal B during a weak electric field. FIG. 13 shows specific circuit examples of the channel selection circuit 26 and tuner 2, and the channel selection circuit 27 and tuner 6. In this circuit, the tuning voltage applied to the tuner using a variable capacitance diode as a tuning element is set in advance using multiple variable resistors, and channels are switched by switching and operating the variable resistors. A channel selection device designed to perform the following is used. Using a variable capacitance diode as a tuning element in a tuner,
Many devices are used that switch the channel selection voltage applied. FIG. 13 shows the main parts of such a tuner, where 28 is a VHF tuner and 29 is a UHF tuner. A switching diode 33 is provided for band switching between the VHF high band and the VHF low band. 34 is a terminal to which power supply BV for operating the VHF tuner 28 is applied; 35
36 is a terminal to which a tuning voltage BT for channel switching is applied, 36 is a terminal to which a band switching voltage BS is applied, and 37 is an IF output terminal. The UHF tuner 29 also includes a variable capacitance diode 38 and a resonant line 39 as a tuning element. 40 is a power supply for operating UHF tuner 29
BU is applied to the terminal, 41 is the terminal to which the tuning voltage BT common to VHF tuner 1 is applied, 42 is the terminal to which the tuning voltage BT common to VHF tuner 1 is applied.
This is an IF output terminal. In addition, only a part of the tuning circuit is shown in the figure, and all other circuit parts are omitted. Next, an example of the basic configuration of a device that applies a channel selection voltage to such a tuner to perform channel switching and band switching will be described with reference to FIG. 14. Here, 43 is a tuning voltage setting circuit that presets the tuning voltage BT to be applied to the variable capacitance diode of the tuner, and is provided with a plurality of variable resistors 44a to 44l, each of which is used to set the tuning voltage BT to be applied to the variable capacitance diode of the tuner. Settings are made so that a tuning voltage BT can be obtained, and a selected one is taken out to a terminal 46 via diodes 45a to 45l, and the impedance is converted by a transistor or the like (not shown) to the VHF tuner. 28 and UHF
Each variable capacitance diode 30, 38 of tuner 29
added to. 47 is a channel switching circuit for switching which of the variable resistors 44a to 44l is to be operated; here, a binary counter 48 and a decoder 49 are used. That is, a pulse generating circuit 50, a binary counter 48 that counts the pulses, a binary-hexadecimal decoder 49 that selectively generates an output according to its binary output, and the counter 48 and the pulse generator. The control circuit 51 includes a control circuit 51 that controls the operation of the circuit 50. Decoder 4
9 is equipped with an output switching transistor for each of the 16 output terminals a to p, and the counter 48
According to the binary output output from the transistor, only one of these transistors is selectively turned on, and a low level output is generated at one of the output terminals a to p. 12 of them
A variable resistor 44 connected to the output terminals a to l
Among the transistors a to 44l, a current is caused to flow through only those connected to the output terminals of the transistors which have become conductive. At the time of channel switching, one of the plurality of normally open switches 53a to 53l provided on the switch board 52, for example, the switch 53c, is closed. At that time, if the channel at the position of the switch 53c is not selected, the output of the output terminal c of the decoder 49 to which this switch 53c is connected is at a high level, so the output is sent to the control circuit via the switch 53c. 51 input terminals CH
The output from the output terminal OC causes the pulse generating circuit 50 to start generating pulses, and the generated clock pulse CL is applied to the counter 48 via the terminal UCL. This causes the counter 48 to start counting, and the transistors in the decoder 49 that are rendered conductive change accordingly.
Output terminal c to which switch 53c is connected
When the transistor becomes conductive, the input to the input terminal CH of the control circuit 51 becomes low level, so the operation of the pulse generating circuit 50 is stopped, and the selected state is maintained until the switch of another channel is operated. The channel will be selected. If the frequency of the clock pulse generated by the pulse generating circuit 50 is set sufficiently high, for example, about 2 KHz or more, the above-mentioned channel switching can be completed within a very short time while the switch is closed. 54U and 54D are switches that are opened and closed by operation signals such as ultrasonic waves or light when sequentially selecting channels by remote control or manual operation. When the switch 54U is operated, a counter 48 is sent from the control circuit 51.
A count up signal is applied to the counter 48 to select the channel one above, and when the switch 54D is operated, a count down signal is applied from the control circuit 51 to the counter 48 to select the channel one below. In the present invention, the outputs of the detection circuits 24 and 25 shown in FIG.
The switches 54U and 54D shown in the figure are connected in parallel to the control circuit 51 side terminal, and when the electric field strength becomes weak, a low level signal is applied to the control circuit 51 in the same way as when the switches 54U and 54D are closed. This is to select one channel upward or downward. Therefore, the cathode ray tube screen is the
The channel selection operation is stopped when the first television signal, the second television signal, or both are switched and a strong electric field television signal is obtained.
A high-quality image with a strong electric field is projected on the cathode ray tube screen. Especially if the second television signal (image of channel B) is disturbed and becomes noisy,
First television signal (image of channel A)
It also becomes unsightly. Therefore, as described above, by detecting the electric field strength of the channel B signal and driving the channel selection circuit 27 to switch channels when the electric field is weak, the image of channel B, that is, the sub-screen as well as the channel The image A, that is, the main screen, is also extremely easy to see. Moreover, it is only necessary to newly provide the detection circuits 24 and 25 for detecting the strength of the electric field strength in the circuit configuration, and the UP terminal of the control circuit 51 in the channel selection circuits 26 and 27,
Another advantage is that the configuration is simple because the DOWN terminal can be used. Next, 55 is a band switching circuit that switches the tuner band in accordance with the channel switching as described above, and includes band setting switches 56a to 56l provided for each channel. and a switching circuit 57 for switching. Switches 56a-5
6l are contacts L and VHF for VHF low band, respectively.
It has contacts for each of three bands, contact H for high band and contact U for UHF band, and a common contact,
The common contacts are each connected to the output end of the channel switching circuit 47 via a resistor. 58V
58U is a terminal that supplies operating power BV to VHF tuner 28, 58U is a terminal that similarly supplies operating power BU to UHF tuner 2, and 58S is a coil switching power supply BS for band switching in VHF tuner 1. This is the terminal for supplying. When a switch set to the VHF low band, for example channel 56a, is selected,
When the state is "A" in the table below, the VHF low band is selected. Further, when a switch to which the VHF high band is set is selected, for example, channel 56d, the state becomes B and the VHF high band is selected. Furthermore, when the UHF band is set, for example, when the 56h channel is selected, the switch changes to the state of "Ha" and the UHF band is set.
A band is selected. In this way, band switching is performed.

[Table] Further, 59 is a channel display circuit, and display lamps 60a to 60l connected to respective output terminals a to l of the channel switching circuit 47 display the channel being selected. Furthermore, 61 is a day feed circuit which stops the display of the channel display circuit 59 during this switching period by a day feed signal outputted from the output terminal DEF of the control circuit 51 during channel switching,
And for tuner by output from output terminal 62
This is to stop the operation of the AFC circuit. As is clear from the embodiments described above, the television receiver according to the present invention synchronizes the second television signal that creates the sub-screen with its synchronization signal, thins out the scanning lines and pixels, and writes the second television signal into the storage means. This signal is read out in synchronization with the synchronization signal of the first television signal, and a second television signal whose time axis is compressed is read out.
A second television signal with a compressed time axis is inserted into the first television signal that creates the main screen by deleting a part of it, and this composite signal is displayed. It is something. Therefore, you can also watch other programs on the same screen. Furthermore, it can be used as a monitor in a video tape recorder. The electric field strength of at least the second television signal is detected, and when the electric field strength is weak, the detection output drives a channel selection circuit to automatically switch the second television signal to the next channel. As a result, not only the image of the second television signal but also the first television signal can be easily viewed, and an image of good quality can always be obtained. In this case, the detection output of the means for detecting the strength of the electric field strength is applied to the channel up terminal or channel down terminal of the control circuit that constitutes the tuning circuit, and the channel switching is performed by utilizing the configuration of the tuning circuit as much as possible. This has the advantage that the configuration is simple.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a television receiver according to an embodiment of the present invention, Fig. 2 is a diagram showing how images are projected on a television picture tube, and Fig. 3 is a vertical diagram between both channels simultaneously projected on a picture tube. FIG. 4 is a diagram showing the relationship between the synchronization signal and B channel writing to the storage circuit and reading from it. FIG. 4 is a diagram showing the relationship between the A channel and B channel video signals. FIG. FIG. 6 is an explanatory diagram of a circuit that performs writing and reading, FIG. 6 is an explanatory diagram of the operation of the memory circuit, and FIGS. 7, 8, and 9 are circuit diagrams that generate signals to be supplied to the circuit of FIG. 5, respectively. FIG. 10 is an explanatory diagram of the operation of the signal selection circuit,
Fig. 11 is an explanatory diagram of the operation of the ring counter;
13 and 14 are specific circuit diagrams of a portion of FIG. 1. 2, 6... tuner, 13... signal selection circuit,
20... Control circuit including a memory circuit for writing and reading image information, 24, 25... Detection circuit, 2
6, 27...Tuning selection circuit.

Claims (1)

[Claims] 1 A first electronic tuner that receives a first television signal, a second electronic tuner that receives a second television signal, and a channel selection signal that is applied to each of the first and second electronic tuners. First and second channel selection voltage setting circuits that set voltages for each channel; a counter and decoder that selects the channel selection voltage electronically; and a pulse that generates switching pulses to the counter and decoder. A generation circuit, a tuning switch provided for each channel and controlling switching states of the counter and decoder for each channel, and a control circuit provided between the tuning switch and the counter and decoder. , first and second switches connected to the channel up terminal and channel down terminal of this control circuit, respectively, for switching the channel upward and downward one station at a time, and for storing the second television signal. a second television signal is written in the storage means in synchronization with the synchronization signal and with scan lines and pixels thinned out, and a second television signal whose time axis is compressed is read from the storage means. a control means for reading out in synchronization with a synchronization signal of the first television signal;
By exchanging with the television signal of the above-mentioned first television signal, the second
means for displaying the television signal as a monitor; and a detection circuit for detecting the electric field strength of the second television signal; The detection output is connected to either the channel up terminal or the channel down terminal of the control circuit constituting the channel selection circuit for the second television signal, and the detection output is used to select the channel for the second television signal. A television receiver characterized by switching from one channel to another.