JPS6022865B2 - Dual screen display television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called two-screen television receiver that simultaneously displays a small monitor image within a standard image.

In particular, the present invention provides a two-screen display television receiver in which the size of the small screen can be selectively changed when the small screen is in still image mode. In addition, the present invention is capable of simultaneously displaying a small screen on a large screen using interlaced scanning.
The screen display television receiver has a small screen digital video signal storage device comprising two digital IC memories corresponding to the first field and the second field, in other words, odd and even fields, of the small screen video signal. In a two-screen display television receiver comprising:
To provide a device which sets a small screen in a still image mode, stops writing in this storage device, and reads out the memory in accordance with the size of the small screen and in correspondence with interlaced scanning.

The present invention will be explained below with reference to the drawings. Figure 1 shows
FIG. 1 is a schematic block diagram showing an embodiment of the present invention. The device of this embodiment can be roughly divided into a large screen image receiving circuit 1, which corresponds to a normal color TV receiver capable of receiving only a single screen;
A small screen image receiving circuit 2 is provided.

First, a TV reception signal is received by the antenna 3, and transmitted through a distributor 4 for preventing mutual interference between the large screen signal and the small screen signal. Enter into 2.

Broadly speaking, the large screen image receiving circuit 1 includes a large screen tuner 11, an intermediate frequency amplification and detection circuit 12, a synchronization separation circuit 13, a video amplification circuit 14, a cathode ray tube 15, an audio amplification circuit 16, and a speaker amplification circuit 16. - It has a power of 17. The connections and effects between these are the same as those of a normal TV receiver, so explanations will be omitted. On the other hand, the output of the distributor 4 is also applied to the small screen image receiving circuit 2.

In this circuit, a small-screen video signal is obtained via a small-screen tuner 21 and an intermediate frequency boosting and detection circuit 22, as seen in conventional dual-screen television receivers. First, briefly speaking, a video signal for a small screen is converted into a digital signal by an analog/digital (hereinafter referred to as A/○) converter 23, and a digital
A signal written in the C memory 24 and read out as described later is converted into an analog signal by a digital/analog (hereinafter referred to as D/A) converter 25, and then converted to an analog signal by an analog switch 26.
The image is then projected onto a cathode ray tube 15 via an image intensifier circuit 14.

The small screen video signal is also applied to a synchronization separation circuit 27, which detects and separates vertical and horizontal synchronization signals included in the small screen signal and applies them to a memory control circuit 28.

This memory control circuit 28 includes the large screen image receiving circuit 1.
The vertical and horizontal synchronization signals contained in the large screen video signal separated by the synchronization separation circuit 13 provided in the video signal are added. Based on these four types of synchronization signals, a write command, a read command, and a switching command signal are output to the A/D converter 23, digital IC memory 24, and analog switch 26. In addition, intermediate frequency increase and detection circuit 2
It is preferable to provide the output signal No. 2 as an audio output for a small screen via the audio section amplification circuit 30, and it is possible to listen to this through earphones, for example.

Furthermore, a channel selection circuit 5 is provided to enable successive selection of desired reception channels for each of the large screen and small screen. Next, specific embodiments of the present invention will be described, but the present invention is not limited to the numerical values used below and the configurations determined in relation thereto, and various modifications can be made in accordance with the spirit of the explanation to be described later.

As shown in Fig. 2, the normal TV video signal period is 52.5 seconds in the horizontal direction and 483 lines in the vertical direction, and it is preferable to select the memory capacity to be a multiple of 2n. , here, 128 horizontal scanning lines are extracted in the vertical direction to form a small screen.

In addition, the amount of information in the vertical direction of the small screen is 1 of the amount of information on the large screen.
'3, it is only necessary to extract one horizontal scanning line out of three, and the sampling range is ultimately one in the vertical direction.
28 x 3 = 4 spots. The horizontal direction is determined to be proportional to this, and 52-5x foot = 41.74 mountain Se
c. Furthermore, the memory required to store the small screen video signal is determined as follows. Here, one scanning line is made up of 64 dots, and one dot is represented by one gradation of one Chenian scale, and it is assumed to be a 4-bit signal. Therefore, the memory capacity per small screen is 128×64×4=32.7 bits. At this time, the write clock frequency is equal to the reciprocal of the horizontal sampling period divided into 64, so 64/(41.74×10-6)=1.
It is 53MHZ. The read clock frequency R should be 3 times the write clock frequency when the length of the small screen in the middle direction is 1/3 of the length of the large screen, so 1.53×3=4. It is sufficient to use the five rules MHZ. However, if the vertical axis ratio of the small screen is not required to be 3:4, it is sufficient to satisfy the relationship nR,=3nW, and both values may be close to the above values. Similarly, if you want the inside of the 4-screen to be 2'3 of the large screen, just select the readout clock frequency so that R material R2 = nose na w.
Next, writing of the small screen video signal into the digital IC memory will be explained.

Here, an example using a shift register will be explained. As mentioned above, there is a phase difference between the large screen reception signal and the small screen reception signal, so it is necessary to temporarily store the small screen reception signal, and it is not possible to write and read it at the same time. Therefore, separate shift registers are provided corresponding to the first field and the second field of the small screen reception signal.

FIG. 3 is a schematic block diagram to illustrate a write operation.

In the figure, the intermediate frequency increasing and detecting circuit 2 of FIG.
The second small screen video signal is applied to a synchronization separation circuit 41, where the vertical synchronization signal Vs and horizontal synchronization signal Hs in the small screen signal are separated.

The horizontal synchronization signal is preferably an automatic frequency adjustment circuit (A
, F, C) 42, one is applied to a latch circuit 51 (described later) after aligning the phase of the 1.53 MHz oscillation waveform with respect to the horizontal synchronization signal by the write clock oscillator 43, and the other is applied to the latch circuit 51 (described later), and the other is applied to the latch circuit 51 (described later). After being frequency-divided by 1/3 in the converter 44, it is applied to the horizontal write enable signal generator 45.
This is because, as described above, one scanning line is composed of 64 dots and one out of three scanning lines is extracted. Further, the vertical synchronization signal Vs is applied to the vertical write enable signal generator 46 and also to the frame detection circuit 47. A horizontal synchronizing signal Hs is also added to this circuit 47, and the phase relationship between the two synchronizing signals Vs and Hs is checked to determine whether the input video signal is the first field or the second field, that is, an odd field. Determine whether it is an even field. Note that the horizontal and vertical writable signal generators 45 and 46 output signals only during a period corresponding to the sampling range determined as described above out of the normal TV video signal period, and they are It is preferable to use a multipipulator or the like.

On the other hand, the small screen video signal is preferably 3.5
The signal is applied to an A/D converter 50 via an 8MHZ trap circuit 48 and a clamp circuit 49.

In order to convert each gradation into a 4-dot signal for each dot, A/○ converter 5 is digitized at each stage.
The zero output is applied to the encoder 52 via a latch circuit 51 which operates in synchronization with the clock signal from the write clock oscillator 43.

The 4-bit signal output of the encoder 52 is sent to a serial/parallel (hereinafter referred to as S/P) converter 53A or 53B.
is applied to the shift register group 54A or 54B via. The shift register groups 54A and 54B correspond to the aforementioned small screen video signal storage device. In this embodiment, four relatively low-speed and small-capacity shift registers are used for each field. For example, four shift registers with a capacity of 4K bits are used, and the 4K-bit shift register in parentheses is used as a shift register with a capacity of IK bits. It is composed of four registers, and further includes the aforementioned S/P converters 53A, 5.
3B, the effect is apparently equivalent to that of using a high-speed, large-capacity shift register, but this configuration is not particularly limited.

The output signal of the frame detection circuit 47 is passed through the clock control circuit 57 to the S/P converter 53A, In addition to 53B, either one may be activated.

Incidentally, the output signals of the gate circuit 55 and the 2/4 frequency divider circuit 56 are also applied to the clock control circuit 57 as shown. In the above manner, the small screen video signal is converted to the A/D
After conversion, each dot is converted into a 4-bit signal to represent one pitch tone, and further 64 dots per scan line and 1
The data is stored in two shift register groups 54A and 54B so as to visualize 128 or 256 scan lines per small screen.

As a result of the above, these two shift register groups 54A, 54
One of B contains a small-screen video signal corresponding to the scanning of the first field (for example, an odd field), and the other contains a small-screen video signal corresponding to the scanning of a second field (for example, an even field). are respectively A/D converted and then stored.

Here, DATA/FIX shown in FIG. 3 is a manual switch that turns the small screen into a still mode image. When this switch is activated, the clock signal from the write clock oscillator 43 is blocked by the gate circuit 55, and the A/D Writing of the converted small screen video signal to the two shift register groups 54A and 54B is stopped.

At this time, two shift register groups 54A, 54
B is the same A/D that is stored when this switch is activated.
The converted small screen video signal is controlled to be read out repeatedly. Therefore, this DATA・FIX
Unless the switch is operated, the memory contents of the two shift register groups 54A and 54B are rewritten. next,
As mentioned above, the reading of the signals written in the shift register groups 54A and 54B will be explained.

To outline the read operation, as shown in FIG. 1, the output signal of the synchronization separation circuit 13 is applied to the digital IC memory 24 via the memory control circuit 28 to determine the timing, and the stored contents of the digital IC memory 24 are transferred to the D/A. analog switch 26 at the timing instructed by the memory control circuit 28.
It opens and closes and displays four screens simultaneously on a large screen.

Further explanation will be given with reference to FIGS. 4 and 5. The large screen video signal is preferably applied to the analog gate circuit 75 via the clamp circuit 78, and further passes through the buffer circuit 46 to become a video output signal.

On the other hand, "the large-screen video signal is processed by the sync separation circuit 61.
At , vertical synchronization signal VL and horizontal synchronization signal VL in the video signal are separated. Small screen size selection circuit 81
outputs a signal, for example, a high level or low level signal, for selecting the size of the small screen to 1'9 (area ratio) or 2/3 of the size of the large screen according to a selection operation by the receiver.

The vertical read counter 83 counts the horizontal synchronizing signal HL based on the vertical synchronizing signal VL, and decodes the output to determine the display position of the small screen in the vertical direction. N2 and No or N,
A signal indicating the position of and No is outputted and supplied to the vertical read enable signal generator 64. The horizontal read timing signal generator 82 counts read clock signals using a counter with the AFC pulse as a reference, decodes the output, and starts reading the small screen memory in response to a signal from the small screen size selection circuit 81. M2 in Figure 5 to determine the end position
and Mo or M, and a signal of Mo is output. Further, the read clock oscillator 82 outputs either the clock signal NAR having a frequency three times the write frequency as described above, or the clock signal R2 having a frequency 3'2 times the write frequency, as described above. The recipient now uses the small screen size selection circuit 81 to change the size of the small screen to the large screen "X" shown in FIG.
It is assumed that the "Y" direction, which is 1/9 of the size of ", is selected.
The "1/morning screen selection signal" from the small screen size selection circuit 81, for example, a high level or low level signal, is a read start signal generator 82, a vertical read enable signal generator 64, a memory selector drive circuit 70, and a read clock oscillator 63. supplied to The read clock oscillator 63 supplies the gate circuit 66 with a clock signal R having a frequency three times the write frequency. The vertical read enable signal generator 64 uses the timing pulses N, . The horizontal read enable signal generator 65 uses the timing pulses M, , Mo supplied from the horizontal read timing signal generator 82 to form and output a signal that enables reading from M, for a period of Mo, using a flip-flop, for example. do. Therefore, the gate circuit 66 receives a read enable signal having vertical and horizontal cycles. In this way, when it is detected by the signal that the scanning beam is at a predetermined position corresponding to the small screen, the read clock signal 〆R, gated by the gate circuit 66 is applied to the clock control circuit 57. At this time, as already explained regarding writing, the shift register groups 54A and 54B store in one of them the small screen video signal to be read out in response to scanning of the first field (odd field) after being A/D converted. On the other side, a small screen video signal to be read out in response to scanning of the second field (even field) is A/D converted and stored. Therefore, the memory selector drive circuit 7
0, the shift register groups 64A and 54B are switched for each field based on the signal from the frame detection circuit 47 (for example, 54A is switched for an odd field and 54B' is switched for an even field), and this switching signal is also sent to the clock control circuit 57. is applied to

In this way, all the timing information necessary for reading is
The signal is applied to the clock control circuit 57. The storage information written to the shift register group 54A or 54B is stored from the four shift registers constituting each shift register group.
The 4-bit signal when inputted is provided so as to be outputted in a predetermined order so as to successively reproduce it.

For this purpose, a signal obtained by dividing the frequency of the output of the gate circuit 66 by 1'7 is applied to the P/S converters 71A and 72B via the clock control circuit 57 to achieve synchronization.
The output signals of the P/S converters 71A and 71B are applied to a memory selector 72, which selects an output signal to be read based on a command signal from the memory selector drive circuit 70, and selects the output signal to be read out based on a command signal from the memory selector drive circuit 70. The signal is converted into an analog signal by a /A converter 80 and applied to an analog gate circuit 75 via a low-pass filter LPF 73 and a clamp circuit 74.
The output signal of the horizontal readable signal generator 65 is applied to the analog gate circuit 75, and based on this, the large screen video signal or the small screen video signal is selectively passed through the buffer circuit 76. Video signal output terminal 7
Output to 7. As a result, as shown in FIG. 5, a picture of 4 screen "Y", which is 1'9 of the size of the large screen "X", is displayed on the screen.

Further, this small screen "Y" is output on the screen as a signal read from the same memory in the same field as shown in FIG. 6A. On the other hand, it is assumed that the recipient selects the small screen size "Z" which is 2'3 of the size of the large screen "X" using the small screen size selection circuit 81.

In this case, first turn on the above-mentioned DATA/FIX switch to still image mode, and then
After the static/large screen of "Y" is set, the selection operation of the small screen size selection circuit 81 is performed. Of course in this case,
When the small screen size selection circuit 81 selects "Z" which is 2'3 of the large screen size, it automatically selects DATA first.
- It may be linked to operate the FIX switch. Therefore, the aforementioned two shift registers 54A, 54B are stopped from being written and the same data to be read out corresponds to each scan of the first and second fields written at 1'9 of the large screen size. A/D
The converted small-screen video signal is displayed as shown in FIG. 6 and read out repeatedly, as will be explained below. The '12/sum screen selection signal' from the small screen size selection circuit 81 is supplied to the horizontal read timing signal generator 82, the vertical read enable signal generator 64, the memory selector drive circuit 70, and the read clock oscillator 63. The clock oscillator 63 has a write frequency of 3
/2 times the frequency of the clock signal R2 is sent to the gate circuit 66.
supply to.

The vertical read enable signal generator 64 uses the N2, No timing pulses from the vertical read counter 83 to
A signal is output that enables reading only during the period from 2 to No. The horizontal read enable signal generator 65 uses the M2 and Mo timing pulses supplied from the horizontal read timing signal generator 82 to output a signal that enables read only during the period from M2 to Mo.

Therefore, the vertical direction of the gate circuit 66 is from N2 to No.
, a signal indicating that reading is possible for a period from M2 to Mo in the horizontal direction is input. When it is detected by such a signal that the scanning beam is at a predetermined position corresponding to the small screen, the read clock signal 〆R2 gated by the gate circuit 66 is applied to the clock control circuit 57. At this time, the small screen video signal is digitized and stored as a still image in the shift register groups 54A and 54B, as described above. On the other hand, the memory selector drive circuit 70 receives the "2/chiro screen selection signal" from the small screen size selection circuit 81 and outputs it from the vertical read counter 83 based on the signal inputted from the frame detection circuit 47 described above. The current 1/2 frequency divided signal is input. As a result, the memory selector drive circuit 70
outputs a signal for alternately reading out the shift register groups 54A and 54B every horizontal scanning period of the same field. Therefore, on the display screen, as shown in Figure 6, the first field (odd field) and the second field (even field) each become a signal for reading out the same memory information for one horizontal scanning period. Supplies to control circuit and memory selector. In this way, all timing information necessary for reading is provided to clock control circuit 57. The following operation is the same as when "1/9 screen" is selected.

As described above, in the present invention, when a small screen is simultaneously displayed on a large screen that is performing interlaced scanning, the size of the small screen can be selectively changed when the small screen is used as a still image.

Of course, in this case, small-screen videos can also be displayed.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an embodiment of the device of the present invention;
FIG. 2 is a schematic diagram showing a sampling range of a small-screen video signal in an embodiment of the present invention, and FIG. 3 is a schematic block diagram mainly showing the operation of writing a digital video signal into a shift register of the embodiment device. 4 is a schematic block diagram mainly showing the operation of reading a digital video signal from the shift register of the embodiment device, and FIG. 5 is a schematic block diagram for explaining the display area of the small screen in one embodiment of the present invention. and FIG. 6 are diagrams for explaining the relationship between readout of the shift register for small screens and scanning lines of the present invention. 48, 49, 50, 51, 52...first converter, 5
4A, 54B... Digital signal storage device for small screen, 41, 47, 57, '53A, 53B.・・・．・・・
Write circuit, 63... Oscillator, 41, 47,
61, 83, 70, 72... memory selector means,
57, 61, 62, 64, 65, 66, 67, 82, 8
3, 71A, 71B...Reading control means, 74, 73
, 80...Second converter, DATA/FIX...
Switch for switching to still image, 81...Small screen size selection circuit. Fig. 2 Fig. 5 Fig. 6 Ship chart Ship box dimensions

Claims (1)

[Claims] 1. A two-screen television receiver that simultaneously projects a small screen on a part of the large screen using interlaced scanning, which (1) digitizes this small screen video signal and converts it into a small screen digital signal. a first converter;
) a small screen video signal storage device comprising two digital memories in which the small screen video signals respectively corresponding to the first field and the second field of the small screen video signal are stored; Data for writing the small screen video signal output from the first converter in the first field of the screen video signal into one of the two digital memories of the storage device, and writing the signal output in the second field into the other. (4) a first clock signal having a different frequency for the read clock signal of the storage device;
, an oscillator that oscillates at a second frequency and selectively outputs one of the oscillators; or a first memory selection switch that switches to the other, and a memory selector that switches readout of the storage device to one or the other of the digital memories every two horizontal scanning periods so as to correspond to every two scanning lines of the large screen. and (6) a signal read from the storage device when the memory selector means is switched to a first memory selection while being supplied with a clock signal having a first or second frequency from the oscillator. The first horizontal/vertical readout timing has a predetermined horizontal/vertical ratio so that each scanning line is displayed on a scanning line-by-scanning basis.
When a vertical read enable signal is supplied to the storage device and the memory selector means is switched to a second memory selection, a signal read from the storage device is displayed every two scanning lines. readout control means for supplying to the storage device a second horizontal/vertical readout enable signal having a readout timing that provides a small screen having the predetermined horizontal/vertical ratio and having one side twice the length of the above; (7)
a second converting the small-screen digital signal read from the storage device into an analog signal and converting it into the small-screen video signal;
a converter; (8) a switch for selectively stopping writing in the storage device and switching a small screen to a still image for controlling the signal stored in the storage device to be repeatedly read when the writing is stopped; (9) A first still image control for outputting a clock signal having a first frequency of the oscillator and controlling the memory selector means to perform a first memory selection switch; and a clock signal having a second frequency of the oscillator. a second still image control that outputs a signal and controls the memory selector means to switch the second memory selection; and a small screen size selection that is selectively performed when the writing is stopped by the switch. A two-screen display television receiver characterized by comprising a circuit.