JPS6318368B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase nonlinear acyclic digital filter to which a sampled signal is input, and particularly to a variable filter whose filter characteristics can be varied.

The filter characteristics of a digital filter can be changed by changing the coefficients of its multiplier. Therefore, the variable function of the filter can be easily realized by storing all the coefficients corresponding to the desired characteristics in advance in a read-only memory (ROM) and supplying the necessary coefficients to the multiplier of the filter. However, if the number of multiplier coefficients of the filter and the types of characteristics desired to be realized are large, the memory size of the ROM becomes large and the realization becomes difficult. For example, filter tap = 100, variable step = 50,
If the coefficient word length is 12 bits, 60KBit of memory is required. On the other hand, there is a conventional method for significantly reducing the number of variable coefficients in a phase-linear acyclic digital filter (FIR filter), for example, in Japanese Patent Application No. 52-143648 ``Acyclic Variable Filter''.
is proposed. However, no effective method has been proposed in the case of phase nonlinearity.

This invention proposes a circuit configuration of a variable filter that greatly reduces the number of types of variable coefficients in a phase nonlinear acyclic filter.

When P=jω (j=√−1, ω=2πf), the transfer function H(P) of all zero points in the P plane is given by equation (1).

H(P)= _N-1 〓 ⁱ⁼⁰ a _i P ⁱ ...(1) a is a constant. Transfer function H(P) is expressed as Z(=
e ^j 〓 ^T ) The transfer function of the digital filter can be obtained by converting to the plane, and in this invention, the following equation (2) is used for this conversion.

P=jKsinΩT...(2) Here, T=1/ _s ( _s : sampling frequency)
It is. From equation (2), ω=KsinΩT...(3) The function of equation (3) is obtained and is shown in Figure 1. As can be seen from Figure 1, the ω-axis [-K, K] is on the Ω-axis [-
π/2T, π/2T]. Therefore, by varying K, the amplitude characteristic of the Z-plane transfer function obtained by the transformation of equation (2) can be varied in the Ω-axis direction.

On the other hand, the right side of equation (2) can be expressed using Z as follows.

jsinΩT=1/2 1-Z ^-2 /Z ^-1 ...(4) Therefore, if K/2 1-Z ^-2 /Z ^-1 is substituted for P in equation (1), the transmission in the Z plane is Get the function. Let this be G(Z).

However, K ^* =K/2. Furthermore, since the amplitude of Z ^N-1 is 1 in G(Z), the amplitude characteristics do not change even if Z ^N-1 is set to 1, so if this is G ^* (Z), becomes. FIG. 2 shows an example of a configuration that realizes equation (6).
The input terminal 11 has N-1 delay devices 1 _N-2 to 1 ₁ each having a delay amount of T seconds at the sampling period of the input signal.
is supplied to the input side of the cascade-connected delay device 1 _N-2 .
Also, a variable multiplier 12 that multiplies by a variable coefficient K ^* ,
Delay devices 13 and 14 whose multiplication output has a delay time of T seconds
N-1 arithmetic stages 2 consisting of an adder 15 that adds up what passes through the series circuit and what doesn't pass through the series circuit 2 _N-
2 to 2 ₀ has its multiplier 12 on the input side, and adder 1
5 are connected in series as the output side of 5. The input terminal 11 is supplied to the input side of the arithmetic stage 2 _{N- 2 through a fixed multiplier 3 N- 1 with a coefficient a N-1} , and is supplied to the input side of the arithmetic stage 2 _{N-2 .}
Each output is a fixed multiplier 3 with coefficients a _N-2 to a ₀ , respectively.
Each adder 1 of operation stage 2 _N-2 to ₂₀ through _N-2 to ₃₀
5. The output of the adder 15 of the arithmetic stage 2 ₀ is supplied to the output terminal 16 .

In this configuration, when i=0, the input signal at the terminal 11 passes through N-1 delay devices 1N _-2 to ₁₀ , and is multiplied by _a0 by the multiplier ₃₀ , which is then output as shown in (6). in the ceremony
Match the value of a ₀ Z ^-(N-1) . The output of delay device 1 _{and 2} is
Z ^-(N-1)+1 , which is multiplied by _a1 in multiplier ₃₁ .
a ₁ Z ^-(N-1)+1 . Since the calculation of K ^* (1-Z ^- 2) is performed in each of the calculation stages _2N-2 to ₂₀ , the output of the multiplier ₃₁ is sent to the multiplication of the calculation stage ₂₃ through the adder 15 of the calculation stage ₂₁ . Multiplied by K ^* in vessel 12
a ₁ Z ^-(N-1)+1・K ^* , and excluding the input from multiplier ₃₀ , the output of adder 15 is a ₁ Z ^-(N-1)+1・K ^* (1−
Z ^-2 ), which is the value when i=1 in equation (6). Similarly, it can be seen that FIG. 2 is for calculating equation (6).

In FIG. 2, N-1 variable multipliers 12 are used, but their variable coefficients are K ^* and are all the same.
Therefore, in order to change a filter characteristic, it is only necessary to store one value of K ^* for that one characteristic.

Next, consider the case where the transfer function H(P) is factorized.

H (P) = _M 〓 ⁱ⁼¹ (a _0i + a _1i P + a _2i P ² ) ...(7) G (Z) = _M 〓 〓 _i=1 (a _0i + a _1i (K/2 1-Z ^-2 /Z ^-1 )+a _2i (K/2
1-Z ^-2 /Z ^-1 ) ² ) =Z ^2M _M 〓 〓 _i=1 (a _0i Z ^-2 +a _1i K ^* Z ^-1 (1-Z ^-2 )+a _2i K ^*2 (1-Z ^-2
) ² )...(8) Since the amplitude of Z ^2M is 1 in G (Z), remove it to get G ^* (Z).

G ^* = _M 〓 〓 ⁱ⁼¹ (a _0i Z ^-2 +a _1i K ^* Z ^-1 (1-Z ^-2 ) +a _2i K ^* (1-Z ^-2 )
² )...(9) Figure 3 shows a circuit that realizes the following equation (10), which represents one value of i in equation (9).

H _i (Z)=a _0i Z ^-2 +a _1i K ^* Z ^-1 (1-Z ^-2 )+a _2i K ^* (1-
Z ^-2 ) ² ... (10) A signal from the input terminal 17i is input to a cascade connection of four delay devices 21 to 24 having a delay time T. The output of the delay device 22 is a fixed multiplier 25 with a coefficient a _0i
is multiplied to obtain the first term a _0i Z ^-2 on the right side of equation (10),
This is supplied to adder 26. The output of the delay device 21 is Z ^-1 and the output of the delay device 23 is Z ^-3 , and these are added in the adder 27 to obtain Z ^-1 (1-Z ^-2 ), which is a fixed multiplication. The multiplier 28 multiplies a _1i and the multiplication output is sent to the variable multiplier 31 via the adder 29.
is supplied to K ^* and multiplied by a _1i K ^* Z ^-1 (1−Z ^-2 )
is obtained, and its output is supplied to the adder 26.
In this way, the second term on the right side of equation (10) is obtained. The output of the delay device 22 is multiplied by -2 by the fixed multiplier 32 to become -2Z ^-2 , and this, Z ^-4 from the delay device 24 and 1 from the terminal 17i are added by the adder 33 (1 −Z ^-2 ) ² is obtained and its output is output by the fixed multiplier 34.
a _2i is multiplied and further multiplied by K ^* in the variable multiplier 35 to obtain a _2i K ^* (1−Z ^-2 ) ² , which is added to the adder 2.
9 to the variable multiplier 31 and further K ^*
By multiplying, the third term of equation (10) is obtained. The output of adder 26 is provided to output terminal 18i.

The circuit with transfer function H(Z) is the circuit with Hi(Z)
It is constructed by cascading M circuits, each with =0 to i=M.

As mentioned above, in the circuits shown in Figures 2 and 3, there is only one type of variable coefficient K ^* and the variable coefficient K ^* required to change the filter characteristics.
The memory size for storing can be significantly reduced.

In addition, although the delay device, multiplier, etc. were configured as separate circuits in the above example, they can be configured using a microcomputer without configuring each circuit individually as shown in FIG.
A filter can also be constructed by performing calculations using the circuit shown in FIG.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the frequency axis mapping relationship associated with conversion from the P plane to the Z plane, and FIG. 2 is a configuration diagram showing an example of the configuration of an acyclic variable filter according to the present invention.
FIG. 3 is a diagram showing one operation stage of a configuration example of the acyclic variable filter according to the present invention. 11: Input terminal, 16: Output terminal, 1 ₀ ~ 1 _N-
2 , 13, 15, 21 to 24: Delay device with sampling period T, 2 ₀ to 2 _N-2 : Arithmetic stage, 3 ₀ to 3 _N-1 : Fixed multiplier, 12, 31, 35: Variable multiplier .

Claims (1)

[Claims] 1. The delay amount of the sampling period of the input signal is successively N
a first cascade delay means which doubles the output of the variable multiplication means;
cascade calculation means for performing the calculation of the first calculation means in cascade N times, which includes addition means for adding outputs delayed by the delay means; and first fixed multiplication means for supplying an input signal to the first cascade delay means; means for supplying the first stage input of the cascade calculation means through the cascade calculation means, and means for supplying each delayed output of the first cascade delay means to the second to N-th
1 fixed multiplication means, respectively, to the addition means of each corresponding operation stage of the cascade operation means, each of the first fixed multiplication means and the second to N-1 fixed multiplication means; An acyclic variable filter characterized in that the multipliers are independent of each other and a filter output is obtained as the output of the final stage of the cascaded arithmetic means. 2. first to fourth delay means each having a delay amount corresponding to the sampling period of the input signal and delaying in series;
a first addition means for adding the input signal of the first delay means, the output obtained by multiplying the output of the second delay means by a first fixed value, and the output of the fourth delay means; a multiplication means for fixed multiplication and variable multiplication, a second addition means for adding the output of the first delay means and the output of the third delay means, an output obtained by multiplying the added output by a third fixed multiplication, and the multiplication means a third addition means for adding the output of the second delay means; a variable multiplication means for variably multiplying the added output; and a fourth addition means for adding the multiplication output, the output of the second delay means, and the fourth fixed multiplied output. It becomes more,
The multiplier for the second fixed multiplication and the multiplier for the fourth fixed multiplication are provided in a plurality of arithmetic means which are independent of each other, with the input side of the first delay means as an input and the output side of the fourth addition means as an output. An acyclic variable filter configured to operate in cascade.