JPS63181449A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63181449A JPS63181449A JP1471987A JP1471987A JPS63181449A JP S63181449 A JPS63181449 A JP S63181449A JP 1471987 A JP1471987 A JP 1471987A JP 1471987 A JP1471987 A JP 1471987A JP S63181449 A JPS63181449 A JP S63181449A
- Authority
- JP
- Japan
- Prior art keywords
- stepped
- oxide film
- resist
- stepped part
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 239000007772 electrode material Substances 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 この発明は、半導体装置に関する。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor device.
従来の技術
第2図(a)の断面図のように、半導体基板1上の絶縁
体層2に、段差が存在し、この段差を横ぎって配線を形
成する場合、まず絶縁体層2の表面に、第2図(b)に
示すように、配線材料である導体層3を形成し、続いて
、この導体層3をフォトレジストのパターンを用いて配
線に形成する。BACKGROUND ART As shown in the cross-sectional view of FIG. 2(a), there is a step in the insulator layer 2 on the semiconductor substrate 1, and when wiring is to be formed across this step, the insulator layer 2 is first As shown in FIG. 2(b), a conductor layer 3 made of wiring material is formed on the surface, and then this conductor layer 3 is formed into wiring using a photoresist pattern.
このとき、フォトレジストがポジ型レジストの場合、同
レジストパターンを形成するための露光の際に、平担な
部分ではレジストに吸収される光は均一となるが、段差
の凹部分では、反射される光の量が少なくなって、凹部
分の実質的な露光量が減る。すると上記の段差開部分に
は第2図(c)のように、レジスト11が残る。この残
存レジスト11のために配線となる導体のエツチングを
おこなう際にも段差凹部に配線材料、つまり導体材料が
エツチングされずに残る。このような導体材料の残存が
生じると、上記段差を横ぎる配線が複数であるときには
、第3図の斜視図によって示したように、残存の導体3
aによってそれぞれの配線3.3が短絡されてしまう。At this time, if the photoresist is a positive resist, during exposure to form the same resist pattern, the light absorbed by the resist will be uniform in the flat parts, but it will be reflected in the concave parts of the step. This reduces the amount of light that enters the recessed area, reducing the effective amount of exposure of the recessed portion. Then, the resist 11 remains in the stepped opening portion as shown in FIG. 2(c). Because of this residual resist 11, even when etching the conductor that will become the wiring, the wiring material, that is, the conductor material remains in the step recess without being etched. When such residual conductor material occurs, and when there is a plurality of wirings crossing the step, the remaining conductor material 3 as shown in the perspective view of FIG.
The respective wirings 3.3 are short-circuited by a.
上記のような短絡部分ができると正常動作が不可能な半
導体装置ができてしまい、歩留が低下する問題があった
。If such a short-circuit portion is formed as described above, a semiconductor device will be produced which cannot operate normally, resulting in a problem of lower yield.
発明が解決しようとする問題点
上述のように、半導体基板表面の絶縁体に段差がある場
合、この段差を横ぎって配線を形成するとき、配線パタ
ーンをポジレジストで形成すると、上記段差部分にレジ
ストが残存し、配線となる導体材料のエツチングの際に
導体が段差凹部に残り、配線が複数の場合、それらが短
絡してしまうことがある。本発明は、このような問題点
を解消するものである。Problems to be Solved by the Invention As mentioned above, when there is a step in the insulator on the surface of a semiconductor substrate, when wiring is formed across this step, if the wiring pattern is formed using a positive resist, the step will be Resist remains and the conductor remains in the step recess when etching the conductive material that will become the wiring, and if there are multiple wirings, they may be short-circuited. The present invention solves these problems.
問題点を解決するための手段
本発明は、半導体基板上の絶縁膜に段差部およびその段
差部を横断する導体層を有し、かつ、前記導体層の近傍
の前記段差部分に突起を設けたものである。Means for Solving the Problems The present invention has an insulating film on a semiconductor substrate having a stepped portion and a conductor layer that crosses the stepped portion, and a protrusion is provided in the stepped portion near the conductive layer. It is something.
作用
本発明によれば、フォトレジストへの露光が、段差部分
に設けられた突起によって乱反射し、結果として、同段
差の凹部でのレジストの残存、したがって、導体層の残
存も突起部分で解消される。According to the present invention, the exposure light to the photoresist is diffusely reflected by the protrusions provided at the step portion, and as a result, the remaining resist in the recesses of the same step portion, and therefore the remaining conductor layer, is also eliminated at the protrusion portions. Ru.
実施例
第1図は、本発明をディスクリート素子に適用した実施
例を要部斜視図によって示す。実際の素子はエミッタと
してn+層、ベースとしてp層を半導体基板に注入拡散
して形成してあり、上記半導体基板上には絶縁膜として
シリコン酸化膜が存在している。ベース領域上の酸化膜
はそれ以外の部分よりも薄く、ベース領域の周辺部分に
おいて酸化膜表面には0.7umの段差がある。第1図
は、この酸化膜2上の概要形状である。このとき、段差
部分の凹部に電極材料であるアルミニウムが残存すると
エミッタ電極31とベース電極32が短絡したことにな
るが、突起4を形成することによって上記のような短絡
を防ぐことができた。Embodiment FIG. 1 is a perspective view of a main part of an embodiment in which the present invention is applied to a discrete element. The actual device is formed by implanting and diffusing an n+ layer as an emitter and a p layer as a base into a semiconductor substrate, and a silicon oxide film is present as an insulating film on the semiconductor substrate. The oxide film on the base region is thinner than other parts, and there is a step difference of 0.7 um on the oxide film surface in the peripheral part of the base region. FIG. 1 shows the general shape of this oxide film 2. As shown in FIG. At this time, if aluminum, which is the electrode material, remained in the recessed part of the stepped portion, the emitter electrode 31 and the base electrode 32 would be short-circuited, but by forming the protrusion 4, such a short-circuit as described above could be prevented.
発明の効果
本発明によると、絶縁膜の段差部分に設けられた突起に
よって、フォトレジストへの露光が、その段差凹部にも
浸透し、レジストの残存をなくし、したがって、導体層
の残存がなくなる。Effects of the Invention According to the present invention, the projections provided on the stepped portions of the insulating film allow the exposure of the photoresist to penetrate into the stepped recesses, eliminating any remaining resist and, therefore, eliminating any remaining conductor layers.
第1図は本発明実施例の要部斜視図、第2図(a)〜(
c )は従来例を工程順に示す各断面図、第3図は、そ
の要部斜視図である。
2・・・・・・酸化膜、31.32・・・・・・電極、
4・・・・・・絶縁体膜の突起。
代理人の氏名 弁護士 中尾、敏男 ほか1名?−酸化
膜
4− 突起
31− 堂」重
第1図
3?
第2図
?Figure 1 is a perspective view of the main parts of an embodiment of the present invention, Figures 2 (a) to (
c) is a cross-sectional view showing the conventional example in the order of steps, and FIG. 3 is a perspective view of the main part thereof. 2... Oxide film, 31.32... Electrode,
4... Protrusion of insulator film. Name of agent: Lawyer Nakao, Toshio and one other person? -Oxide film 4-Protrusion 31-Dou” heavy Figure 1 3? Figure 2?
Claims (1)
る導体層を有し、かつ、前記導体層の近傍の前記段差部
分に突起をそなえたことを特徴とする半導体装置。1. A semiconductor device comprising: a step portion in an insulating film on a semiconductor substrate; and a conductor layer crossing the step portion; and a protrusion provided at the step portion near the conductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1471987A JPS63181449A (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1471987A JPS63181449A (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63181449A true JPS63181449A (en) | 1988-07-26 |
Family
ID=11868942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1471987A Pending JPS63181449A (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63181449A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107507840A (en) * | 2017-08-29 | 2017-12-22 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
CN111180468A (en) * | 2020-01-06 | 2020-05-19 | 昆山国显光电有限公司 | Display panel, display device and preparation method of display panel |
-
1987
- 1987-01-23 JP JP1471987A patent/JPS63181449A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107507840A (en) * | 2017-08-29 | 2017-12-22 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
CN107507840B (en) * | 2017-08-29 | 2020-10-16 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
CN111180468A (en) * | 2020-01-06 | 2020-05-19 | 昆山国显光电有限公司 | Display panel, display device and preparation method of display panel |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR0136569B1 (en) | Fabrication method of contact hole in semiconductor device | |
US3436611A (en) | Insulation structure for crossover leads in integrated circuitry | |
US3354360A (en) | Integrated circuits with active elements isolated by insulating material | |
US5237199A (en) | Semiconductor device with interlayer insulating film covering the chip scribe lines | |
US3653898A (en) | Formation of small dimensioned apertures | |
JPS63181449A (en) | Semiconductor device | |
JP3430290B2 (en) | Method for manufacturing semiconductor device | |
US3922184A (en) | Method for forming openings through insulative layers in the fabrication of integrated circuits | |
US3807038A (en) | Process of producing semiconductor devices | |
KR0183899B1 (en) | Magnetic arrangement contact hole forming method | |
JPS62194628A (en) | Manufacture of semiconductor device | |
JPH03203323A (en) | Manufacture of semiconductor device | |
JPH03108359A (en) | Wiring structure and formation method therefor | |
KR100204910B1 (en) | Interconnecting method of semiconductor device | |
KR950006340B1 (en) | Contact hole forming method of semiconductor device | |
JPH01272133A (en) | Semiconductor device | |
JPH0621240A (en) | Wiring connecting structure of semiconductor device and manufacture thereof | |
KR0166488B1 (en) | Fine contact forming method in the semiconductor device | |
KR100192439B1 (en) | Method for forming a contact hole of a semiconductor device | |
JPS62171142A (en) | Wiring formation | |
JPH02199835A (en) | Manufacture of semiconductor integrated circuit device | |
JPS6362357A (en) | Interconnecting method in semiconductor circuit | |
JPH04264755A (en) | Semiconductor device and manufacture thereof | |
JPS63104354A (en) | Structure of semiconductor device | |
JPS63292649A (en) | Manufacture of semiconductor device |