JPS63181043A - Generating device for false input signal supplied to controller - Google Patents

Abstract

PURPOSE:To remarkably heighten the developing efficiency of a controller, by supplying a digital false input signal directly to the data bus of the controller. CONSTITUTION:Since the false input signal to the data bus 26 is sent directly from a false input signal generating device 10 without interposing an I/O interface device, etc., it is possible to check a control program without necessitating a peripheral hardware such as the I/O interface device, etc. Therefore, it is possible to perform the development of the control program in parallel with that of the peripheral hardware of a CPU14 independently. In such a way it is possible to heighten the developing efficiency of the controller 12 remarkably, and to shorten a period required for the development of the controller substantially.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a device for supplying a pseudo input signal to a control device in which a control program is executed in order to check the program.

(Prior Art) Even once a program for a control device configured mainly by a microprocessor is completed, the initial level of completion of the program is generally extremely low, and there are usually many errors in the program. There is.

Therefore, the work of carefully checking and correcting the program is repeated over a considerable period of time, thereby completing a program that ensures the desired control operation.

In the future, after the hardware around the processor of the control device is completed, the pseudo input signal generating device 10 is connected to the control device 12 as shown in FIG. 2 (A>).

In this pseudo input signal generator 10, the switching signal 100. shown in FIG. 2(B). Analog signal 102. A pulse signal 104 is jqed, and the control head 12 obtains a control signal through arithmetic processing using these input signals 100, 102°104.

The control signal is confirmed using a logic analyzer or the like, and the control program is checked and then corrected.

(Problems to be Solved by the Invention) Conventionally, however, pseudo signals 100, 102, 104 similar to actual input signals are supplied from the pseudo input signal generator 10 to the control device 12.
In order for microprocessor 2 to execute the program, it is necessary to complete the peripheral hardware of the microprocessor in advance, such as the f10 interface circuit 1 peripheral signal processing circuit, and therefore debugging that requires a lot of time is required. This work has to be carried out after the peripheral hardware is completed, which poses a problem in that product development cannot be carried out efficiently.

The present invention has been made in view of the above-mentioned conventional problems (ζ), and its purpose is to check the control program of a microprocessor used for control arithmetic processing in a control device without waiting for the completion of peripheral hardware. An object of the present invention is to provide a pseudo input signal generating device for a control device that can perform the following functions in parallel and independently.

(Means for Solving the Problem) In order to achieve the above object, in the present invention, a digital data string indicating an input signal of a control signal is written in advance, and the digital data string is transferred to a data bus of a control device. Pseudo input signal storage means to be read is provided.

When it is confirmed that the address indicated by the data sent to the address bus of the control device matches the address preset for the digital data string, reading of the digital data string is permitted by the read permission means. Ru.

Roughly speaking, the read address of each data in the digital data string is based on the time series change of the input signal! ! In is sequentially specified by the read address specifying means.

(Operation) In the present invention, a digital pseudo input signal is directly supplied to the data bus within the control device without going through peripheral hardware.

(Description of Embodiments) Hereinafter, preferred embodiments of the apparatus according to the present invention will be described based on the drawings.

A first embodiment is shown in FIG. 1, in which a CPU 14 performs arithmetic processing for engine control according to a control program stored in a ROM 16.

RAM18 is used for the calculation processing, and CPtJ14
is given an interrupt notification signal from the interrupt signal generator 20.

Furthermore, the decoder 22 decodes the address data output from the CPU 14, thereby causing the ROM 16. R
AM18. One of the interrupt signal generators 20 is selected.

Note that the address bus 24. of the control device 12. data bus 2
6 has no input/output interface elements connected to it, and its peripheral hardware is in an unfinished state.

and address bus 24. The data bus 26 includes a decoder (a kind of comparator) 2 of the simulated input signal generator 10.
8 and a memory (which may be a memory array) 30 are respectively connected, and the decoder 28 is given an address arbitrarily set by an address setter 32 (for example, $1000>).

This address setter 32 can be configured with a hexadecimal switch,
When the decoder 28 confirms that the set address matches the address indicated by the data on the address bus 24, a match signal is applied from the decoder 28 to the data output enable terminal of the memory 30.

Then, a digital data string indicating input signals of the control device 12 is written in the memory 30, and in this example, various switching signals 106-1 and 106-2 shown in FIG. 3(A) are written.
..., engine intake air amount detection signal @10 in the same figure (B)
8. Digital data strings 112-1 each indicating the detection pulse 110 of the same figure (C) obtained by the crank angle sensor,
112-2..., 114, 116 are shown in Fig. 3 (A), (
B) and (C) are written in the memory 30.

As understood from FIG. 3(A), the state of the switching signal @106-1.1062... is the binary data r1J in each bit of the digital data string 112-1.112-2... , rOJ, and their data are represented by switching signals 106-1, 106-2...
・Continuous addresses (parts) are written in chronological order.

Further, as can be understood from FIG.
It is formed of hexadecimal values, and these values are also written in consecutive addresses in the memory 30.

As roughly understood from FIG. 3(C), the signal 110
The pulse period of 1. , 12 . . . and is determined at the time of pulse input, the digital data string 110 is also formed of decimal values, and these values are also written in the memory 30 at consecutive addresses according to the time series changes of the signal 110. .

However, if one pulse is obtained per engine rotation and the continuation clock is 10 μsec, and the engine rotation speed is 6000 beats, the pulse period is several 1
i1000 (1000X 10μsec = 10m
5ec, 60X 1000m5ec/10msec
=600Orpm).

The count value of the counter 34 is supplied to the memory 30 having the above-mentioned storage contents as data specifying the read address of the memory 30, and the counter 34 counts the clock pulses of the clock generator 36.

This embodiment has the above configuration, and its operation will be explained below.

First, the digital data strings shown in FIG. 3 (A>, (B), and (C)) are written into the memory 30, and then the I10 element is allocated to a predetermined address (for example, $1000) in the address setter 32 according to the address. be done.

And RO where the control program once created is written.
M16 is set in the control device 12, and execution of the program is started by the CPU 14.

When this control program is executed, when the CPU 14 sends 7 addresses, which are the same as the set address of the address S9 regulator 32, to the address bus 24, a match signal is applied from the decoder 28 to the data output enable terminal of the memory 30.

As a result, the memory 30 is selected, and the data recorded at the address indicated by the predetermined count value of the counter 34 is directly sent from the data bus 26 as a digital simulated input signal. .

Thereafter, each time the counter 34 is incremented by the clock 36, new time series data is transferred to the data bus 26.
sent to.

Arithmetic processing using the simulated input signal sent from the memory 30 to the data bus 26 in this way is performed by the CPU 14.
It is carried out according to the control program of M16, and as a result,
The data that serves as control commands such as fuel injection timing is C.
Jqed by PU14.

The arithmetic processing results of the CPU 14 are checked using a logic analyzer or the like, thereby efficiently checking the control program.

As explained above, according to this embodiment, the data bus 26
Since the simulated input signal is sent directly from the simulated input signal generator 10 without going through the I10 interface element etc.,
Control programs can be checked without requiring peripheral hardware such as an I10 interface element.

Therefore, the control program can be developed independently and in parallel with the development of peripheral hardware for the CPU 14, which makes it possible to significantly improve the development efficiency of the control device 12 and significantly shorten the period required for development. .

A second embodiment is shown in FIG. 4, in which an address setter 38 and a decoder 40 are added.

The address setter 38 is set with the start address of the program or routine to be checked.
When the decoder 40 confirms that the set address matches the address indicated by the data on the address bus 24, a trigger signal is supplied from the decoder 40 to the counter 34.

Accordingly, in this embodiment, when execution of the program or routine to be checked begins, the counter 34 begins counting, thereby sending a digital simulated input signal from the memory 30 to the data bus 26.

Therefore, according to this embodiment, it is possible to reliably give an initial value to the program or routine to be checked, and as a result, even if the control program is complex and consists of many programs, Even if the program is running, you can reliably extract and check only the necessary programs or routines.

Therefore, it is possible to greatly improve the efficiency of developing control programs.

A third embodiment is shown in FIG. 5, and this embodiment takes into consideration that an interrupt processing program is executed at a predetermined cycle.

For this reason, the coincidence signal of the decoder 28 is counted by the counter 34, and after the decoder 40 starts the counting operation of the counter 34 at the start address of a predetermined program or routine, the counter 34 is counted every time the CPU 14 accesses the pseudo input signal. ]・1 shift is incremented.

Therefore, even if an interrupt processing program is executed at a predetermined control cycle, it is possible to reliably read out the data stored in the memory 30 corresponding to each pseudo input signal access by the CPU 14 as a pseudo input signal. Become.

Furthermore, since the count value of the counter 34 is incremented each time a pseudo input signal is accessed, unnecessary data can be omitted to reduce the number of manual operations required for checking, and therefore pseudo input signals can be generated for a longer period of time. As a result, it becomes possible to greatly improve the efficiency of checking the control program.

By the way, the pseudo input signal generator 1 of each embodiment explained above
If a plurality of 0's are used in arbitrary combination, it becomes possible to perform a composite check of a control program consisting of a plurality of programs that process a large number of input signals.

(Effects) As explained above, according to the present invention, a digital pseudo input signal is directly given to the data bus of the control device.
Regardless of the development status of the control device's processor peripheral hardware, its development and program development can be done in parallel and independently.This greatly increases the development efficiency of the control device and allows the development to be completed in a short period of time. becomes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a preferred first embodiment of the device according to the present invention, FIG. 2 is an explanatory diagram showing a conventional device, FIG. 3 is an explanatory diagram of the stored contents of the memory 30 in FIG. 1, and FIG. The figure is a block diagram showing a second preferred embodiment of the device according to the present invention;
FIG. 5 is a block diagram showing a third preferred embodiment of the apparatus according to the present invention. 10... Simulated input signal generator 12... Control device 14... CPU 16... ROM 18... RAM 20... Interrupt signal @ optical generator 22... Decoder 24... Address Bus 26...Data bus 28...Decoder 30...Memory 32...Address setter 34...Counter 38...Address setter 40...Decoder Figure 2 Figure 4 ρ

Claims (1)

[Claims] (1) Pseudo input signal storage means in which a digital data string representing an input signal of a control device mainly configured with a microprocessor is written in advance, and the digital data string is read out to a data bus of the control device; and a control device. read permission means for permitting reading of the digital data string when it is confirmed that the address indicated by the data sent to the address bus matches the address set in advance for the digital data string; A pseudo input signal generating device for a control device, comprising: read address designating means for sequentially designating a read address of each data in a column in order of time-series change of the input signal.