JPS63180285A - Phase detecting circuit - Google Patents

Abstract

PURPOSE:To shorten a convergence time and to prevent the disturbance of a screen by controlling the phase of a switch control signal outputted from exclusive OR circuits in such a way that data which is inputted to an integrator becomes the polarity of satisfactory integral efficiency. CONSTITUTION:The outputs of latch circuits 21 and 22 are inputted to a subtractor 28, and the output of the circuit 22 is subtracted from the output of the circuit 21. The uppermost bit of positive or negative data is supplied to either of the exclusive OR circuits, and a clock s3 to the other. The polarity of the clock s3 is controlled by the output of the subtractor 28, and it outputs '0', if the polarity is positive, and '1', if negative. Namely, it decides a phase difference between a sampling phase and input data. If the phase difference is in the range of 90 deg. and 270 deg. the clock s3 is inverted, and is supplied as the control signal of a switch SW1. Thus, convergence time is shortened and the disturbance of the screen can be prevented.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a phase detection circuit used in a digital television signal processing circuit or the like.

(Prior Art) Phase detection circuits are used in various locations in digital television receivers and digital video tape recorders. Figure 4 shows conventional digital automatic phase detection (APC)
This shows the configuration of the circuit, and FIG. 5 is a timing chart for explaining its operation. This phase detection circuit is used, for example, as a color synchronization circuit of a digital color signal processing section, and a digitized color signal is supplied to the input terminal 11. The normal video signal is sampled with a 4fsc clock, and the clock is phase-synchronized with the ±1 axis and ±Q axis of the burst signal.

The burst signal is sampled by the latch circuit 12 with a sampling clock s4 having a frequency of 2fsc, and the burst signal is sampled at the node n
1 is output. The signal at the node n1 is supplied to one input node of the switch swl for polarity selection, and is also supplied via the inverter 13 to the other input node of the switch swl. The switch swl is used to adjust the polarity of the input data when the output thereof is subjected to integration processing in the next stage integrator. The integrator is adder 1
4, a saturation circuit 15, and a latch circuit 16, and the adder 14 adds the output of the latch circuit 16 and the output from the switch sw1. In this integrator, the latch circuit 16 is first cleared prior to the burst period of the horizontal cycle, and is driven by the clock s4 to obtain an integrating operation during the burst period.

The output of the integrator is latched at the timing of a clock s5 obtained in a horizontal period, and is used, for example, as frequency control data for a voltage controlled oscillator.

FIG. 5 is a timing chart showing the operation of the above-mentioned phase detection circuit, in which (a) shows a 4fsc sampling clock, and (b) shows a 2fsc clock S4. Also, in the same figure (C), the switch swl is controlled by the fsc clock.
This is a clock that controls the input signal and inputs a carry to the adder 14.

Further, (d) in the figure is a clock that sets the start timing of the phase detection process, and is supplied as a clear pulse to the latch circuit 16 at horizontal intervals. In addition, in FIG. 4(e), the detection output is supplied as a latch pulse to the latch circuit 17 in order to hold the detection output for one horizontal period. Furthermore, in the same figure (f),
This is a clock obtained during the burst gate period, and is used as a burst flag clock BF. Same figure (g)
shows the phase relationship between the signal at the node n1 and the clock s3 that controls the switch s w 1. clock S3
is “H”, switch s1 switches to inverter 1.
Since the output on the 3rd side is selected, the output is set to positive polarity. (h) in the same figure shows the state of change in the output data of the node n2. Further, (i) in the same figure shows output data of the latch circuit 17.

(Problems to be Solved by the Invention) FIG. 6 shows a situation where the phase of the internal clock is controlled and converged by the phase detection circuit described above. −
If there is a phase difference of 90° to +90°, Fig. 6 (a
), the phase changes in the direction shown by the arrow in FIG. 2(b) and converges to the phase indicated by the circle. The figure (C) is 9
It shows the convergence direction when there is a phase difference of 0° to 270°.

By the way, when looking at the above convergence direction, -90' to +9
For a phase difference of 0°, convergence is achieved relatively quickly and the time to phase lock is short, but when there is a phase difference of 90'' to 270°, the phase control data for convergence corresponds to the convergence point. Since the phase control data changes in a direction away from the phase control data (eventually toward a convergence point), it takes time to obtain phase lock.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a phase detection circuit that can shorten the time required for convergence for phase lock.

[Structure of the Invention] (Means for Solving the Problems) This invention uses a reference signal obtained by digitizing an AC signal that arrives at a predetermined arrival period with a sampling pulse having a frequency twice that of the AC signal. a sampling means for sampling; a switch means for selecting, in accordance with a control signal, whether the output of the sampling means has an inverted polarity or a non-inverted output, and supplies the selected output to an integrating circuit operating at the same frequency as the sampling pulse; In a phase detection circuit comprising a latch means for touching the output of the integrating circuit during the reference signal period of the arrival period, the means for generating the control signal for controlling the selection operation of the switch means is the same as the sampling pulse. An exclusive OR circuit in which a frequency switching pulse is supplied to one input, and the upper few bits of the reference signal are input, this data is sampled twice in one cycle of the reference signal, and the sample data is subtracted. and supplying the most significant bit of the result to the other input of the exclusive OR circuit to control the phase of the control signal output from the exclusive OR circuit. The structure is as follows.

(Function) With the above phase comparison means, the phase of the switch control signal output from the exclusive OR circuit is input to the integrator, regardless of the initial phase relationship of the signals to be compared. The data is controlled to have a polarity with good integration efficiency, and the convergence time is shortened.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, which differs from the conventional one in a circuit that generates a control signal for controlling the switch s w l. Therefore, the same parts as in the conventional circuit shown in FIG. 4 will be described with the same reference numerals. In the case of the present invention, a part of the signal at the input terminal 11, for example, the upper three bits, is supplied to the latch circuits 21 and 22. The latch timing of the latch circuits 21 and 22 is as follows: the inverter 23, the latch circuit 24, the AND circuit 25, and the latch circuits 26 and 27.
defined by the timing circuit. Now, the burst flag shown in FIG. 2(b) is supplied to the latch circuit 24 and the inverter 23, and the latch circuit 24 is clocked at s3 (
(shown in FIG. 2(a)), the AND circuit 25
The output shown in FIG. 2(C) is obtained. Then, when this output is supplied to the latch circuits 27 connected in series and each latch circuit 26, 27 is driven with a signal obtained by inverting the clock s4 of 4fsc, the second
A latch pulse at timing t1 in Figure (e) is supplied,
For the latch circuit 22, the timing t in FIG.
Two latch pulses are provided.

Therefore, the latch circuits 21 and 22 latch the data of the phase indicated by the black circles in FIG. 2(e).

The output data of the latch circuits 21 and 22 are supplied to a subtracter 28, and the output a of the latch circuit 22 is subtracted from the output of the latch circuit 21. And the positive representing the subtraction result C,
Alternatively, the most significant bit of negative data is supplied to one input terminal of the exclusive OR circuit 29. The other input terminal of this exclusive OR circuit 29 is supplied with a clock S3. Therefore, the polarity of the clock S3, which is used as a control signal for the switch swl via the exclusive OR circuit 29, is controlled by the output from the subtracter 28. Subtractor 28
If baa is positive, outputs MSB-0, and if baa is negative, outputs MSB-1. This means that whether the phase difference between the sampling phase and the input data (burst signal) is -90° to +90° or 9011 to 2
70' is determined. and,
If the phase difference is between 90'' and 270', the phase of the clock s3 is inverted and supplied as a control signal for the switch swl.

As a result, as shown in Figure 3, the phase difference between the sampling phase and the input data (burst signal) is 90'' to 270°.
Even with a phase difference of , the convergence direction of the synchronous loop is 90°
The direction is the same as when the phase difference is ~+90°, and the convergence time is shortened. If the convergence time is delayed as in the conventional case, the screen will be disturbed during that time, but by applying the present invention, the screen will not be disturbed.

In the above explanation, it was explained as a detection circuit that detects the phase error between the color burst signal and the internal clock.
Any system for obtaining phase synchronization between a periodically arriving reference signal and an internal clock can be employed not only in color signal processing systems but also in various other systems.

[Effects of the Invention] As described above, the present invention can provide a phase detection circuit that can shorten the time required for convergence for phase locking.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a timing chart shown to explain the operation of the circuit shown in Fig. 1, and Fig. 3 shows a phase diagram using the circuit shown in Fig. 1. An explanatory diagram showing the phase synchronization convergence direction of the lock loop, FIG. 4 is a diagram showing a conventional phase detection circuit, FIG. 5 is a timing chart for explaining the operation of the circuit in FIG. 4, and FIG. FIG. 2 is an explanatory diagram showing the direction of phase lock convergence of a phase lock loop using the circuit shown in the figure. 12.16.17.21.22.24.26.27...
・Latch circuit, 13.23... Inverter, 14...
- Adder, 15... Saturation circuit, 25... AND circuit, 28... Subtractor, 29... Exclusive OR circuit. Applicant's agent Patent attorney Takehiko Sae Li Zahan Figure 3

Claims (1)

[Claims] Sampling means for sampling a reference signal obtained by digitizing an alternating current signal arriving at a predetermined arrival period with a sampling pulse having a frequency twice that of the alternating signal, and a polarity inverted output of the sampling means. a switch means for selecting a signal or a non-inverting signal according to a control signal and supplying the selected pulse to an integrating circuit operating at the same frequency as the sampling pulse; In the phase detection circuit comprising latch means for latching, the control signal generating means for controlling the selection operation of the switching means is an exclusive type in which a switching pulse having the same frequency as the sampling pulse is supplied to one input. The OR circuit and the upper few bits of the reference signal are input,
This data is sampled twice in one cycle of the reference signal,
Comparison phase adjustment that performs subtraction processing on sample data and supplies the most significant bit of the result to the other input of the exclusive OR circuit to control the phase of the control signal output from the exclusive OR circuit. A phase detection circuit characterized by comprising means.