JPS63178622A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To instantly obtain a desired output signal being a digitally converted analog input signal by sequentially switching plural analog signals to supply to an analog-digital conversion circuit, and storing its output signal at each corresponding analog signal. CONSTITUTION:A multiplexer 12 connects input lines l1-ln to an input line 15 of an analog-digital conversion circuit 14 sequentially based on a switching control signal from a switching controller 13. An output line 16 of the analog- digital conversion circuit 14 is connected sequentially to plural registers M1-Mn corresponding individually to the input lines l1-ln by the multiplexer 17 based on a control signal from the switching controller 13. The converted digital signal is stored in the register corresponding to each analog signal and the desired output signal being a digitally converted analog input signal is read out by selecting the storage content and reading it.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an analog/digital conversion device, and more specifically, it is suitable for use in, for example, a control device for an internal combustion engine of an automobile, and is used for detecting cooling water temperature, battery voltage, etc. Analog/digital conversion 1Icr! is interposed between the device and a processing circuit that processes the data detected by these devices, and converts the detected analog data into digital data and provides it to the processing device. Regarding 1.

BACKGROUND OF THE INVENTION A typical prior art analog-to-digital converter W11 is shown in FIG. In this analog/digital converter 1, in order to efficiently use the analog/dental converter 2, analog data from a plurality of input lines L1 to Ln is switched by a multiplexer 3, and from any one line. The analog data was fed to the analog/log/deftal converter 2 for conversion.

Problems to be Solved by the Invention Such prior art analog/digital converter f2f
In fil, the multiplexer 3 connects the desired input lines L1 to Ln to the analog/digital converter 2, performs digital conversion, and reads the data, so the digital data of the desired input lines L1 to Ln is could not be obtained immediately. Furthermore, if analog/digital conversion is performed by sequentially switching all the input lines L1 to Ln at the same cycle using the multiplexer 3, it is difficult to perform analog/digital conversion by passing the data from each line L1 to Ln once. This requires a long time, and therefore it is necessary to take measures such as shortening the switching cycle of the line multiplexer 3, which requires data frequently.

An object of the present invention is to provide an analog/digital conversion device that can instantly obtain a digitally converted output signal of a desired signal from a plurality of analog input signals.

Means for Solving the Problems The present invention provides an analog/digital conversion circuit, a multiplexer that sequentially switches a plurality of analog signals and supplies the analog/digital conversion circuit to the analog/digital conversion circuit, and an output signal of the analog/digital conversion circuit. This is an analog/digital conversion device characterized in that it includes a plurality of registers for storing each corresponding analog signal, and means for selecting and reading out the stored contents of the 1tif register.

Operation According to the present invention, a plurality of analog input signals are sequentially switched by a multiplexer and provided to an analog/digital conversion circuit. The output signals digitally converted by the analog/digital conversion circuit are stored in a plurality of registers corresponding to each analog input signal.

Therefore, by selectively reading out the stored contents of the register, it is possible to immediately obtain the digitally converted output signal of the desired analog input signal.

Embodiment FIG. 1 is a block diagram of an analog/digital converter 11 according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the basic configuration of the analog/digital converter 11 shown in FIG. 1. It is. Refer to Figure 2, multiple input lines! 1~! Analog data A1 to An are respectively led from 11 and applied to a multiplexer 12.

The multiplexer 12 selects the input line ! based on the switching control signal from the switching control device 13. 1~! +1 are sequentially connected to the input line 15 of the analog/digital conversion circuit 14. Based on the control signal from the switching control device 13, the output line 16 of the analog/digital conversion circuit 14
Each input line by multiplexer 17! 1 to ln are sequentially connected to a plurality of registers M1 to M++ individually corresponding to each other.

In this way, the plurality of analog data A1 to AI+ are
The digital data D1 to Dn are sequentially converted and stored in corresponding registers M1 to Mn. Digital data D1~ stored in registers M1~Mn
Dn is, when the switching operation of the multiplexer 17 completes one cycle,
Updated with new data. This Denotal Data D1~
The D port is read out via the output register 18 as required.

Next, the configuration and operation of each part will be described in detail with reference to FIGS. 1 and 3. A plurality of analog data A1 to A n are applied to the multiplexer 12 via the input terminals 1 to 1. Based on the switching control signal from the switching controller 21 via one line, the multiplexer 12
Line No. 11 Analog/digital conversion circuit 1
4 input lines 15 in sequence.

The switching controller 21 generates a switching control signal for the multiplexer 12, which will be described later, and an analog/digital conversion signal as shown in FIG. 3(2), based on a clock pulse from the clock generation circuit 22 shown in FIG. 3(1). The trigger pulse from the input data of register M1 shown in Figure 13 (3) to Gl to the input data of register M n shown in Figure 13 (4) is generated. The pulse circulates until the needle is generated. Trigger pulses to input data) Gl to Gn are generated only while the clock pulses are at high level. The switching controller 21 and the clock generation circuit 22 constitute a switching control device 13.

The analog/digital conversion circuit 14 is a so-called successive approximation type analog/digital conversion circuit.

The analog/digital conversion circuit 14 includes a comparator 23, a digital/analog converter 24, a successive approximation register 25, and a reference voltage generation circuit 26. Input line 15 is connected to one input terminal of comparator 23, and the output of comparator 23 is applied via line 27 to successive approximation register 25.

The successive approximation register 25 provides a parallel signal to the digital/analog converter 24 via the line 28 when the analog/digital conversion start pulse from the switching controller 21 described above is inputted via the fin 20 . The digital/analog converter 24 converts the digital signal from the successive approximation register 25 into an analog voltage level based on the input voltage from the reference voltage generation circuit 26, and supplies the analog voltage level to the other input of the comparator 23 via line 29. Give it to the terminal.

Comparator 23 delivers a high output on line 27 when input line 15 is equal to or higher than line 29, and outputs a high output on line 27 when input line 15 is lower than line 29. Derive low level output.

The output of the comparator 23 input to the successive approximation register 25 is converted into a serial bit signal shown in FIG. 1~. Register M corresponding to each f11 individually
1 to Mn. Thus, in this example,
Switching of the registers M1 to Mn is performed by addressing the registers M1 to Mn instead of the multiplexer 17 shown in FIG. The registers M1 to Mn are provided with input data G1 to Gn, respectively, and the input data G1 to Gn are connected to the input data G1 to Gn via lines E1 to En as shown in FIGS. 3(3) and 3(4). Every time the trigger pulse shown from the switching controller 21 is input, the stored contents of the registers M1 to Mn are updated to new data.

Registers M1 to Mn have output dates OC1 to O, respectively.
Cn is provided, and when a pulse is input to these output data (OC1 to OCn) from the input register 30 as shown in FIG. The contents of the output register 18 are read out from the output register 18 via the data bus B2 as shown in FIG. 3(7).

The input register 30 receives the addresses of the registers M1 to Mn whose stored contents are to be output via the data bus B3, and inputs the output data (OCI to OCn) of the registers M1 to Mn corresponding to this address. The trigger pulse for the read instruction described above is derived. The data read timing of input register 30 and output register 18 is controlled by read control circuit 31.

The read control circuit 31 is supplied with clock pulses from the clock generation circuit 22, and also receives a signal requesting data read through a line 32. As a result, the read control circuit 31 derives a read instruction pulse from the input register 30 while the clock pulse is at a low level.

Therefore, a trigger pulse for a read instruction is not derived from the input register 30 during writing to the registers M1 to Mn.

FIG. 4 is a block diagram showing a specific configuration of a start pulse generation portion for analog/digital conversion in the switching controller 21 shown in FIG. ff11. Here, the analog/digital conversion circuit 14 converts the analog data A1 to A
It is assumed that n is converted into an 8-bit digital data string as shown in FIG. 3(5). Also, a start bit and an end bit are provided before and after the converted data string, so when 10 clock pulses are derived from the clock generation circuit 22, one analog data, for example A1, becomes digital data D1. It is converted and stored in register M1. Therefore, when nine clock pulses are input, the analog/digital conversion start pulse generation part of the switching controller 21 starts the analog/digital conversion for one cycle of the clock pulse as shown in FA3 diagram (2). The multiplexer 12
For example, 10 7-lips 70
It is composed of knobs F1 to FIO.

A high-level input is always applied to one input terminal P1 of the 7-rip 70-tube F1, and the output terminal Q1 derives a low-level output. When a clock pulse is input from the other input terminal CLK, the switching mode changes and the output terminal Q1 outputs a high level output.

One input terminal P2 of the 7-rip 70-tube F2 is connected to the output terminal Q1 of the 7-rip 70-tube F1, and a clock pulse is input to the other input terminal CLK.

The input/output terminals P3 to PIO, CLK, and Q3 to Q9 of the remaining 7 lips and 70 tubes F3 to FIO are similarly connected. The output from the output terminal QIO of the 7-lip 70-tub FIO is commonly given to the clear terminal CLR of each of the 7-lip props F1 to FIO. The output from the output terminal Q9 of the 7-rip 70-tube F9 is also provided to the analog/digital conversion circuit 14 via line 20.

In the start pulse generation part of the analog/digital conversion configured in this way, at time t1, the clock shown in FIG. 3 (1) and FIG. Pulse CLK is input, and from the output terminal 7-Ql of this 7-lip 70-tube F1 as shown in FIG.
When the high level output shown in 2) is derived, the 7-lip prop F2 derives the high level output shown in FIG. 5(3) at time t2 when the next clock pulse CLK is input manually.

In this way, the 7-lip 70-tube Fl'''F8 sequentially derives a high-level output, and when the tarok pulse CLK is input to the 7-lip 70-tube F9 at time [3], the 7-lip 70-tube Fl'''F8 outputs a high level output. A high level output shown in FIG. 5 (4) is derived from the output terminal Q9, and this output is sent to the analog signal via line 20 as the start pulse STA for analog/digital conversion shown in FIG. 3 (2). /successive approximation star 25 of digital conversion circuit 14
given to.

Also, this output is the input terminal T- of the 7-lip 70-tube F10.
When the clock pulse CLK is input at time L4, a high level output shown in FIG. Clear terminal CL of
Commonly input to R, 7 ribs 70 tubes F1 to FIO
will be reset.

tp and a are block diagrams showing the specific structure of the upper part of the switching control Hffff of the multiplexer 12 in the switching controller 21 shown in FIG. Here, 1&n of input analog data is assumed to be 8. When the analog/digital conversion start pulse STA shown in the above-mentioned Pt53 diagram (2) is input to the pinary counter 35, a 4-bit signal is derived from the output terminals Qa-Qdh. The output terminal Qd is connected to the clear terminal CLR, and when a high level output is derived from the output terminal Qd, the binary counter 35 is reset. Therefore, 3 bits, ie, 8 types of signals are derived from the output terminals Qα to Qc and applied to input terminals A to C of the decoder 3G.

The decoder 3G sequentially derives pulses from the eight output terminals N1 to N8 corresponding to the input 3-bit signal, and outputs the pulses to the multiplexer 12 and the IAND data) R1-1.
Give to 18. Each AND date R1 to R8 includes a clock pulse CLK shown in f:tS3 figure (1) and figure 7 (1), and an analog/digital conversion shown in figure 3 (2) and figure 7 (2), respectively. 1111 start pulse S
TA is given. Therefore, the high level pulses shown in FIG. 7(3) and FIG. 7(4) are sequentially derived from the decoder 36 one line at a time, and the multiplexer 12 is switched. AND day) R1 to R8 are input with the high level output of the decoder 3G or C], and by inputting the clock pulse CLKB and the analog/tenotatal conversion start pulse STA, the renostars M1 to Mn are input. Input data) Gl to G8 in Figure 3 (3)
and the bird shown in f53 diagram (4) derives the pulse.

FIG. 8 is a block diagram of the read control circuit 31. The read control circuit 31 is composed of two 7-lip 70-tubes Fil and F12 and an inversion buffer 37.
The input terminal T11 of the tube Fil is connected via the line 32.
A read request signal READ shown in FIG. 3(8) is applied. When the low-level read request signal READ is input to the input terminal Tll of the 7-lip 70-tube Fll, a high-level output is derived from the output terminal Q to the input terminal P12 of the 7-lip 70-tube F12.

A clock pulse (CLK) is applied to the input terminal T12 of the 7-rip 70-tube F12 via an inverting buffer 37. Therefore, the 7-rip 70-tube F12 is
When the clock pulse CLK is at low level with the read request signal READ being input to the 0 block FIL, the output data of the registers M1 to Mn is output from the output terminal Q.
The read instruction trigger shown in FIG. 3 (6) gives a pulse to CI to OCn. This allows the corresponding register M
1 to M+1 through the output register 18 in FIG.
), digital data D1 to Dn are read out.

The output of the 7-lip 7a-tube F12 is also input to the clear terminal CLH of the 7-lip 70-tub Fil, and therefore the output terminal Q of the 7-lip 70-tub F12 is input to the input register 30.
At the same time, 7 lips and 70 tubes Fi are derived.
l is reset.

In this way, in the analog/digital converter 11, the input line! 1-L Ahelog datum 1-811 from n
goes up to the multiplexer 12 and is sequentially applied to the analog/digital conversion circuit 14 to convert the digital data D1 to
D Converted to n, input Ka line! 1~! It is stored in registers M1 to Mn that correspond individually to each summer.
The data D1 to Dn are updated sequentially. Therefore, in the input register 30, the desired renostars M1 to M
In addition to specifying the address of the output register 1
The digital data D1 to Dn can be immediately read out from the analog/digital conversion circuit 14, and the analog/digital conversion circuit 14 can be used efficiently.

FIG. fi9 is a block diagram of a microcomputer application device 41 according to another embodiment of the present invention. As is clear from the embodiment shown in FIG. 1, the analog/digital converter 11 of the present invention can immediately read desired data by specifying the seven addresses of registers M1 to Mn. . Therefore, the present analog/digital converter 11 can be connected to the microcomputer 44 in the microcomputer application device 41 via the address bus B4 and the data bus B5, as well as the external memories 42, 43. Analog/digital converter 1
An analog input ink 7/8 46 is provided in connection with the ink 7/8 46, and a plurality of analog input signals a1 to all are applied to the analog input ink 7/8 46. External memory 42.43 and analog/digital converter jllll
The data stored in the address decoder 45 is read out to the processing circuit 44 in response to a read request signal from the address decoder 45.

In connection with the microcomputer 44, there is a digital signal human power interface 7/8 47 and a control signal output interface 7/8 48.
and are provided, each with a Denotal Iko number.
and a control signal output line B7 to the microcomputer 44.

Digital input signals d1 to -1 are given to the digital signal input ink 7 and eighth 47, and the control signal output ink 7
Control l signals OUT 1 to 0UTk are derived from the ace 48 .

This allows analog/digital conversion schedules, that is, procedures such as setting the order and cycle of conversion for multiple inputs, specifying input lines, instructing the start of conversion, and reading old and data until the end of conversion. is no longer necessary, conversion data can be easily obtained by reading out external memory, and processing procedures can be significantly reduced.

In the above embodiment, the analog/digital conversion circuit 14 uses a successive approximation type, but in other embodiments of the present invention, an integral type, parallel comparison type, etc. may be used.

Also the switching control output of multiplexer 12 via line 19 and registers M1-M via data bus B2.
Although the output of n data is performed using parallel signals, it may be performed using serial signals as yet another embodiment of the present invention.

Effects As described above, according to the present invention, a plurality of analog input signals are sequentially switched by a multiplexer and converted into digital signals by an analog/digital conversion circuit. The converted digital signals are stored in registers corresponding to each analog input signal, and by selecting and reading out the stored contents, the digitally converted output signal of the desired analog input signal can be read out. Can be done.

Therefore, the analog/digital conversion circuit can be used efficiently, and an output signal obtained by digitally converting a desired analog input signal can be obtained immediately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an analog/digital converter 11 according to an embodiment of the present invention, FIG. 2 is a block diagram showing the basic configuration of the analog/digital converter 11 shown in FIG. 1, and FIG. 1 is a timing chart for explaining the operation of each part in FIG. 1, and FIG. 4 is a block diagram showing the specific configuration of the start pulse generation part for analog/digital conversion in the switching controller 21. FIG. 55 is a waveform diagram for explaining the operation of the switching controller 21 shown in FIG. , Figure 7 is P
T! , FIG. 6 is a waveform diagram for explaining the operation of the switching controller 21 shown in FIG. 6, FIG. 8 is a block diagram showing a specific configuration of the readout control circuit 31, and FIG. Block Diagram FIG. 10 is a block diagram of a prior art analog/digital conversion device 1. DESCRIPTION OF SYMBOLS 11... Analog/digital conversion device, 12... Multiplexer, 13... Switching control device, 14... Analog/digital conversion circuit, ]7... Multiplexer, 18... Output register, 21... ...Switching controller, 2
2... Clock generation circuit, 23... Comparator, 24.
...Digital/analog converter, 25...Successive approximation register, 26...Basic voltage generation circuit, 30...Input voltage converter, 31...Reading control circuit, 35...Binary counter, 36... Decoder, 37... Inverting buffer, 41... Microcomputer application device, 42
．． 43...External memory, 44...Microcomputer, 45...Address decoding, 46...Analog human power interface 78, 47...Denotal signal input interface 78, 48...Control signal output Inter 7 Eighth, M1-Mn...Register Agent Patent Attorney Number of Strokes Keiichi Figure 5 Figure 6

Claims (1)

[Claims] An analog/digital conversion circuit, which sequentially switches a plurality of analog signals to convert the analog/digital
A multiplexer to be applied to the digital conversion circuit, a plurality of registers that store output signals of the analog/digital conversion circuit for each corresponding analog signal, and means for selecting and reading out the stored contents of the registers. Characteristic analog/digital conversion device.