JPS63177245A - Control equipment for high-speed data transfer - Google Patents

Abstract

PURPOSE:To transfer data at a high speed by using channel information to decide a transfer route between modules on a common bus, using the time slot information to set transfer timing and giving time division control to the common bus for transmission/reception of data on each module. CONSTITUTION:When pictures are transmitted and received, a clock control part 17 of a bus control part 2 produces a timing clock common to each module. At the same time, a channel information generating part 18 outputs the channel information, the module numbers and a channel information deciding signal. A module number comparator 6 in a channel information detecting part 4 compares the address given from a proper address generating circuit 5 with the module number on an address line 3 and outputs a channel information latch pulse 9 when the coincidence is obtained between them. A time slot information generating part 19 of a control part 2 outputs the slot information and a deciding signal and then a coincidence pulse 14 via a channel information comparator 12 of a time information detecting part 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high-speed data transfer control device used in an image processing device such as a facsimile machine.

Conventional technology Conventionally, in image processing devices such as facsimiles,
When transferring data such as image signals between modules such as the image reading control section, image data compression/expansion section, and recording control section, it is necessary to provide a dedicated multiplex bus between each module, or use a general-purpose bus such as a multipath bus. A common bus is provided.

When using the former dedicated multiplexed bus, data can be transferred at the maximum transfer rate of each dedicated bus without being affected by other transfer channels, and
When using the latter common bus, the bus control unit controls the bus and adjusts the right to use the bus according to transfer requests from each module, allowing a large amount of data to be sent via the same bus. Can be transferred.

Problems to be Solved by the Invention However, when using the former dedicated multiplex bus, data can be transferred at high speed, but it is difficult to change the transfer route, and therefore, the versatility is limited. The problem is that it lacks.

On the other hand, when the latter common bus is used, it is necessary to request the bus control unit for the right to use the common bus before data transfer. In order to prevent exclusive use of the common bus for a long time, the right to use is requested for each word.

Therefore, when a channel with a very high transfer rate, such as an image signal, monopolizes a common bus, the time required to arbitrate the bus increases depending on the frequency of data transfer, and the efficiency of the common bus decreases significantly. There is a problem that data cannot be transferred at high speed.

Another problem is that a channel with a low transfer rate and low priority is not given the right to use the bus, making it impossible to obtain a predetermined processing capacity.

In view of the above problems, an object of the present invention is to provide a high-speed data transfer control device that can transfer data at high speed via a common bus and can change the transfer route between each module. No.

Means for Solving the Problems In order to solve the above problems, the present invention determines the transfer route between each module on a common bus based on channel information, and determines the transfer timing of each transfer route based on time slot information. The present invention is characterized in that each module is configured to transmit and receive data by time-divisionally controlling the common bus. Because the route can be easily changed and the time slot information can reduce the unused time of the bus that would otherwise be spent on traditional bus arbitration,
Data can be transferred at high speed.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram schematically showing the overall configuration of a data transfer system according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a high-speed data transfer control device incorporated in the system of FIG. FIG. 3 is a timing chart showing signals on the common bus of FIG. 2.

First, the overall configuration of the high-speed data transfer control device according to the present invention will be explained with reference to FIG. 1.
A plurality of modules 1-1 to 1-n that transmit and receive data such as an image data compression/expansion section and a recording control section are connected to a common bus 3.
It is connected to the bus control unit 2 via.

In FIG. 2, the bus control unit 2 includes each module 1-1.
A clock control unit 17 that generates a common timing clock for modules 1-1 to 1-n, channel information that determines each transfer route between modules 1-1 to 1-n, and each module 1-1.
A channel information generating unit 18 that generates a module number for writing the channel information in each of the modules 1-1 to 1-H, and a channel information determination signal for causing each module 1-1 to 1-H to determine the respective channel information. and time slot information for determining the transfer timing of each transfer' route between the modules 1-1 to 1-n, and a time slot information determination signal for causing each module 1-1 to in to determine the respective transfer timing. The time slot information generating section 19 is configured to generate multiple timeslot information.

The channel information includes information indicating the direction of transmission and reception;
The time slot information includes the channel number of the transfer route indicating the logical channel of the transmitting/receiving module, and the time slot information includes the channel number of each transfer route between the modules 1-1 to 1-n.

The common bus 3 carries the channel information and each module 1.
A data line 3-1 through which data between -1 and in flows under time division control, an address line 3-2 through which the module number and the time slot information flow, and a line 3-3 through which the time slot information determination signal flows. , a line 3-4 through which the channel information determination signal flows, and a line 3-5 through which the timing clock flows.

Each module 1-k (k=1 to n) includes a channel information detection section 4, a time slot information detection section 11, a transmission buffer 15 that temporarily stores data to be transmitted to the reception side module, and a transmission side module. The general configuration includes a reception buffer 16 that temporarily stores received data.

The channel information detection section 4 includes a unique address generation section 5 that generates a module number that is a unique address for each module 1-, and an address from the unique address generation section 5 and the module number on the address line 3-2. A module number comparison circuit 6 outputs a channel information latch pulse 9 when they match, and a latch circuit 7 latches the channel information 8 sent via the data line 3-1 with the channel information latch pulse 9. is configured.

The time slot information detection unit 11 compares the channel number of the channel information 10 from the channel information latch circuit 7 with the channel number of the time slot information sent via the address line 3-2, and extracts the time slot when they match. It consists of a channel information comparison circuit 12 that outputs a pulse 14, and a time slot control circuit 13 that controls the transmission and reception of data based on the time slot extraction pulse 14 from the channel information comparison circuit 12.

Next, the operation of the embodiment according to the above configuration will be explained with reference to FIG.

The clock control section 17 of the bus control section 2 outputs a timing clock common to each module to the clock line 3-5, and each module 1- operates in synchronization with this clock.

When this device transmits or receives an image, the channel information emitting unit 18 of the bus control unit 2 sequentially outputs channel information to the data line 3-1 prior to data transfer of 'M to each module 1-, and The module number of the same value as the unique address of each module 1- is sequentially input to the address line 3-.
2, and furthermore, the channel information determination signal is sequentially output to line 3.
-4 In each module 1-k, the module number comparison circuit 6 of the channel information detection section 4 outputs the output from the unique address generation section 5 in synchronization with the channel information determination signal on the line 3-4. The address and the module number on the address line 3-2 are compared, and when they match, the channel information latch pulse 9 is output.
By latching the channel information sent out via channel information latch pulse 9 with channel information latch pulse 9, the transfer route between each transmitting/receiving module is determined.

Next, the time slot information generation section 19 of the bus control section 2
outputs the time slot information to the address line 3-2 and outputs the time slot information determination signal to the line 3-3, and in each module 1-k, the channel information comparison circuit 12 of the time slot information detection unit 11 but,
Channel information 10 from latch circuit 7 and address line 3- are synchronized with the time slot information determination signal on line 3-3.
The time slot information on 2 is compared, and if they match, a time slot extraction pulse 14 is output.

Therefore, the time slot control circuit 13 is activated by the time slot extraction pulse 14, and the transmitting and receiving side modules transmit and receive data via the transmit buffer 15 and the receive buffer 16, respectively. Note that the time slot information on the address line 3-2 is switched sequentially, and data is transferred in a time-division manner over a large number of transfer routes.

As explained above, according to the embodiment, the data line 3
-1 is controlled in a time-division manner, data can be transferred at high speed via the data line 3-1, and the transfer route can be changed.Next, Figures 4 to 7 A second embodiment of the present invention will be described with reference to the drawings. In these drawings, the same reference numerals are given to the same constituent members as those explained in the previous embodiment.

In FIG. 4, the bus control section includes a lock control section 17 and a channel information generation section 18, as in FIG.
Furthermore, it has a central processing unit (CPU) 21 and a time slot information generation section n.

As shown in FIG. 7, the time slot information generation unit includes a time slot memory 22a that stores channel numbers according to the frequency of use of each transfer route, and a memory address counter 2 for accessing data in this memory 22a.
2b, and a cycle controller 22c that determines the cycle so that the time slot information is repeated at a predetermined cycle.

When this device transmits or receives images, a predetermined channel number corresponding to the frequency of use of each transfer channel is stored in the time slot memory 22a before data transfer. That is, more frequently used channel numbers of the data line 3-1 are stored, and fewer frequently used channel numbers are stored.

Further, the total number of channel numbers stored in the time slot memory 22a is set in the period counter 22C.

Next, the operation of the embodiment will be explained with reference to FIGS. 5 to 7. Note that when determining the transfer route between each module based on the channel information, the same operation as in the previous embodiment is performed, so the explanation thereof will be omitted.
When the above data is set in 2a etc., the path control unit (9)
5, the memory address counter 22b of the time slot memory 22a counts sequentially, and as shown in FIG.
A time slot discrimination signal is output from the line 3-3 to the line 3-3.

Therefore, in order to perform transmission and reception at the frequency of use of the set common path for each module 1-, as shown in Figure 6, the transfer route set with a large number of channels is used more frequently, and each channel The frequency of use of the data line 3-1 can be set arbitrarily.

As described in detail, the present invention determines the transfer route between each module using channel information, sets the transfer timing of each transfer route using time slot information, and allows each module to time-share a common bus. Since it is configured to control data transmission and reception, the transfer route between each module can be easily changed, and time slot information can reduce the unused time of the path that would be spent in conventional path arbitration. Because of this, data can be transferred at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the overall configuration of a data transfer system to which the present invention is applied, and FIG. 2 is a block diagram showing an embodiment of a high-speed data transfer control device incorporated in the system of FIG. FIG. 3 is a timing chart showing the signals of the common bus in FIG. 2, FIG. 4 is a block diagram showing a second embodiment of the high-speed data transfer control device according to the present invention, and FIG. FIG. 4 is a timing chart showing the signals of the common bus, FIG. 6 is an explanatory diagram showing the frequency of use of the common bus, and FIG. 7 is an explanatory diagram of the contents stored in the time slot memory of FIG. 4. 1-1 to 1-n...Module, 2.Redundant...Path control unit, 3...Common bus, 4...Channel information detection unit, 11...Time slot information detection unit, 18.・・・
Channel information generation section, 19.22...Time slot information generation section. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure 3 3-5 JIfL---- Figure 4

Claims (2)

[Claims] (1) A common bus for transferring data by time-sharing control, a plurality of modules that transmit and receive data via the common bus, and means for generating channel information for determining a transfer route between the modules. , and a bus control unit having means for generating time slot information indicating transfer timing of each of the transfer routes, and each of the modules detects channel information from the bus control unit and stores the transfer route. and a means for detecting time slot information, and when the time slot information is detected, time-sharing control is performed on a common bus according to each transfer route to transmit and receive data. Transfer control device. (2) Claim 1, further comprising a bus control unit that generates time slot information indicating the transfer timing of each transfer route according to the usage frequency of the common bus for each transfer route set in advance. The high speed data transfer control device described.