JPS63175519A - Output circuit - Google Patents

Abstract

PURPOSE:To obtain an output circuit whose output level is matched accurately to an ECL (Emitter Coupled Logic) level by using a sensor block so as to sense the dispersion of the characteristic of transistors (TRs) and varying a gate potential so as to absorb the variance of TRs. CONSTITUTION:A TR 10 is a TR of the same kind of an output TR 3 and the variance in the characteristic of FET has a large correlation because the FET is arranged near the pattern. Thus, if the FET threshold value of the TR 3 varies, the current capability of the FET is increased and its output voltage is going to rise, then the current capability of the TR 10 is increased. Since the current flowing to a resistor 9 is increased, the gate potential results in falling down thereby compensating the rise in the output voltage finally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) This invention relates to an output circuit of an integrated circuit using F g T.

(Prior Art) Conventionally, ECL (EmitlerCou) is an integrated circuit format used in fields that require high floor space.
(pled Logic). As is well known, ECL uses TTL (Transistor-Tr) to operate bipolar transistors in non-saturation.
ansistQtLogic) fL How does the overflow of minority carriers occur?

Therefore, high-speed operation is possible at 0T. But non-saturating operation?
Since the logic amplitude is limited in order to achieve this, its amplitude is small compared to other logics.

NJ, tBA TTL+4 approx. 2V; 0MO8 is 5V [j
L.

gCLiO, 8V. CI7) Tame E CL
In order to connect ICs, it is necessary to match the logic levels, and the logic amplitude and logic threshold are strictly determined. Recently, integrated circuits using GaAsi field effect transistors (FETs) have been attracting attention because of their high speed performance.

In system construction, the ultra-high-speed part uses 0aAsIe,
It is desirable to configure the high-speed portion with BCL and the low-speed portion with 0MO8 from the viewpoint of cost, consumption, etc.

For this reason, the output circuit of ()aAsIc is at the BCL logic level? It has to be satisfying. However, the conventional G
The aAsIC output heating was insufficient to satisfy the above conditions.

Is there a drawing below? The conventional technology will be explained using the following.

Figure 2 shows S using G a A s F B T fc.
CF L (5ourccCoupled FET
This is the output circuit of a circuit called Logic.

In the figure, 1.2 is a differential transistor, and 3 is an output transistor that can flow multi-order currents.

R, L, 1. RL2 is load resistance %RTI is transistor 3? Gate and drain voltage to operate with saturation characteristics? It is a resistance to secure.

I, , I, is a constant d current source. Outlet pressure V out
Since the 'zECL level is set, the gate position of transistor 3 is designed as follows.

Here ■ oH = 10.8v, vOL - geh of 18■
level.

vGS (VG when designed as l:OV)1. VGL remains as it is -o, sv, -1,8V. F
ET's! Pressure.

The current characteristics are expressed by the following equation.

I, = K, (VGS-VTH)z Here, K is a parameter indicating the current capacity of the FET, and is %
V T HFiF gT threshold A1 straight is shown. Here ■
, is a current source (usually a resistor) connected outside the IC that is set to make VG8 zero.

Now, if K or V'I'H, which is a parameter of PET, varies from the design value, (2) does not change, so the change will be absorbed by vGs.

As is clear from equation (1), since GHyGL does not change, the VOH and VOL k settings are shifted by -51.

For example, if the VTR changes by +20, VGS changes from the design value of OV to -20 of VTH. If the VTR is -0, 5V, V will be 1 OLIV from OV, and VV OH (JL will be -0, 8V respectively -o, 7V,
-1.8V;6>ra -1,7V and ff1Z and go L.

Variations in VTH of about 20 factors must be taken into consideration in the current process, and fluctuations in output power cannot be avoided.

The output amplitude is made larger than the ECL level.
It seems to be fine as long as the level is satisfied even if there is some variation, but it is not preferable to set the amplitude too large because this will result in a decrease in speed.

On the other hand, the case of gcL is shown in FIG. In the figure, 4.5 is a differential transistor, and 6 is an output transistor. As is well understood, the undercurrent-4 pressure characteristics of bipolar electrons are expressed by the following equation.

Here, Is is the saturated current, q is the electron, charge, K is Holtzmann's constant, and T is the ambient temperature. As is clear from the above equation &i! In order to keep Ii constant even if the direct current varies, ■BF and the ladder make only a small number of changes.

For example, V13E is 4.7 m even if Is increases by 20%.
V decrease (VBg is 800mV, fc, QC-0,6
%) f only. Therefore, changes in output voltage due to variations in transistor parameters: A little consideration, 1
There's no need to do it.

(While the invention is trying to solve it: troublesome) GaAs IC: In order to connect with gcLIc, the output 'tat3ji level should be the ECL logic level.
I need to add it.

However, in the conventional circuit, the design center
Even if it is possible to satisfy the ld condition, it is not sufficient to satisfy the ld condition when the four FETs vary.

The object of the present invention is to provide a means by which the ECL logic level can be satisfied even if the characteristics of the elements vary.

[Structure of the invention]

(Means for solving all the problems) Fig. 1 shows the gist of the invention for solving the above problems by using 8 in the output circuit of FBTo Jikuku? FIG. 2 is a block diagram of a circuit. Name in the figure Is the number that indicates the same configuration as in Figure 2 the same number? It's a dike. 7 is a sensor block for sensing variations in the FET characteristics of the output transistor; 8 is a control block that receives the signal from 7 and outputs a control signal;
9 receives on the control signal R, l, 1. The potential of the junction point of L2 (resultingly, the gate potential of 6 vGH, vG
This is a block for changing L).

(Function) According to such a configuration, the sensor block 7 senses the variation in the characteristics of the transistor 6, and the fresh water is converted into a control signal in the control section 8 and is outputted to V via the zero position change block 9.
Change B2. Since the change in VR is also due to the change in VG, the fluctuation of the transistor 6 is absorbed, and this system operates so that the output voltage V out does not change.

(Example) FIG. 44 shows an embodiment of the present invention.

The difference from the conventional example shown in FIG. 2 is that the transistor 1° is placed in the υ position. Below, I will explain the actions of this episode. Transistor 1o has the same +f as output transistor 3! mFIZ is performed using a transistor with s<ion implantation process conditions are the same).

Moreover, it is known that the variations in FET properties have a large fL correlation with each other because the FETs are formed close to each other in terms of pattern arrangement.

Therefore, if the VTf of 3 varies in the deeper direction U (IVTHI→dog), the current capacity of FET increases U[] and Vo
When ut tries to rise, the current capacity of 10 FETs also increases. For this reason, the current flowing through the resistor 9 increases υ, so VR drops, and as a result, VG drops, so that the increase in Voul can be compensated for in the end by kl. In comparison with FIG. 1, the sensor block 7 and control block 8 in FIG. 1 correspond to the transistor 10 in FIG. 4, and the potential change block 9 corresponds to the resistor 9.

FIG. 5 shows another embodiment of this fan-mei. At the beginning Junmu moves 1
I will wait for a while. The operational amplifier 16 reduces the direct voltage at the terminals of the differential transistors 12, 13id and 11(J, 3) so that the north direct voltage of the transistor 11 becomes equal to Vref.This will be explained in detail below.Output transistor 3
The dummy output transistors 11 and 11 are PET transistors having the same blueness and process conditions, and are also made of PET transistors Ll, RL2 and RL3.几L
4 is the same single-direction resistor, transistors 14 and 15 are of the same shape and have the same process conditions, and I1 and I4 are cardiac current sources that flow the same @.

As is clear from the figure, 14, RL3. RL4. I.

■, and 11 constitute the output circuit.

1, 2. [(Ll, 几L2.+5.L, When the current of the differential transistor 1.2 is equal in L and 3, that is, the output level of the output transistor 3 is the same as the monitor when the logic threshold is reached.

In other words, the output voltage of the output transistor 11 accurately reflects the output voltage Vouti of the transistor 3.

FIG. 6 shows an example of the operational amplifier 16 shown in FIG.

It consists of only N channels. Peeking source Q.

Q is set to be larger than the original I6 of the formula flow 1, and the remaining four flows other than those flowing in the formula flow 1 and I6 are Dl.

Dskm and Qs and Qt pull in. One output is output from the cathode terminal of diode D.

If the gate potential of Ql rises above the 4th gate potential of Q, then I Qi > r Qt will be satisfied. But r-
Qs = I Q, or since it is a rent mirror from Q6, Q, and V, I Qa - I Qy. So △I Q= I Q
It works to flow out the current of i-dQ from the output terminal.

〔Effect of the invention〕

According to the present invention, it is possible to provide an output circuit that can accurately match the output level of the output circuit to the ECLv level even if the parameters of the elements vary.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the concept of the present invention, Figure 2 is a diagram showing the conventional output port @, and the conventional output equivalent by a bipolar transistor. The diagram shown in Figure 4 is 1.2...differential FE.
T, 3... Output FET, 7... Sensor block,
8...Control block, 9...Potential change block. Agent: Patent attorney Nori Kon, Kikuo Takehana No. 1 Figure 2 Figure + 1 Procedural amendment honor (method) % formula % 1. Case display patent application No. 1982-6133 2. Invention title output circuit 3. Relationship with the case of the person making the amendment Patent applicant (307) Toshiba Corporation 4, Agent Address: 1-1 Shibaura-chome, Minato-ku, Tokyo 105 March 31, 1985 (Delivery date) Figure 3” is corrected.

Claims (3)

[Claims] (1) A differential field effect transistor, a load resistor connected to the differential field effect transistor, a gate connected to the connection point between the load resistor and the differential field effect transistor, and a drain connected to the load resistor. is connected to a power supply and whose source is an output terminal; a sensor block that senses variations in the elements of this output terminal field-effect transistor; and a control signal generated by receiving information sensed by this sensor block. An output circuit comprising: a control block; and a potential changing block connected between each of the load resistors and a power source and changing the potential at the connection point in accordance with a control signal from the control block. (2) The potential change block is composed of a resistor, and the sensor block and control block are composed of FETs whose drain is connected to the terminal opposite to the terminal connected to the power supply of the resistor, and whose gate and source are connected to the other power supply. The output circuit according to claim 1, characterized in that: (3) The sensor block consists of a circuit obtained by removing the differential transistor from the output differential circuit, the control block consists of an operational amplifier, and the potential change block consists of a differential circuit and a plurality of FETs to which the output is transmitted,
The output circuit according to claim 1, wherein these FETs are used in both the differential output circuit and the sensor block, and have a drain connected to a power source and a source connected to each load resistor. .