JPS63131072A - Peak detection circuit - Google Patents

Abstract

PURPOSE:To suppress increase in power consumption, by providing a control means to control supply of an emitter current in a current switching means according to a peak value held with a capacitor. CONSTITUTION:For example, when a signal of 'H' level appears at an input terminal 1, a transistor (Tr) 101 is made conductive through a transistor (Tr) 2 and diodes 11 and 12. On the other hand, as a potential develops at a Tr 141 of a control means 14 corresponding to the charged state of a capacitor 6, the conduction state of a Tr 104 of a current switching means 10 is also controlled. In short, when a marking rate of an input signal appearing at an input terminal 1 drops, current flowing through the Trs 104 and 101 increase, and hence a larger emitter current is supplied to an input side Tr5. This makes the time constant in the charge of the capacitor 6 so small as to eliminate the need for lowering a holding peak value. When the marking rate of an input signal appearing at the input terminal 1 is high, the base potential of the Tr 104 lowers and current flowing through the Trs 104 and 101 also decreases or is down to zero, thereby reducing power consumption at the means 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak detection circuit for detecting the peak value of a signal, and relates to a peak detection circuit used in, for example, a high-speed repeater.

[Conventional technology]

Figures 2 and 3 are peak detection circuits shown in "High-speed Repeater Peak Detection Circuit" at the 4454 National Conference of the Institute of Electronics and Communication Engineers in 1985, respectively. In FIG. 2, (1) is an input terminal to which a signal is applied, (2) has a base connected to this input terminal, and a collector connected to the first potential point of the DC power supply (3), which is ten potentials. The emitter is resistive (
An NPN type transistor (51 has its base connected to the emitter of this transistor (2)) is connected via the DC power supply (31) to the 2'1E point which is one potential or ground potential.

The input side transistor is an emitter follower NPN type transistor whose collector is connected to the first potential point, and a potential corresponding to the potential input to the input terminal (1) is applied to the base. (6) is connected between the emitter of this input transistor and the second potential point.

The base of the capacitor (7) that holds the peak value is connected to the emitter of the input side transistor (5).

N P N of an emitter follower whose collector is connected to the first potential point, and whose emitter is connected to the M22 potential point via the resistor (8) and connected to the output end (9).
This is an output side transistor consisting of a

In the peak detection circuit configured in this way.

The peak value of the signal input to the input terminal (1) is held by the capacitor a1) and output to the output terminal (9). The capacitor (6) is charged by the current flowing through the input transistor (51) and discharged by the current flowing into the output transistor (7).At this time, the capacitor (6) is charged. The constant τC is given by the product of the emitter resistance value of the input side transistor (5) and the capacitance value C of the capacitor (6), and is expressed by a ninth-order equation.

τc=(kT/qxθ]·C where, k is Boltzmann's constant, T is absolute temperature, q is an electric element, and tI8 is the emitter current of the input side transistor (51).

However, in the steady state, the input side transistor 15
The current flowing through 1 is several μA, and the input side transistor +
Since the emitter resistance value of 51 is very large, several tens of ohms,
The charging time constant τC in the capacitor (61) has a large value.If the charging time constant τC is large in this way, especially when the mark rate of the transmission code decreases, compared to when the mark rate is high. There was a problem that the peak value to be maintained decreased.

In order to solve the above problem, FIG. 3 shows that the peak circuit shown in FIG.
A current switching means is provided which supplies an emitter current to the emitter of the input transistor when the level is 'H', and does not supply an emitter current to the emitter of the input transistor when the level is @L''v/I/.

In Figure 3, αD and α2 are diodes connected in series between the emitter of the transistor (2) and the resistor (4), and the base is at the connection point between diode 4 and the resistor (4). a first transistor whose collector is connected to the emitter of the input transistor (51);
(102) is a second transistor whose emitter is connected to the emitter of the first transistor, whose collector is connected to the first potential point, and whose base is connected to a reference potential point (13) having a predetermined potential.

(105) is a constant '* current source connected between the emitters of these first and second transistors and the 21st point,
The first and second transistors (101,) (1 hit)
This constitutes the current switching means αG.

In the peak detection circuit configured in this way.

When a @H# level signal appears at the input terminal (11), it is connected to the base of the first transistor (101) via the input terminal (
A potential corresponding to the potential f appearing in 1) appears. As a result, the first transistor (101) becomes conductive,
An emitter current is supplied to the emitter of the input transistor (51). By increasing the current value flowing through the constant current source (105J), the emitter resistance value of the input side transistor (51) can be decreased and the charging time constant τC can be decreased. appears, the first
The transistor (101) becomes non-conductive, and the emitter of the input side transistor (51) is connected to the ta switching means l1 (l
The emitter ta is supplied from the capacitor (61
is discharged by the current flowing into the output side transistor (7). In short, when each signal at the "L" level appears at the input terminal (1), it indicates a special holding operation similar to that of the peak detection circuit shown in FIG.

[Problem that the invention seeks to solve]

However, in the peak detection circuit configured as described above, the constant current source (1
03) is determined to prevent the retention peak value from decreasing even at the lowest mark rate, it is necessary to increase the ta value flowing from the constant current source (105 month), and the low mark rate. If the mark rate I is higher, an extra current flows, which inevitably increases power consumption.

This invention has been made in view of the above points, and aims to provide a peak detection circuit that does not cause a decrease in the peak value of the retainer even when the mark rate decreases, and that consumes less power as a whole. That is.

[Means for solving problems]

In the peak detection device according to the present invention, a capacitor that holds a peak value is exposed to light by ta flowing to the input transistor, and is discharged by tfL flowing to the output transistor, and the peak value held in the capacitor is output to the output end. In a device equipped with a current switching means for supplying emitter current to the emitter of the input side transistor according to the level of the input signal, the amount of emitter current supplied by the current switching means is controlled according to the peak value held in the capacitor. A control means is provided.

[Effect]

The control means in this invention changes the amount of emitter current supplied to the current switching means according to the peak value held in the capacitor. In other words, when the signal input to the input terminal is a low mark rate signal, the amount of supply from the emitter ta in the current switching means is increased to reduce the time constant during charging, thereby reducing the peak value that should be held in the capacitor. If the signal input to the input terminal is a high mark rate signal with no drop in the peak value that should be maintained at the time constant during charging, the amount of emitter current supplied by the current switching means is reduced. Reduces current consumption.

〔Example〕

An embodiment of the present invention will be described below based on FIG. 1. In FIG. 1, (10 is an input side transistor (5
), and does not supply emitter current to the emitter of the input side transistor (5) when the potential input to the input terminal (1) is at the "L# level". The base is connected to the connection point with (4), and the collector is connected to the input side transistor (51
A first transistor of NPN type (10) connected to the emitter of this first transistor (1
The first transistor (13) is connected to the emitter of the first transistor (13); a second NPN transistor (102), and these first and second transistors (101), (102)
The collector is connected to the emitter of 1JP, and the emitter is connected to a second potential point via a resistor (105), and 1JP flows at a constant value depending on the control potential applied to the base.
A third N-type transistor (composed of 10 transistors) α◆ is a control means for controlling the amount of emitter current supplied to the current switching means according to the peak value held in the capacitor (6). The base is the output side transistor (
)), and the collector is connected to the resistor (142J
A PNP-type fourth transistor (14) is connected to the base of the third transistor (14) to control the base potential.
The emitter of this fourth transistor (14) is connected to the emitter, and the collector is connected to the second potential point via a resistor (14).

The base is connected to a reference potential point α3 having a predetermined potential,
The first transistor (143J) of the PNP board constitutes a differential amplifier with the fourth transistor +14, and these fourth and fifth transistors (14).

The constant current source (145) is connected between the emitter of (143) and the first point and is constituted by, for example, a transistor.

In the peak detection circuit configured in this way.

When a signal of "H level" appears at the input terminal (1),
1) (12) Connect the input terminal (12) from the emitter of the flange resistor (2) to the outside of the diode and the base of the first transistor (101) via Kai.
A potential corresponding to the potential appearing at 11 appears. As a result, the first transistor (101J) becomes conductive. On the other hand, the base E of the fourth transistor (14J) of the control means a4 has a potential corresponding to the state of charge of the capacitor (6). The conduction state of the transistor (14) also changes depending on the charging state of the capacitor (6), and the conduction state of the third transistor (10) of the current switching means αG is also controlled.

In other words, when the charging potential of the capacitor (61) is round, the conduction state of the third transistor (10) is high, and the current flowing through this third transistor (10) is large.

Conversely, as the charge level of the capacitor (61) becomes higher, the conduction state of the third transistor (10) becomes lower, and the current flowing through this third transistor (10) becomes smaller. In addition, when the mark rate of the input signal appearing at the input terminal (1) decreases and the peak value to be held decreases, the base potential of the third transistor (10) increases and this third transistor (The current flowing in the 10th direction becomes thicker, and the first transistor (10
Since the current flowing in Since the time constant τC for charging becomes smaller, there is no need to reduce the peak value held.Also, even if the mark rate of the input signal appearing at the input terminal (1) is high and the time constant for charging is large, the peak value to be held does not decrease. If the base potential of the third transistor (100) is low, the current flowing through this third transistor (100 Since the flowing current is also small or O, the current switching means (Il
The power consumption in m can be reduced. At this time,
Although power is consumed in the control means I, since it is only used to control the base potential of the third transistor (10), only a small current needs to flow, and the power consumption is extremely small. Switching means <1
(The reduction in power consumption in I leads to a reduction in the power consumption of one circuit as a whole.

On the other hand, when an L” level signal appears at the input terminal (1),
The first transistor (101J) becomes non-conductive, and the emitter current is not supplied from the ta switching means to the emitter of the input side transistor (51).The capacitor (61 is discharged by the current flowing into the output side transistor α2). .In short, when the "" LnLn level appears at the input terminal (1), it exhibits the same retention performance as the peak detection circuit shown in FIG.

As described above, in the above-mentioned peak detection circuit, even if the input signal is a low mark rate signal, it is possible to suppress the decrease in the peak value at the capacitor (6), and also to suppress the overall power consumption. , even if the input signal is a transmission signal with a different transmission code mark rate periodically or temporally, stable signal reproduction at a constant level can be automatically performed without changing the setting of the peak time constant. It is.

〔Effect of the invention〕

This invention gt1 (As mentioned above, in a peak value detection circuit in which a capacitor that holds a peak value is charged by an input transistor and discharged by an output transistor array, the emitter of the input transistor is Since the current switching means for supplying the emitter current to the current switching means and the control means for controlling the amount of emitter current supplied by the current switching means are provided, the capacitor E can be maintained even if the mark rate of the input signal G is low. This has the effect of preventing the peak value from dropping and suppressing an increase in power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the present invention, and FIGS. 2 and 3 are diagrams showing conventional peak detection circuits, respectively. In FIG. 1, (1) is an input terminal, (5) is an input side transistor, (6) is a capacitor, and (7) is an output side transistor. (9) is the output terminal, (1G is the current switching means, (101
, 1, (102). (10 is the first, second, and third transistors, α4 is the control means, (14, I, 145) are the fourth and fifth transistors, and (145) is a constant mA source. The same reference numerals in the figures indicate the same or corresponding parts.

Claims (4)

[Claims] (1) An input side transistor in which a potential corresponding to the potential input to the input terminal is applied to the base and the collector is connected to the first potential point, the emitter of this input side transistor and the second
a capacitor connected between the first potential point and the second potential point to hold the peak value, the base of which is connected to the emitter of the input transistor, and the emitter of which is connected to the output terminal of the transistor; an output side transistor connected to the emitter of the input side transistor,
An emitter current is supplied to the emitter of the input transistor when the potential input to the input terminal is at a first level, and an emitter current is supplied to the emitter of the input transistor when the potential input to the input terminal is a second level. a peak detection circuit comprising a current switching means for controlling the current switching means, and a control means for controlling an amount of emitter current supplied in the current switching means according to a peak value held in the capacitor. (2) The current switching means includes a first transistor whose base is applied with a potential corresponding to the potential input to the input terminal, whose collector is connected to the emitter of the input transistor, and whose collector is connected to the first potential point. a second transistor whose emitter is connected to the emitter of the first transistor and whose base is connected to a reference potential point having a predetermined potential; and the emitters of the first and second transistors and the second potential point. 2. The peak detection circuit according to claim 1, further comprising a third transistor connected between the first and second transistors and whose base is controlled by the control means. (3) The control means includes a fourth transistor whose base is connected to the emitter of the output side transistor, whose collector is connected to the second potential point and to the base of the third transistor of the current switching means; a fifth transistor connected between the emitter of the fourth transistor and the second potential point, the base of which is connected to a reference potential point having a predetermined potential; and the emitters of the fourth and fifth transistors connected to the first potential point. 3. The peak detection circuit according to claim 2, further comprising a constant current source connected between the peak detection circuit and the peak detection circuit. (4) The input side and output side transistors and the first to third transistors are NPN type transistors, and the fourth and fifth transistors are PNP type transistors, Claim 3 The peak detection circuit described in section.