JPS60137109A - Differential amplifier circuit including bipolar transistor and mos transistor together - Google Patents

Abstract

PURPOSE:To reduce characteristic variation with variation in the threshold valtage of MOS transistors (TR) by providing a differential couple of bipolar TRs, a couple of MOSTRs as a load resistance and an MOSTR as a constant current source. CONSTITUTION:A differential amplifier stage consists of the differential couple 1 of bipolar TRs, the couple 4 of conductive MOSTRs as the load resistance, and the conductive MOSTR5 as the constant current source which specifies a bias current. A voltage source which biases the MOSTR5 consists of an MOSTR6 of the same conduction type with the MOSTR4 and an MOSTR7 of the same conduction type with the MOSTR5. The source and drain of the TR6 are connected to the gate of the TR5 and a power source potential Vcc respectively, and the source and drain of the TR7 are connected to the gate of the TR5 and a ground potential GND respectively. Consequently, variation of characteristics is reduced against variation in threshold voltages of the TRs 4 and 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a differential amplifier circuit, and particularly to a differential amplifier circuit in which bipolar transistors and MOS transistors are mixed.

[Background of the invention]

FIG. 1 shows a general differential amplifier circuit using bipolar transistors 1 as a differential pair. 2 is a load resistance, and 3 is a constant current source. Terminals A and B are input terminals, and C is a differential output terminal. The current Ic1+Icz flowing through the load resistor 2 can be expressed as follows.

where α: base common current amplification factor of the pievora transistor 10, llCl: current flowing through the current source 3, q: charge element, k: Boltzmann constant, T: absolute temperature, Vl: potential difference between signals input to terminals A and B. Out. At this time, Veut = 'R (let Icz) at the output terminal C..."...
...The output signal expressed by (3) is obtained.

When the above-mentioned differential amplifier is configured with a semiconductor integrated circuit,
The load resistor 2 is often replaced with a MOS transistor 4 as shown in FIG. Terminal.

E is fixed to the ground potential GND when the MOS transistor 4 is 2MO8, and to the power supply potential VCC when the MOS transistor 4 is 0MO8. MOS) transistors have a relatively small conductance gm, so they can form a load resistance in a small area.
It is advantageous in terms of integration.

Further, in an actual integrated circuit, the constant current source 3 is composed of a MOS transistor or a bibolar transistor as shown by 5 in FIG. At this time, a predetermined voltage is applied to the terminal F, and a bias current Iam flows. Here, it is assumed that the load resistance is the MOS transistor 4 of the first conductivity type.

MO'S) Since the transistor 4 operates in a non-saturated region, the on-resistance R,14 is as follows.

・・・・・・・・・(4) β04”μR4Cax where μR4: surface mobility, C6e: gate distribution per unit area, W4: channel width, L4: channel length,
Vog4: Boot-source TK voltage, y, h, 2, is the threshold voltage of the MOS transistor of the first conductivity type. 'If the transistor 5 (a MOS transistor of the second conductivity type serving as a current source) operates in the saturation region, the bias current I+
ez is β. ,=μ85C@one.

μe5: surface mobility, W5: channel width, L
6 = channel length, VQII6: gate-source voltage, Vthz: threshold voltage of the second conductivity type MOS transistor.

From equations (1) to (5), the relationship between the input signal V+= and the output signal V'Wt of the circuit in FIG. 2 is as follows: Vast = R1111 (Ic1IC2)10 - (6) becomes.

As can be seen from equation (6), the amplification factor of the circuit shown in FIG.
It can be seen that it depends on L. Therefore, the threshold T
As the pressure and channel dimensions vary, the differential amplification characteristics change.

For example, when the absolute value of the threshold voltage VfB of the first conductivity type MOS transistor 4 decreases, the MO
S) On-resistance Re++4 of transistor 4 decreases.

On the other hand, the current flowing through each MOS transistor 4 does not depend on the threshold voltage Vthl of the first conductive type MO8I transistor, as expressed by equations (1), (2), and (5). Even if the threshold voltage V*hx changes, M, O
8) There is no change in the current flowing through transistor 4. Therefore, the output signal V at the output terminal C. The amplitude of t is M of the first conductivity type.
OS) When the absolute value of va+1 of transistor 4 decreases, it decreases.

Furthermore, considering the case where the absolute value of the threshold voltage V*h2 of the second conductivity type MOS transistor 5 decreases, (5
), Ixz increases, and the currents Icl and Ic2 flowing through the MOS transistor 4 increase.

On-resistance R@II of MOS transistor 4 is Vthz
Because it does not depend on R, even if Vthz changes, the on-resistance R
e++ remains unchanged. Therefore, the output amplitude V+ deviates from the initial design value and increases.

The threshold voltage and channel dimensions are subject to some degree of variation due to variations in device manufacturing conditions.

There is a need for a circuit configuration that reduces changes in differential amplification characteristics due to variations in such parameters.

[Purpose of the invention]

The purpose of the present invention is to maintain the same performance even when the threshold voltage, channel dimensions, etc. of a MOS transistor vary due to manufacturing variations.
It is an object of the present invention to provide a differential amplifier circuit in which bipolar transistors and MOS transistors coexist and whose differential amplification characteristics do not change much.

[Summary of the invention]

The present invention, which achieves the above object, is characterized by a differential pair constituted by bipolar transistors, and a first conductivity type MO8) transistor whose one main terminal is connected to one main terminal of the bipolar transistor. a load resistor of a differential pair, a constant current source composed of a first semiconductor element whose one main terminal is connected to the other main terminal of the bipolar transistor, a source and a drain of which are connected to a control terminal of the first semiconductor element, a second first conductivity type MO8) transistor connected to a power supply potential, a second semiconductor element whose one main terminal and the other main terminal are respectively connected to a control terminal of the first semiconductor element and a ground potential; It is to be equipped.

In a preferred embodiment of the present invention, the first and second semiconductor elements are second conductivity type MO8) transistors, or
Alternatively, it is a bipolar transistor of the same conductivity type as the bipolar transistors forming the differential pair.

[Embodiments of the invention]

An embodiment of the differential amplifier circuit according to the present invention is shown in FIG.
Shown in (b). Bipolar transistor differential pair 1,
MOS of the first conductivity type serving as a load resistance) Langistav 4
A differential amplification stage is constituted by a second conductivity type MOS transistor 5 serving as a constant current source that defines a bias current. The voltage source for biasing the second conductivity type MOS transistor 5 is composed of a first conductivity type MOS transistor 6 which is the same as the MOS transistor 4, and a second conductivity type MOS transistor 6 which is the same as the MOS transistor 5. . The source and drain of the MOS transistor 6 are MO
S) The gate of the transistor 5 is connected to the power supply potential VCC, and the source and drain of the MOS transistor 5 are connected to the gate of the transistor 5 and the ground potential GND, respectively.

Here, if the first conductive type is p type, the terminal type is E.

G is the ground potential GND, and in the case of n-type, the power supply potential VC
Let it be C. Here, the drain D and the source S are connected as shown at 7 when the second conductivity type is n type, and as shown at 7' in FIG. 3(b) when the second conductivity type is p type.

When the configuration shown in Fig. 3(a) is adopted, the first conductor's turtle-shaped MOS
Threshold voltage of transistor 4 Vthx s 24th voltage type M
O8) A differential amplifier whose characteristics change little with respect to fluctuations in the threshold voltage th2 of the transistor 5 can be realized.

The feature of this embodiment is that the voltage source constituted by the MOS transistor 4.5 and the voltage source 7 is designed to compensate for fluctuations in the differential amplification characteristics due to variations in the threshold voltages V*ht and Vsh2 of the MOS transistor 4.5. The feature is that the potential VF at point F in FIG. 3(a) is set.

That is, MOS transistor 6 operates in a non-saturated region, and MOS transistor 7 operates in a saturated region. At this time MOS)
The on-resistance R, 17 is 9, and the current Ia flowing through the MOS transistor 7 is as follows. Here, Ia: MOS) is the current flowing through the transistor and 7. MOS) Ranjistaro pMO8,
When the MOS) Langistav is set to 0MO8, and the potential at point F is set to VF, then according to equations (7) and (8), V F = Vcc Ia R, . . .
・−・α◇ holds true.

Figure 3 (C
). Here, the operating characteristic of MOS) is the slope 1/R0. is represented by the solid line 30 in equation (9). The operating characteristics of the Langistav (MOS) are a quadratic curve as shown by the solid line 31 depending on the cutting distance.

At this time, the potential Vr at point F takes a value corresponding to the intersection 34 of the solid lines 30 and 31.

Now the threshold voltage of MOS transistor 6 V t h 1
As the absolute value of increases, the operating characteristic curve changes from solid line 30 to broken line 32, and the operating point with solid line 31 changes from 34 to 3.
Move to 5 and VF decreases. It can be seen that when the absolute value of the threshold voltage Vth2 of the Ranjistaf (MOS) increases, the operating characteristic curve changes from the solid line 31 to a broken line 33, the operating point with the solid line 30 moves to 36, and VF increases.

For example, consider the characteristics of a differential amplifier when the absolute value of the threshold voltage Vtb1 of the first conductivity type MOS transistor 4 increases. MOS) transistor 4 according to equation (4)
The on-resistance R0,4 of increases. Here, if there is no change in the current flowing through the MOS transistor 4, the output amplitude Va++t will increase as described above. However, in a differential amplifier circuit with a power supply circuit as shown in Fig. 3(a), as the absolute value of the threshold voltage Vth1 of the MOS transistor increases, VF, that is, VosB decreases.
According to equation 5), the bias current Imm is reduced, and as a result, the increase in the output amplitude at the output terminal is suppressed.

Next, consider a case where the absolute value of the threshold voltage Vthz of the MOS transistor 5 increases. When Vy is constant, (5
) formula, threshold voltage Vi2 of 9M0S transistor 5
As Izm increases, Izm decreases, and the output amplitude decreases.

However, in the configuration of FIG. 3(a), as mentioned earlier, when the absolute value of the threshold voltage Vtb2 of the MOS Langistav increases, VF increases, so the decrease in l1ll is suppressed, and the decrease in the output amplitude cannot be suppressed. can.

Also, this configuration is a first conduction type MOS) transistor 4.6
Even if there is a difference in the amount of variation in channel dimensions between the transistor 5.7 and the second turtle-type MOS transistor 5.7, the accompanying variation in differential amplification characteristics can be compensated for.

Channel width of transistor 4.6 (first conduction type MOS)
4. ．． It is assumed that W is significantly reduced in the device manufacturing process compared to the channel width wII, W of the second conductive MOS transistors 5 and 7. In this case, the on-resistance ratio of transistor 4 is given by equation (4). , 4 increases, but VF decreases by equation (7) ~ aυ and becomes 1.4
becomes small, and the output amplitude is eventually kept constant.

Another embodiment of the present invention will be explained with reference to FIG.

FIG. 4 shows a sense amplifier for a bipolar and MOS mixed memory. The memory cells 13 and 14 output data to the data line 10 via the transfer transistor 40 in response to a signal from the word line 12. Here, when the Y selector switch 11 is selected by the Y address line 15, the contents of the memory cell 13 are transferred to the common data line 21.
is output to. Common data line information is load resistance MO8
4, is amplified by a differential amplifier circuit constituted by a current source consisting of differential pair 1 and MOS transistors 5, 6.7, and is output from terminal C. Here, the Ibora transistor 17 is used for impedance conversion. Also 0MO8
) Transistor 8 is for turning on and off MO8') transistor 7, which constitutes a current source, and differential pair 1.
When the data line handled by the memory chip is not selected or when a signal is written, the voltage applied to the terminal G is set to a high level, thereby reducing the power consumption of the memory chip. Further, 9 is a 0MO8) transistor, and 18, 19.20 are constant current sources.

Bipolar transistors have higher conductance g than MOS. Therefore, it is extremely effective when used in a differential pair of a memory sense amplifier that needs to process small signals at high speed.

On the other hand, the gain of the sense amplifier can be increased by increasing the resistance value of the load resistor. It is convenient to use MOS transistors to obtain high resistance on a semiconductor integrated circuit. Since the transistor (NO8) has a relatively low g7, it is possible to create a high resistance with good accuracy in a small area. From the above points, it is highly effective to use a bipolar and CNO8 mixed circuit in order to obtain a high gain and compact differential amplifier circuit.

However, in CMO8 circuits, the threshold value is generally 1.
It is difficult to completely control the a pressure, and some fluctuation is inevitable. When the threshold voltage changes, NO8
) The characteristics of the load MO8 made up of transistors change, and the differential amplification characteristics vary.

The signal at terminal C is output to the outside after being amplified by the amplifier circuit. At this time, the signal amplitude of terminal C changes greatly and
If the operating point of the amplifier circuit connected to terminal C deviates from the operating point, the speed of transmission of signal 1d from terminal C onward will be delayed, resulting in an increase in memory read time.

A fourth circuit that applies the circuit configuration of the differential amplifier circuit according to this embodiment.
In the readout circuit as shown in the figure, the threshold voltage V*ht,
V*hz % Even if the channel dimensions change, the output amplitude remains constant, so the operating point of the amplifier circuit connected to terminal C does not deviate. In this way, this embodiment makes it possible to realize a memory readout circuit that can maintain high speed even when the threshold voltage and channel dimensions vary.

In the embodiment of the present invention, the NO8) transistors 5゜7 need only have the same threshold voltage and channel size fluctuations, so in the previous explanation, they have been described as NO8) transistors of the same conductivity type. Without limitation, as shown in FIG. 5, these are bipolar transistors 22.2 of the same conductivity type as bipolar transistor 1 constituting a differential pair.
It is also possible to replace it with 3.

〔Effect of the invention〕

According to the present invention, it is possible to improve the stability of a bipolar and NO8 mixed type differential amplifier circuit that has the advantages of high gain and compactness.

That is, even if the threshold voltage and channel dimensions change due to variations in process conditions, the differential amplification characteristics can be kept stable. As a result, when manufacturing an element incorporating a bipolar and NO8 mixed type differential amplifier circuit, it is possible to improve the fractional yield during manufacturing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a differential amplifier circuit according to the prior art.
Figure 2 is the same diagram showing the configuration of a differential amplifier circuit according to the prior art, and Figures 3 (a), (b), and (c) are diagrams showing the configuration and operation of a differential amplifier circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing an example in which a differential 1 so 11'i & circuit according to another embodiment of the present invention is applied to a memory circuit, and FIG. 5 is a diagram showing another embodiment of the present invention. . 1... Bipolar transistor forming a differential pair, 2
...Load resistance, 3. Constant current source, 4. 14th conductivity type MOS transistor serving as load resistance, 5... 2nd conductivity type NO8) transistor serving as constant current source, 6.・・・
No. 8) transistor of the first conductivity type, 7.7'...second
Conductive type NO8) transistor, 8...nNO8) transistor, 9...nNO8) transistor, 10... data line, 11... Y address switch, 12° 12'
...Word line, 13, 14...Memory cell, 15.
...Y address line, 17t...Bipolar transistor for impedance conversion, 18,19゜20...
Constant current source, A, B... Differential input terminal, C... Differential output terminal, D, E... Load MO8) Gate of transistor, F... Constant power supply M'08) Gate of transistor , G.
...NO8) Gate of transistor, 21...Common data line, 22.23...Pibora transistor side 1
Figure 2 Figure 3 (α)

Claims (1)

[Scope of Claims] 1. A differential pair constituted by bipolar transistors, and a differential pair constituted by iN4 with a first conductivity type MOS transistor whose main 19m1 child is connected to one main terminal of the bipolar transistor. A pair of load resistors, a constant current source constituted by a first semiconductor element whose one main terminal is connected to the other main terminal of the bipolar transistor, whose source and drain are connected to the control terminal of the first semiconductor element and the Ichihara a second MO transistor of the first conductivity type each connected to a potential, one main terminal and the other main terminal of which are respectively connected to the control terminal of the first semiconductor element and a second transistor connected to the ground potential
A differential amplifier circuit comprising: a semiconductor element. 2. In claim 1, the above-mentioned first and second
A differential amplifier circuit characterized in that the semiconductor element is a second conductivity type MO8) transistor. 3. In claim 1, the above first and second claims
A differential amplifier circuit characterized in that the semiconductor element is an Ibora transistor (of the same conductivity type as the Ibora transistor) constituting the differential pair.