JPS60183816A - Signal amplitude converting circuit - Google Patents

Abstract

PURPOSE:To attain high performance LSI by adding a level shift diode between a collector of a bipolar transistor (TR) and a gate of an n-MOS FET so as to obtain a large output amplitude. CONSTITUTION:The basic building block is improved; a diode D3 is provided between a collector of a bipolar TRQ3 and a gate of an n-MOS FET Q2 and an R3 is added. When an input VIN is at a low level, both the Q3, D3 are turned off, 0V is applied to the gate voltage of the Q2 via the R3 and the Q2 is turned on. When the VIN goes to a high level, the TRQ3 is turned on and the collector current flows not only to the R1 but also to the R3 and D3. A voltage higher than a Vout 2 by a VBE is applied to the gate of the Q2, the ON-resistance of the Q2 is increased by the voltage so as to prevent the saturation of the Q3. As a result, the low level of the Vout 2 is as expressed in equation and a 3.6V output amplitude is obtained. An amplitude larger than the Vout by 0.8V is obtained in this way.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, and more specifically, a high-speed digital LSI (logic LSI or memory IJL).
8 I) relates to the circuit configuration.

[Prior art]

Conventionally, in LSIs that require high-speed performance, ECL (Emit
A circuit format called ter Cowpled Logic is used. The signal amplitude of this circuit is approximately 0.
It is 8V. On the other hand, recently, the 0M08 circuit has come into use, and in particular, it has become widely used in memo IJLSI, taking advantage of its low power consumption feature. 0MO8 type memo IJ L 8 I like this is high-speed ECL
When incorporating into a similar system, enter the memo IJLSI.
It is necessary to make the output signal ECL compatible. Therefore, in the input circuit, the small amplitude of the HCL signal is
In order to operate the 08 circuit, it is necessary to convert the signal amplitude to a large signal amplitude of about 5V.

Normally, a MOS type differential amplifier is used for this input circuit, but the delay time is 5 ns or more, which is a major factor that prevents the achievement of high-speed performance of the entire memory LSI. It becomes. -If you try to obtain a large output signal amplitude with an ipolar differential amplifier, it has the disadvantage that the bipolar transistor will become saturated and the delay time will increase.

Therefore, a basic invention as shown in Figure 1 was made.

(Japanese Patent Application No. 58-180242) In order to achieve the above-mentioned purpose of high-speed signal amplitude conversion, voltage amplification is performed using a bipolar transistor with good voltage sensitivity. −
A MOS-FET is inserted and the gate of the FET is controlled by the output voltage.

The operation of this circuit will be explained in detail using the circuit diagram shown in FIG. 1 and the potential and current transient response analysis waveforms shown in FIG.

E CL input signal VIN (0-9V% 1.7V)
Wow Ql.

The level shift circuit consisting of DI HD2 + "1 performs a 3VB□ level shift. (Veg is the base-emitter voltage of the bipolar transistor (approximately O, SV
), the signal D2 after this level shift has a High level of approximately -
3.3■, Low is approximately -4.IV. This VO2 is input to the drain of an n-MOS-FET, and the source of the FET is connected to the base of an output npn transistor Q3. A reference voltage Vref (approximately -4,8
V) is applied. A load resistor R1 is connected between the collector of Qa and the ground, and also connected to the gate of sQ2. Note that VBB is a power supply voltage (-5, 2v). When the current VIN power is low (■0□ is also low), the npn transistor Q3 is off and Voutl is high.
h level (OV). This Vout2 is n-MOS
-% Q2 because it is applied to the gate of PET (Q2)
is also on. Next, VIN is Htgh (VO2(
) Htgh ) ic When switched, base current is injected into Qa via Q2, turning Qa on.

Although Voutl quickly goes to Low level, Qa is not saturated because this voltage is applied to the gate of Q2 to increase the on-resistance of Q2 and reduce the base current. It can be seen that the base potential VB3 and base current IB3 of Qa change as shown in FIG. 2, and Qa is not saturated. As a result, the low level of Voutl is Vref +78g (Qa) VO
2(Q2);-4,8+0.8-1.2=-2,8V
is obtained. Here, VO2 is the gate-source voltage of the n-MOS-FET, and the drain current is from several μ to several l.
Calculations are made assuming 1.2V when OμA is flowing.

In this way, with this circuit, from 0.8V input double width to 2.8V
The output amplitude of v can be obtained. Also, since the bipolar transistor Q3 operates in a non-saturated state, the delay time of this circuit is VI
When looking at the 50% point of each of N''outl, high-speed conversion is possible at around 1.5 ns on the rising side of V.utl and around 0.8 ns on the falling side.

However, the output amplitude is 2.8V, which is not sufficient to drive the CMOS inverter in the subsequent stage.

[Purpose of the invention]

An object of the present invention is to improve the above-mentioned prior art (circuit format shown in FIG. 1) and to obtain an even larger output amplitude.

[Summary of the invention]

In order to achieve the above object, the present invention improves the basic circuit format shown in Figure 1 and adds a level shift diode between the collector of the bipolar transistor (Qa) and the gate of the n-MOS-FET (Q2). By doing this, the forward voltage (V
nB or V. 8) is intended to obtain a larger output signal amplitude.

[Embodiments of the invention]

Embodiments of the present invention will be described below in comparison with the basic circuit format shown in FIG.

FIG. 3 shows an embodiment of the present invention. Comparing with Figure 1, the collector of the bipolar transistor (Qa): n-M
A diode (D
3) and the addition of R3. When the input VIN is Low, Qa and D3 are both off and %
OV is added to the gate voltage of Q2 via R3, and Q2 is in the on state. Next, when vIN becomes High, Qa turns on, but this collector current not only flows through R1 but also through R
It also flows through 3 and D3. V at the gate of Qz. ut
A voltage higher than 2 by V RB is applied, and at this voltage Qz
This increases the on-resistance of Qz and prevents saturation of Qz. This result is V. The low level of ut2 is Vref + Vng (Qz) + Vos (Qz) VBg (
D3):”l:Vref + VO2(Qz) =-4
,8+1.2=-3.6V is obtained. Thus V.

3.6■ is obtained as the output amplitude of ut2. In this way, V in Figure 1. An amplitude 0.8■ larger than utl can be obtained. FIG. 4 shows the results of transient response analysis of the circuit shown in FIG. 3. Although the difference is that the amplitude of vout2 is large, the delay time is almost the same as the analysis result of FIG. 2.

FIG. 5 shows another embodiment of the present invention, and in FIG.
VBI of the g level shifted thing with a transistor and a resistor
This allows a level shift of an arbitrary multiple of I. In FIG. 5, the gate voltage of Qz and the collector potential of s Q34 differ by (1+-)VBB. The Low level of vout 3 is obtained, and the output amplitude of vout 3 is the same as that of the first embodiment (third example).
Compared to the figure, an amplitude larger by R4/Rs x Vng can be obtained. This value can be freely set by the value of R4/Rs.

A third embodiment of the invention is shown in FIG. This is n-MO
An n-MOS-FFAT (Qs) is used as a level shift diode between the gate of the 8-FET (Q, 2) and the collector of the bipolar transistor (Qz). In this figure 6, the output ■. ut4 High
The level is Ov and is equal to the two examples of MiJ. −
The low level of the force, vout4, is expressed by the following equation.

Vref+VnB(Qz)+Vos(Qz) Vos(
Qs) zvref+Vam” 4.8+0.8=-4,
OvAs a result, the output amplitude of hvout4 is 4v.

In the embodiment of the previous invention (FIG. 1) and the three embodiments of the present invention (FIGS. 3, 5, and 6), the input signal level shift circuit consists of an emitter follower circuit and two diodes. So the level is shifted by 3 VBB,
It is possible to perform level shifting using only an emitter follower circuit instead of a diode. Further, the level shift amount can also be set to a different level shift amount depending on the setting of the reference voltage Vref. Also, Figure 1, Section:
In Figures 3, 5, and 6, R2 is a resistor for discharging the base load, but one end of this is connected to VgB instead of Vref potential.
It may also be connected to Tunyuan. Also, if this resistor is removed, the rise response of the output will be delayed somewhat, but depending on the purpose, the temperature may be set in this way. It is also possible to form the resistors R, , R3 in FIGS. 1, 3, 5, and 6 with n-MO8-1i''ET.

FIG. 7 is a circuit diagram showing a method of generating the reference voltage Vref in the present invention, and Vref is -6VB.

:; It is possible to obtain a constant voltage of -4.8V almost independently of the power supply voltage VBII.

〔Effect of the invention〕

As described above, the circuit of the present invention provides an E of 0.8 V amplitude.
The CL input can be converted to a large amplitude of about 4V, and the time required for the conversion is as fast as about 1.5ns.

Even higher speeds can be achieved by optimizing the resistors L and R2. This output signal can be used to drive a CMOS inverter or the like.

And the input signal is IDCL compatible and internal is 0M0
It is possible to realize a memory IJLSI or a logic LSI with eight circuits, and it can contribute to improving the performance of these LSIs.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the invention of the earlier application (No. 11? Application No. 180242/1983), Fig. 2 is a diagram showing the transient response analysis results of the circuit shown in Fig. 1, Figs. 3, 5, FIG. 6 shows an embodiment of the present invention, FIG. 4 shows a transient response analysis result of the circuit shown in FIG. 3, and FIG. 7 shows a reference voltage Vref generation circuit. Explanation of symbols QttQ3rQ4pQu... npn bibolar transistor Q2. Qs...-n-MOS-FETD
, , D2. D3. D,,%D,5...
Diodes R1, R2, R3, R4, 5. R11,
...Resistance V I N ... Input signal Vout ” r vOui 2+ Vout ” r
Vout 4... Output signal Vref...
...Reference voltage VBB...Power supply voltage 3) 9 Corner f Akira 2. )9 Kenyu: '3 (?ls) Ken'e I+ (Female) Kengitsu 乍L Otsu 1st Q 71st sword vEl:

Claims (1)

[Claims] An emitter follower circuit using an npn type bipolar transistor or an input signal level shift circuit formed by cascading at least a plurality of diodes, an n-MOS-FET whose drain is connected to the output of the level shift circuit, and a base of the 1" an npn type output transistor connected to the source of the FET, a predetermined reference voltage connected to the emitter of the output transistor, and a resistor connected between the collector and ground and between the gate of the FET and ground,
Between the collector and the gate, connect a bipolar diode or M with the anode on the gate side and the cathode on the collector side.
A signal amplitude conversion circuit that inserts an O8 type diode to increase the amplitude of an input signal to the base terminal of the first stage of the level shift circuit, and obtains an output signal from the collector of the output transistor.