JPS63174356A - Semiconductor device for image processing - Google Patents

Abstract

PURPOSE:To make short the wirings located between each section of the title semiconductor device and to contrive both miniaturization of constitution and accomplishment of high speed operation of the device by a method wherein a light-receiving part, a memory part and a logical operation part are laminated in one body. CONSTITUTION:Photoelectric conversion elements 10 are arranged in matrix form on a plurality of the first semiconductor layers 1. Said photoelectric conversion elements 10 are formed with the element in which the degree of resistance varies by the intensity of the light received such as amorphous Si for example. On the second semiconductor layer 2, a plurality of memory circuits 20 are provided in matrix form corresponding to the photoelectric conversion element 10. Memory elements 30 are formed on the third semiconductor layer 3. On the fourth semiconductor layer 4, a plurality of logical operation elements 40 are formed in matrix form corresponding to the elements 10, and besides, a timing control circuit 41 is formed.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Field of Application) The present invention relates to a semiconductor device used for digital image information processing, and particularly relates to a method for detecting only moving parts from a plurality of images on the same screen. The present invention relates to an image processing semiconductor device for extracting or detecting the presence or absence of a moving image.

A method is adopted in which the captured image is stored in the memory 52, and then the CPU 53 is used to perform serial processing on the data in the memory 52. For example, when extracting only a moving image from among multiple images on the same screen, the image of the object 54,55 at time t1 is divided into digital data for each pixel by the light receiving element 51, and input/output control is performed. CP via device 56
Stored at address 57 in memory 52 under control of U53. Furthermore, the image at time t2 is similarly stored at another address 58 in the memory 52. At this time, as shown in FIG.
3.64. Therefore, by calculating the exclusive OR of data corresponding to the same pixel, the contour 65 of the moving image is extracted.

However, this type of device has the following problems. That is, since the spatial distance between the light receiving section, the storage section, the logic operation section, etc. becomes large, it is difficult to send signals at high speed. Furthermore, there is a problem that the light receiving time becomes longer in proportion to the number of pixels.

(Problems to be Solved by the Invention) As described above, it has been difficult to miniaturize the overall configuration of image processing semiconductor devices that have conventionally combined different parts for each function such as a light receiving section, a storage section, and a logic operation section. Moreover, there was a drawback that the processing speed decreased significantly as the number of pixels increased.

The present invention has been made in consideration of the above circumstances, and its purpose is to obtain a sufficiently high processing speed even when the number of pixels increases, and to reduce the size of the configuration.
An object of the present invention is to provide an image processing semiconductor device suitable for extracting moving images.

[Configuration of the Invention (Means for Solving Problems) The gist of the present invention is to employ a so-called three-dimensional structure in which parts having different functions are arranged in a layered manner.

That is, the present invention provides a semiconductor device for image processing that extracts only a moving part from a plurality of images on the same screen or detects the presence or absence of a moving image. A storage element that stores each output, a second storage element that stores each output formed by arranging storage elements that store each output of the photoelectric conversion element in a matrix, and a storage element of this semiconductor layer. A third storage element that stores each output of the photoelectric conversion element, which is formed by arranging in a matrix a storage element that stores each output of the photoelectric conversion element with a time lag; The first to fourth semiconductor layers are arranged in an arbitrary order, and each of the first to fourth semiconductor layers is arranged in a matrix in which logic elements are arranged in a matrix to store each of the fourth outputs. It is arranged in a stacked manner.

(Function) With the above configuration, since the light receiving section, storage section, logic operation section, etc. are integrated into one layer, the overall structure can be made smaller, and the wiring between each part can be made extremely short. . Therefore, it becomes possible to shorten the time required for signal processing, and it is possible to sufficiently cope with an increase in the number of pixels.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a schematic configuration diagram schematically showing an image processing semiconductor device according to an embodiment of the present invention. In the figure, 1 is a plurality of first semiconductor layers, and photoelectric conversion elements 10 are arranged in a matrix in this layer 1. The photoelectric conversion element 10 is an element whose resistance changes depending on the intensity of received light, such as an amorphous S
It is formed from i. 2 is a second semiconductor layer, and in this layer 2, a plurality of memory circuits (storage elements) 20 are formed in a matrix in correspondence with the photoelectric conversion elements 10. 3 is a third semiconductor layer, and in this layer 3, a memory element 30 is formed similarly to the second semiconductor layer 2.

4 is a fourth semiconductor layer, and in this layer 4, a plurality of logic operation elements 40 are formed in a matrix shape corresponding to the photoelectric conversion element 10, and a timing control circuit 41 is further formed.

FIG. 2 shows a circuit configuration factor corresponding to one pixel of the above device. The photoelectric conversion element 10 of the first semiconductor layer 1 is connected in parallel with the capacitor 11.

The memory circuit 20 of the second semiconductor layer 2 includes an inverter 21
．． 22 and a transistor 23 are connected in a closed loop configuration. An input terminal of the memory circuit 2o is connected to the photoelectric conversion element 10 via an input transistor 24, and an output terminal is connected to the exclusive logic gate third semiconductor layer 3 via an output transistor 25, which will be described later. Similarly to the semiconductor layer 2, a memory circuit 30 consisting of inverters 31 and 32 and a MOS transistor 33, and a transistor 34
．． 〜、36 are formed. Further, the logical operation element 40 of the fourth semiconductor layer 4 is an exclusive OR gate, and the outputs of the two memory circuits mzo and so are given to the input terminal of this exclusive OR gate 4o, and the transistor 42
The logical OR output is taken out via the . Further, the fourth semiconductor layer 4 includes the first semiconductor layer 1
A transistor 43 is formed to apply a predetermined potential v, 8 to the photoelectric conversion element 10.

Next, the operation of the apparatus configured as described above will be explained with reference to the timing chart of FIG.

First, prior to operation, the reset signal φ is set to “H”SR, and the potential on one side of the photoelectric conversion element 10 is set to a predetermined potential vP.
Set to s. When φPSR is set to L'' at time t1, the potential changes according to the amount of light received until time 1./.During this period, the amount of light received from one terminal Pt1 of the memory circuit 2o to time t1' is binarized and stored in the memory. latched into circuit 20.

Similarly, after the amount of light received from time t2 to t2' is latched in the memory circuit 30, the contents of the two memories are transferred to the exclusive OR gate DT 40 by the pulse φ. Thereafter, the data obtained by exclusive ORing ur is outputted to the outside by pulse φ.

The image data thus obtained is "L" when the object is not moving, and "H" only when the object is moving.
becomes. Therefore, only moving parts can be extracted from multiple images on the same screen. In this case, the photoelectric conversion element 10 serves as a light receiving section, and the memory circuit 20 serves as a storage section.
．． 30, and an exclusive logic gate 40 serving as a logic operation section
Since these are integrated into one layer, the overall structure can be significantly miniaturized. Furthermore, since the wiring between each part can be made extremely short, it is also possible to transmit signals at high speed.
The overall processing time can be significantly reduced.

Therefore, even if the number of pixels increases, signal processing can be performed at a sufficiently high speed, and a p-type MOS transistor 42 can be formed by the method.

The first and seventh transistors 42 form a part of the exclusive OR gate 40 of the fourth semiconductor layer 4.

Next, as shown in FIG. 4(b), a 5i02 film 43 having a thickness of about 0.8 to 1.2 [μ77Z] is formed on the entire surface by CVD.
After covering the substrate 41 with etching, a hole is formed to expose the substrate 41 in an etching process. Next, the thickness is about 0.8 [μ7IL]
After forming a polycrystalline silicon film by a sputtering process, this is annealed by electron beam irradiation to form a single crystal St layer 44 as the third semiconductor layer 3. Thereafter, as shown in FIG. 4(c), a transistor 45 forming a part of the memory circuit 30 is formed.

Next, as shown in FIG. 4(d), the whole is made to a thickness of about 0.8
~1.2 Cttml (1) Cover again with the CVD-S i 02 film 43, and form an opening by etching to expose the single crystal part and use it as a seed part during single crystallization of the upper layer.

After depositing a polycrystalline silicon film with a thickness of about 0.6 [μ7IL] on this 5i02 film 43, it is made into a single crystal by irradiation with an electron beam, and the single crystal S as the second semiconductor layer 2 is formed again.
One layer 44 is formed. Part 47. Amorphous SL film 48
and a transparent electrode 49 are formed in this order to form the photoelectric conversion element 10 of the first semiconductor layer 1. This allows the first
to fourth semiconductor layer 1. A semiconductor device formed by laminating and integrating .

Note that the present invention is not limited to the embodiments described above. For example, the stacking order of the first to fourth semiconductor layers can be changed arbitrarily.

However, the first semiconductor layer forming the photoelectric conversion element is preferably the uppermost layer in order to obtain a sufficient amount of incident light. Furthermore, instead of using amorphous silicon as the photoelectric conversion element, it is possible to use a PIN photodiode or the like. Furthermore, the memory circuits of the second and third semiconductor layers are not limited to the same as shown in FIG.
It can be changed as appropriate depending on the specifications. In addition, various modifications can be made without departing from the gist of the present invention.

[Effect of the invention] As detailed above, according to the present invention, there is provided a light receiving section.

It can be serialized and exhibits an effective effect as an image processing semiconductor device used for extracting moving images.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram schematically showing an image processing semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing one pixel equivalent of the above device, and FIG. 3 is a circuit diagram of the above device. FIG. 4 is a cross-sectional view showing the manufacturing process of the above device, and FIGS. 5 and 6 are schematic diagrams for explaining the problems of the conventional device. DESCRIPTION OF SYMBOLS 1... First semiconductor layer, 2... Second semiconductor layer, 3
...Third semiconductor layer, 4...Fourth semiconductor layer, 10
...Photoelectric conversion element, 20.30...Memory element, 4
0...Logic operation element. Applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka Figure 3 Figure 4

Claims (4)

[Claims] (1) A first semiconductor layer formed by arranging a plurality of photoelectric conversion elements in a matrix, and a second semiconductor layer formed by arranging memory elements each storing each output of the photoelectric conversion elements in a matrix. , a third semiconductor layer formed by arranging memory elements in a matrix that store each output of the photoelectric conversion element with a time lag from the memory element of this semiconductor layer; and the second and third semiconductors. a fourth semiconductor layer formed by arranging logic elements in a matrix to perform logical operations on data stored in corresponding storage elements of the layer;
A semiconductor device for image processing, characterized in that the first to fourth semiconductor layers are stacked in any order. (2) The image processing semiconductor device according to claim 1, wherein the first semiconductor layer is an uppermost layer. (3) The image processing semiconductor device according to claim 1, wherein the photoelectric conversion element is made of amorphous silicon. (4) The image processing semiconductor device according to claim 1, wherein the logic element is an exclusive OR circuit.