CN104282628B - A kind of preparation method of cmos image sensor overall situation pixel storage capacitance - Google Patents
A kind of preparation method of cmos image sensor overall situation pixel storage capacitance Download PDFInfo
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- CN104282628B CN104282628B CN201410593540.5A CN201410593540A CN104282628B CN 104282628 B CN104282628 B CN 104282628B CN 201410593540 A CN201410593540 A CN 201410593540A CN 104282628 B CN104282628 B CN 104282628B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 66
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 66
- 238000009413 insulation Methods 0.000 claims abstract description 63
- 230000004888 barrier function Effects 0.000 claims abstract description 58
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 1
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- 238000005516 engineering process Methods 0.000 description 15
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- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
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- 230000003321 amplification Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
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- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
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- -1 silicide metals Chemical class 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
Abstract
The invention discloses a kind of preparation method of cmos image sensor overall situation pixel storage capacitance, original abutment wall structure is substituted by forming lighttight metal silicide layer in the top crown side wall of storage capacitance, and formed by insulation barrier on mos capacitance, clearance for insulation between bottom crown metal silicide, make to incide the light in storage capacitance to be reflected by metal silicide layer, avoid incident light and enter mos capacitance charge signal memory block from the side wall of top crown, so as to reduce the light source spurious response of memory node, ensure the accuracy of signal in global exposing pixels unit storage capacitance, prevent from storing the distortion of signal, and can effectively it prevent, short circuit generation between bottom crown.
Description
Technical field
It is complete more particularly, to a kind of cmos image sensor the present invention relates to field of IC technique
The preparation method and structure of office's pixel light leakage storage capacitance.
Background technology
Imaging sensor refers to the device for converting optical signals to electric signal, generally extensive commercial imaging sensor core
Piece includes charge coupling device (CCD) and the major class of complementary metal oxide semiconductor (CMOS) image sensor chip two.
Cmos image sensor is compared with traditional ccd sensor, have low-power consumption, low cost and with CMOS technology phase
The features such as compatible, therefore obtain more and more extensive application.Now, cmos image sensor has not only been applied to consumer electronics neck
In domain, such as miniature digital camera (DSC), mobile phone camera, video camera and digital single anti-(DSLR), moreover, automotive electronics,
The fields such as monitoring, biotechnology and medical science are also widely used.
The pixel cell of cmos image sensor is that imaging sensor realizes photosensitive core devices, the most frequently used pixel list
Member is the active pixel structure comprising a photodiode and four transistors.In these devices, photodiode is sense
Light unit, realize the collection to light and opto-electronic conversion；Other MOS transistors are control units, are mainly realized to photoelectricity two
The choosing, reset of pole pipe, signal amplification and the control read.The number of MOS transistor, determines non-sense in one pixel cell
Size shared by light region.Dot structure comprising four transistors is commonly referred to as 4T pixel cells.
Generally there are two kinds of shutter control modes in digital camera:That is mechanical shutter and electronic shutter.Mechanical shutter passes through
The foldings of mechanical parts before cmos image sensor controls the time for exposure；Electronic shutter by pixel cell when
Sequence is controlled to change the time of integration, so as to reach the purpose of control time for exposure.Because mechanical shutter needs mechanical parts, can take
The area of digital camera, therefore it is not suitable for portable digital camera.For video surveillance applications, due to be typically into
Row video acquisition, therefore, typically using the electronic shutter control time for exposure.Electronic shutter is divided into two kinds again：That is roller shutter type and complete
Office's exposure type.Roller shutter type electronic shutter often go between time for exposure be inconsistent, easily made when shooting high-speed object
Into motion blur phenomenon；And then every a line of global exposure type electronic shutter is simultaneously stored charge signal in same Time Exposure
In the memory node of pixel cell, finally the signal of memory node is exported line by line.Global exposure type electronic shutter is due to all
Row is exposed in the same time, so motion blur phenomenon will not be caused.
It is right with cmos image sensor application more and more extensive in industrial, vehicle-mounted, road monitoring and high speed camera
Further improved in the demand for the imaging sensor that can catch high-speed moving object image.In order to monitor high-speed object, CMOS
Imaging sensor needs to use the global pixel cell (referred to as global pixel) exposed, and is used to deposit in global exposing pixels unit
The memory node for storing up charge signal is a very important index for the spurious response of light source.In actual applications, according to
Each pixel cell uses the number of transistor, and global exposing pixels unit has 4T, 5T, 6T, 8T and 12T etc..Although various pictures
Transistor size in plain unit is different, but their light leakage requirements to storage capacitance therein are identicals.
Referring to Fig. 1, Fig. 1 is a kind of circuit structure of existing 8T overall situations exposing pixels unit.As shown in figure 1, with 8T
Exemplified by global exposing pixels unit, charge-storage node is exactly mos capacitance C1 and C2 therein.The light source of memory node is parasitic to be rung
Spurious response of the memory node electric capacity to incident light should be referred to.For pixel cell, the light on pixel cell surface is incided
Line can not all focus on photodiode surface due to refraction and scattering, have some light to incide storage
On node C1 and C2, C1 can also produce photoelectric respone under the irradiation of incident light with C2 as photodiode.Due to entering
Penetrate the irradiation of light and on C1 and C2 caused electric charge, can influence to store the superincumbent voltage as caused by photodiode originally
Signal, thus cause the distortion of signal.
MOS storage capacitances in CMOS technology include MOS conventional capacitances and MOS transfiguration electric capacity, and mos capacitance is according to doping class
Type can be divided into two kinds of structures of N-type and p-type again.Further referring to Fig. 2, Fig. 2 is a kind of existing conventional N-type MOS transfigurations electricity
Hold structure.By taking N-type MOS transfiguration electric capacity as an example, its cross section structure is as shown in Fig. 2 mos capacitance is one is formed in P type substrate 1
Two terminal device.The top crown 5 of electric capacity is N-type polycrystalline, extractions of the metal silicide 4-2 as top crown 5；Bottom crown 2 is N
Trap, the top of N traps 2 are N+ source-drain areas 3, extractions of the metal silicide 4-1 as bottom crown 2；Gate oxide 6 in CMOS technology is made
Dielectric layer between capacitor plate.In CMOS technology, in order to reduce the transverse electric field of device, it is necessary to using the source being lightly doped
Drain region.Therefore separated, it is necessary to be injected N+ injections and NLDD using abutment wall 7, the introducing of abutment wall also can prevent N+ polycrystalline simultaneously
Short circuit between the metal silicide above N+ source-drain areas.But due to dielectric layer that abutment wall uses be typically silica or
Silicon nitride, and silica and silicon nitride are all-transparent for incident ray, therefore incident ray can penetrate abutment wall 7 and enter
The polycrystalline top crown 5 of electric capacity and the region (as indicated by the arrows in the figure) of N traps bottom crown 2, cause the charge signal stored in mos capacitance
Distortion, ultimately cause the distortion of cmos image sensor output signal.
Therefore, how effectively to prevent incident light from entering mos capacitance charge signal memory block, to avoid storing the mistake of signal
Very, it has also become one important topic of industry.
The content of the invention
It is an object of the invention to overcome drawbacks described above existing for prior art, there is provided a kind of cmos image sensor is global
The preparation method of pixel storage capacitance, substituted by forming lighttight metal silicide layer in the top crown side wall of storage capacitance
Original abutment wall structure, make to incide the light in storage capacitance and reflected by metal silicide layer, avoid incident light from upper pole
The side wall of plate enters mos capacitance charge signal memory block, so as to reduce the light source spurious response of memory node, prevents from storing
The distortion of signal.
To achieve the above object, technical scheme is as follows：
A kind of preparation method of cmos image sensor overall situation pixel storage capacitance, including：
Step 1：A substrate is provided, over the substrate the trap of the bottom crown of formation storage capacitance, top crown and metal-oxide-semiconductor
Area, grid；
Step 2：Insulation barrier is deposited, then, removes the upper surface of the top crown and the insulation of side wall covering
Barrier layer, retain the top crown sidewall bottom and the insulation barrier with exterior domain；
Step 3：The first metal silicide layer is deposited in the upper surface of the top crown and side wall, then, is removed on described
The sidewall bottom of pole plate is located at below first metal silicide with the insulation barrier of exterior domain；
Step 4：Abutment wall etching and source and drain injection are carried out to the storage capacitance and the metal-oxide-semiconductor, then, described in removal
The abutment wall of storage capacitance；
Step 5：Above the bottom crown on the outside of the insulation barrier of the storage capacitance, the source and drain of the metal-oxide-semiconductor
The second metal silicide layer of deposit above area and grid, and first metal silicide is led in the top crown sidewall bottom
Crossing between the insulation barrier and second metal silicide layer of the storage capacitance has clearance for insulation.
Preferably, the substrate is p-type or N-type substrate.
Preferably, in step 2, using photoetching process, being coated with, being exposed and developed for photoresist is carried out, to remove on described
The upper surface of pole plate and the photoresist of side wall covering, then, the upper surface of the top crown are removed using dry or wet etch
And the insulation barrier of side wall covering, retain the top crown sidewall bottom and the insulation barrier with exterior domain.
Preferably, in step 3, removed using dry or wet etch described in being covered beyond the side wall of the top crown
Insulation barrier, retain the insulation barrier of the top crown sidewall bottom.
Preferably, in step 4, using photoetching process, being coated with, being exposed and developed for photoresist is carried out, to be deposited described in removal
Storing up electricity holds the photoresist of region overlay, then, the abutment wall of the storage capacitance is removed using dry or wet etch.
Preferably, the insulation barrier is single or multiple lift.
Preferably, the insulation barrier is using silica, silicon nitride or silicon oxynitride one or more therein
The single or multiple lift barrier layer of formation.
Preferably, the thickness of the insulation barrier is 10~1000 angstroms.
Preferably, the thickness of second metal silicide layer is less than the thickness of the insulation barrier.
Preferably, first metal silicide layer and/or second metal silicide layer are using titanium, cobalt or nickel shape
Into metal silicide layer.
It can be seen from the above technical proposal that the present invention forms lighttight gold by the top crown side wall in storage capacitance
Belong to silicide layer and substitute original abutment wall structure, and by insulation barrier formed the upper and lower pole plate metal silicide of mos capacitance it
Between clearance for insulation, make to incide the light in storage capacitance and reflected by metal silicide layer, avoid incident light from top crown
Side wall enter mos capacitance charge signal memory block, so as to reduce the light source spurious response of memory node, ensure global expose
The accuracy of signal in light pixel unit storage capacitance, prevents from storing the distortion of signal, and can effectively prevent between upper and lower pole plate
Short circuit generation.Therefore, the present invention can be mutually compatible with existing CMOS technology well, and it is high-quality to obtain imaging sensor
The image of amount.
Brief description of the drawings
Fig. 1 is a kind of circuit structure of existing 8T overall situations exposing pixels unit；
Fig. 2 is a kind of existing conventional N-type MOS transfiguration capacitance structures；
Fig. 3 is a kind of flow chart of the preparation method of cmos image sensor overall situation pixel storage capacitance of the present invention；
Fig. 4~Figure 14 is that a kind of cmos image sensor of preparation method making of application drawing 3 in one embodiment of the invention is complete
The device architecture schematic diagram of office's pixel storage capacitance.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment of the present invention is described in further detail.
It should be noted that in following embodiments, when embodiments of the present invention are described in detail, in order to clear
Ground represents the structure of the present invention in order to illustrate, special that structure in accompanying drawing is not drawn according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should avoid being understood in this, as limitation of the invention.
In the present embodiment, referring to Fig. 3, Fig. 3 is a kind of cmos image sensor overall situation pixel storage capacitance of the present invention
Preparation method flow chart.Meanwhile please compare refering to Fig. 4~Figure 14, Fig. 4~Figure 14 is application drawing in one embodiment of the invention
3 preparation method makes a kind of device architecture schematic diagram of cmos image sensor overall situation pixel storage capacitance.In Fig. 4~Figure 14
The device architecture of signal, it is corresponding with each making step in Fig. 3 respectively, in order to the understanding to the inventive method.
As shown in figure 3, the invention provides a kind of preparation method of cmos image sensor overall situation pixel storage capacitance, bag
Include：
As shown in frame S01, step 1：One substrate is provided, forms bottom crown, the top crown of storage capacitance over the substrate
Well region, grid with metal-oxide-semiconductor.
It refer to Fig. 4, the MOS storage capacitances in CMOS technology include MOS conventional capacitances and MOS transfiguration electric capacity, mos capacitance
Two kinds of structures of N-type or p-type can be divided into again according to doping type, it corresponds to and uses p-type or N-type substrate (i.e. silicon chip).With normal
Formed in the CMOS technology of rule exemplified by the process of the N-type MOS transfiguration electric capacity of the present invention, first, used on the silicon chip of P type substrate 1
Stand CMOS forms N traps 2, grid oxygen 6 and N-type polycrystalline 5, makes have storage capacitance area 20 and metal-oxide-semiconductor area on the substrate 1
30.N traps 2 are the bottom crown of N-type transfiguration mos capacitance and the well region of conventional metal-oxide-semiconductor；Jie of the grid oxygen 6 as N-type transfiguration mos capacitance
The grid oxide layer of matter layer and conventional metal-oxide-semiconductor；N-type polycrystalline 5 is as the top crown of N-type transfiguration mos capacitance and the grid of conventional metal-oxide-semiconductor.
As shown in frame S02, step 2：Insulation barrier is deposited, then, the upper surface and side wall for removing the top crown are covered
The insulation barrier of lid, retains the top crown sidewall bottom and the insulation barrier with exterior domain.
Fig. 5 is refer to, insulation barrier 8 is deposited in silicon chip surface full sheet, storage capacitance area and metal-oxide-semiconductor area is all covered
Lid.Insulation barrier 8 can be single layer structure or sandwich construction, can use silica, silicon nitride or silicon oxynitride etc. absolutely
One or more in edge material are formed, and its gross thickness is between 10 angstroms to 1000 angstroms.For example, it can be formed sediment in silicon chip surface full sheet
Product a layer thickness is 10 angstroms or 1000 angstroms of silica or silicon nitride or silicon oxynitride as insulation barrier；Also can form sediment successively
Silica, 50 angstroms of the silicon nitride of 10 angstroms of product, form the insulation barrier for the two-layer structure that gross thickness is 60 angstroms；It can also replace
Silica, 200 angstroms of silicon nitride, 300 angstroms of the silicon oxynitride of 100 angstroms of deposit, form the three-decker that gross thickness is 600 angstroms
Insulation barrier.
Purpose using insulation barrier is in order to which the designated area subsequently in device forms metal silicide, i.e., as gold
Belong to the barrier layer of silicide.
Fig. 6 is refer to, then, using photoetching process, being coated with, being exposed and developed for photoresist 9 is carried out on full wafer silicon chip,
The photoresist for subsequently needing to form the upper surface of the top crown 5 of the N-type transfiguration mos capacitance of metal silicide and side wall covering is gone
Remove.
Fig. 7 is refer to, then, using dry or wet etch, the insulation that the upper surface of top crown 5 and side wall cover is hindered
Barrier 8 removes.This process needs to control etch amount and etch rate, prevents the insulation barrier 8-1 quilts of top crown sidewall bottom
Etch away, the insulation barrier 8-1 retained at this will be used as the barrier layer of metal silicide, play a part of clearance for insulation.
Due to there is the protection of photoresist 9, the sidewall bottom of top crown 5 is also obtained with the insulation barrier 8 of exterior domain (including conventional metal-oxide-semiconductor area)
To retain.Then, by removing photoresist 9, formed as shown in Figure 8 with insulation barrier 8-1,8 N-type MOS transfigurations electricity
Appearance and conventional MOS structure.
As shown in frame S03, step 3：The first metal silicide layer is deposited in the upper surface of the top crown and side wall, so
Afterwards, the sidewall bottom for removing the top crown is located at below first metal silicide with the insulation barrier of exterior domain
Layer.
Fig. 9 is refer to, the deposit and reaction of metal silicide is carried out, deposits to be formed in the upper surface of top crown 5 and side wall
First metal silicide layer 10.First metal silicide layer 10 is as the extraction of top crown 5 and the screen layer of incident light, so as to shape
Into the polycrystalline upper polar plate structure of complete mos capacitance.First metal silicide layer 10 can use silicon conventional in CMOS technology
Compound metal material is formed, including titanium, cobalt or nickel etc., and therefore, the present invention need not increase extra gold in CMOS technology
Belong to material.
Figure 10 is refer to, then, is hindered the insulation covered beyond the side wall of top crown 5 using dry or wet etch
Barrier removes (including conventional metal-oxide-semiconductor area), but retains the sidewall bottom of top crown 5 and be located at the exhausted of the lower section of the first metal silicide layer 10
Edge barrier layer 8-1, to form the clearance for insulation between the upper and lower pole plate 5,2 of mos capacitance, prevent the short circuit between pole plate.
As shown in frame S04, step 4：Abutment wall etching and source and drain injection are carried out to the storage capacitance and the metal-oxide-semiconductor, so
Afterwards, the abutment wall of the storage capacitance is removed.
Figure 11 is refer to, using stand CMOS, to MOS capacitance region and metal-oxide-semiconductor area progress abutment wall 7 etches and source and drain
3 injections.In CMOS technology, in order to reduce the transverse electric field of device, it is necessary to using the source-drain area being lightly doped, therefore, it is necessary to make
N+ injections and NLDD are injected with abutment wall and separated.
Figure 12 is refer to, then, using photoetching process, being coated with, being exposed and developed for photoresist 11 is carried out, by mos capacitance
The photoresist of region overlay removes, and conventional metal-oxide-semiconductor region still has photoresist 11 to shelter.
Figure 13 is refer to, then, the abutment wall of MOS capacitance region is removed using dry or wet etch.Because abutment wall uses
Dielectric layer be typically silica or silicon nitride, and silica and silicon nitride are all-transparent for incident ray, thus
In the prior art, incident ray can penetrate polycrystalline top crown and N trap bottom crown region of the abutment wall into electric capacity, cause MOS electric
The distortion of the charge signal stored in appearance.Because the present invention in the side wall of top crown 5 uses lighttight first metal silicide
10 instead of abutment wall, therefore, after being reached the separated purpose of N+ injections and NLDD injections using abutment wall, you can removed.
As shown in frame S05, step 5：Above the bottom crown on the outside of the insulation barrier of the storage capacitance, institute
The second metal silicide layer of deposit above the source-drain area and grid of metal-oxide-semiconductor is stated, and makes first metal silicide on described
Pole plate sidewall bottom is exhausted by having between the insulation barrier and second metal silicide layer of the storage capacitance
Intermarginal gap.
Figure 14 is refer to, finally, using the metal silicide technology of conventional cmos, in the insulation barrier of N-type mos capacitance
The top of bottom crown 2 (i.e. the top of N+ source-drain areas 3), the N+ source-drain areas 3 of metal-oxide-semiconductor and the deposit of the top of grid 5 in outside form the second gold medal
Belong to silicide layer 4-1.In the second metal silicide 4-1 of N-type MOS capacitance region, extraction and incident optical screen as bottom crown 2
Cover layer.The the second metal silicide 4-1 formed on the polycrystalline 5 and N+ source-drain areas 3 of conventional metal-oxide-semiconductor, respectively as grid 5 and source
The extraction in drain region 3.Second metal silicide layer 4-1 is formed using silicide metals material conventional in CMOS technology, including
Titanium, cobalt or nickel etc..Also, the second metal silicide layer 4-1 and the first metal silicide layer 10 can be used identical or differ
Silicide metals materials is formed.
In order that the first metal silicide 10 passes through insulation barrier 8-1 in the sidewall bottom of top crown 5 of N-type mos capacitance
There is clearance for insulation between the second metal silicide layer 4-1, when depositing the second metal silicide, the second metal silication must be made
Nitride layer 4-1 thickness is less than insulation barrier 8-1 thickness, to make the first metal silicide 10 and the second metal silicide 4-
It will not be in contact between 1 (from diagram as can be seen that being phase between the first metal silicide 10 and the second metal silicide 4-1
Separation).Due to having between the first metal silicide 10 and the second metal silicide 4-1 of N-type mos capacitance as between insulation
The insulation barrier 8-1 of gap stop, avoid the short circuit hair between mos capacitance top crown N-type polycrystalline 5 and bottom crown N traps 2
It is raw.
When prior art makes mos capacitance in CMOS technology, in order to reduce the transverse electric field of device, it is necessary to using gently mixing
Miscellaneous source-drain area, it is therefore desirable to N+ injections and NLDD are injected using abutment wall and separated.The introducing of abutment wall also can prevent N+ simultaneously
The short circuit of metal silicide above polycrystalline and N+ source-drain areas.But the dielectric layer that abutment wall uses is typically silica or nitridation
Silicon, silica and silicon nitride are all-transparent for incident ray, therefore incident ray can penetrate abutment wall into electric capacity
Polycrystalline top crown and N trap bottom crowns region, cause the distortion of charge signal stored in mos capacitance, ultimately cause cmos image
The distortion of sensor output signal.
In order to solve above mentioned problem existing for prior art, the present invention is formed not by the top crown side wall in storage capacitance
First metal silicide layer of printing opacity substitutes original abutment wall structure, and forms the upper and lower pole plate of mos capacitance by insulation barrier
First, second metal silicide between clearance for insulation, due to the lighttight characteristic of metal silicide, make to incide storage electricity
Light in appearance is all reflected by metal silicide layer, avoids incident light and enters mos capacitance electricity from the side wall of polycrystalline top crown
Lotus signal storage, so as to reduce the light source spurious response of memory node, ensure global exposing pixels unit storage capacitance
The accuracy of middle signal, prevent from storing the distortion of signal.Meanwhile first, second clearance for insulation having between metal silicide,
The short circuit generation between upper and lower pole plate can effectively be prevented.MOS is needed present invention can apply to 4T, 5T, 6T, 8T and 12T etc. are various
In the global pixel structure of storage capacitance, and can be mutually compatible with existing CMOS technology well, obtain imaging sensor
The image of high quality.
Above-described is only the preferred embodiments of the present invention, the embodiment and the patent guarantor for being not used to the limitation present invention
Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
- A kind of 1. preparation method of cmos image sensor overall situation pixel storage capacitance, it is characterised in that including：Step 1：One substrate is provided, forms the bottom crown of storage capacitance, the well region of top crown and metal-oxide-semiconductor, grid over the substrate Pole；Step 2：Insulation barrier is deposited, then, removes the upper surface of the top crown and the insulation barrier of side wall covering Layer, retains the top crown sidewall bottom and the insulation barrier with exterior domain；Step 3：The first metal silicide layer is deposited in the upper surface of the top crown and side wall, then, removes the top crown Sidewall bottom be located at below first metal silicide with the insulation barrier of exterior domain；Step 4：Abutment wall etching and source and drain injection are carried out to the storage capacitance and the metal-oxide-semiconductor, then, remove the storage The abutment wall of electric capacity；Step 5：Above the bottom crown on the outside of the insulation barrier of the storage capacitance, the source-drain area of the metal-oxide-semiconductor and The second metal silicide layer of deposit above grid, and first metal silicide is passed through institute in the top crown sidewall bottom Stating between insulation barrier and second metal silicide layer of the storage capacitance has clearance for insulation.
- 2. the preparation method of storage capacitance according to claim 1, it is characterised in that the substrate is that p-type or N-type serve as a contrast Bottom.
- 3. the preparation method of storage capacitance according to claim 1, it is characterised in that in step 2, using photoetching process, Being coated with, being exposed and developed for photoresist is carried out, to remove the photoresist of the upper surface of the top crown and side wall covering, then, The upper surface of the top crown and the insulation barrier of side wall covering are removed using dry or wet etch, is retained on described Pole plate sidewall bottom and the insulation barrier with exterior domain.
- 4. the preparation method of storage capacitance according to claim 1, it is characterised in that in step 3, using dry method or wet Method etching removes the insulation barrier covered beyond the side wall of the top crown, retains the institute of the top crown sidewall bottom State insulation barrier.
- 5. the preparation method of storage capacitance according to claim 1, it is characterised in that in step 4, using photoetching process, Being coated with, being exposed and developed for photoresist is carried out, to remove the photoresist of the storage capacitance region overlay, then, using dry method Or wet etching removes the abutment wall of the storage capacitance.
- 6. the preparation method of storage capacitance according to claim 1, it is characterised in that the insulation barrier be individual layer or Multilayer.
- 7. the preparation method of storage capacitance according to claim 6, it is characterised in that the insulation barrier is using two Silica, silicon nitride or silicon oxynitride one or more single or multiple lift barrier layers formed therein.
- 8. the preparation method of the storage capacitance according to claim 1,6 or 7, it is characterised in that the insulation barrier Thickness is 10~1000 angstroms.
- 9. the preparation method of storage capacitance according to claim 1, it is characterised in that second metal silicide layer Thickness is less than the thickness of the insulation barrier.
- 10. the preparation method of storage capacitance according to claim 1, it is characterised in that first metal silicide layer And/or second metal silicide layer is the metal silicide layer formed using titanium, cobalt or nickel.
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