JPS63173409A - Linear power amplifier - Google Patents

Abstract

PURPOSE:To realize the amplification with high efficiency without causing any switching distortion by introducing the digital processing in switching the power voltage of a power amplification stage according to the amplitude of an input signal in an amplifier amplifying the input signal while applying D/A conversion. CONSTITUTION:A digital input signal Sd is formed into an analog signal Sa after passing through a delay circuit 11 and fed to a power amplifier stage 15. Rectifier circuits 24, 25 output respectively positive/negative voltages VH, VL and -VL, VH. The MSB and 2SB of the signal Sd are fed to AND circuits 41, 51 for detecting the amplitude and AND outputs Sp, Sn are obtained. Since the signal Sd is an offset binary code, the relation between the value of the signal Sd and the amplitude of the signal Sa, the relation between the signals Sp, Sd and between the signals Sn, Sd are as shown in figure (a). In a switching circuit 31, a voltage VL or VH is supplied to a transistor Q1 as the operating voltage with Sp='0' and '1' and a switching circuit 32 is operated similarly with Sn='0' and Sn='1'. Thus, the voltage +VH or -VH is supplied to the amplifier stage 15 only with Sa>=4 and Sa<=-5. Moreover, since the voltage switching is not delayed with respect to the signal Sa in the amplifier stage 15 because of the intervention of the delay circuit 11, no distortion is caused at switching.

Description

[Detailed description of the invention] [Industrial application field] This invention relates to a linear power amplifier.

[Summary of the invention]

This invention provides a power amplifier that converts a digital input signal into an analog signal and linearly amplifies the power from C.
By introducing digital processing when switching the power supply voltage of the power amplification stage according to the amplitude of the input signal, highly efficient power amplification is achieved without deteriorating the characteristics.

[Conventional technology]

2. Description of the Related Art In a power amplifier that linearly amplifies the power of an input signal, for example, an audio power amplifier, there is a method of switching the power supply voltage according to the amplitude of the signal as a method for improving the power supply utilization rate.

FIG. 3 shows an example of this, where an input signal St is supplied to a speaker (2) through a power amplifier (1). Further, the signal Si is supplied to an amplitude detection circuit (3) to extract the absolute value Va of the amplitude of the signal Si, and this voltage Va is supplied to a voltage comparison circuit (4) and compared with a reference voltage Vr.
The comparison output is supplied to the switch circuit (5) as its control signal, and when Va≦V, r (at the time of small amplitude), a relatively low voltage vL is applied to the amplifier (11) through the switch circuit (5).
When Va>Vr (at the time of large amplitude), a relatively high voltage vH is supplied to the amplifier (11) as its operating voltage through the switch circuit (5).

Therefore, the power supply voltage of the amplifier (1) is switched to voltage vL or VH in accordance with the amplitude of the input signal Si, so that the power supply utilization rate at the time of small output is improved, and
Large output can be obtained.

[Problem that the invention seeks to solve]

However, in the above circuit, the switch circuit (5)
Since the switching of voltage VL+VH at is slightly delayed from the signal St to be amplified, distortion occurs at this time.

This invention attempts to solve these problems.

[Means for solving problems]

Therefore, in this invention, digital processing is introduced.

[Effect]

No distortion (and improves power utilization).

〔Example〕

In FIG. 1, the input signal Sd is from a CD player, DA
This is a digital signal from a digital signal tA (not shown) such as a T-player or satellite broadcasting, and for the sake of simplicity, in this example, it is assumed to be a 4-bit parallel offset binary code.

(10) indicates the main signal line, and the signal S
d is supplied to a delay circuit (11). In this case, the delay circuit (11) is composed of, for example, four serial input/series output shift registers corresponding to the number of bits of the signal Sd, and the delay circuit (11) is composed of four serial input/series output shift registers corresponding to the number of bits of the signal Sd.
This is a delay of m seconds.

Then, the signal Sd is delayed in the delay circuit (11) and then supplied to the D/A converter (12) to become an analog signal Sa.
3) and the power amplification stage (14) through the voltage amplification stage (14).
5) In this example, it is supplied to 5EPP-connected transistors Ql and Q2, and its amplified output is supplied to the speaker (16).

In addition, (20) indicates a power supply circuit, (21) a power plug that supplies commercial AC voltage, (22) a power switch, (23) a power transformer, (24), (25)
is a rectifier circuit. The output coil of the transformer (23) is provided with an intermediate tap, and a rectifier circuit (24) is configured by connecting diodes D1°D2 and a capacitor C11C2 to the hot side and intermediate tap of this output coil. A relatively high positive DC voltage V and a relatively low positive DC voltage vL are taken out from the circuit (24). Further, the output coil of the transformer (23) has a diode D3. D4 and capacitors C3 and C4 are also connected to form a rectifier circuit (25), from which a similar negative voltage -VL+VH is taken out.

The collector-emitter of the transistor Q3 is connected between the output terminal of the voltage V of the rectifier circuit (24) and the collector of the transistor Q1.
A resistor R1 is connected between the collector and the base of the resistor R1, and the collector and emitter of the transistor Q4 is connected between the base and the ground, and the output terminal of the voltage vL of the rectifier circuit (24) and the emitter of the transistor Q3 are connected between the base and the ground. Between,
A diode D5 is connected to configure a voltage VL+VH switching circuit (31).

Further, a switching circuit (32) having a transistor Qs, a Qe diode D6, and resistors R1 and R3 is similarly configured between the output terminal of the rectifier circuit (25) and the collector of the transistor Q2.

Furthermore, the MSB and 25
B is supplied to an AND circuit (41) for positive amplitude detection, and its AND output Sp is supplied to the base of transistor Q4 through a hold circuit (42) and an inverter (43). Further, the MSB and 2SB of the signal Sd are supplied to a negative logic AND circuit (51) for negative amplitude detection, and the AND signal Sn is supplied to the base of the transistor Q6 through a hold circuit (52). In addition, a hold circuit (42).

(52) has a fast rise and a slow fall.

According to such a configuration, since the signal Sd is a 4-bit offset binary code, the relationship between the signal SdO value and the amplitude of the signal Sa after D/A conversion is as shown in the first column ( left grip) and as shown in the second column. and,
In the signal Sp, both the MSB and 2SB of the signal Sd are 1"
Since the signal sp becomes "1" only when
n becomes a value as shown in the fourth column for the signal SdO value.

Then, in the switching circuit (31), SP-0''
At this time, transistor Q4 is turned on and transistor Q3 is turned off, so voltage vL is supplied to transistor Q1 as its operating voltage through diode D5. Furthermore, when SP="L", transistor Q4 is turned off and transistor Q3 is turned on, so voltage VH
is supplied to transistor Q1 as its operating voltage through transistor Q3. Note that at this time, the diode D5 is reverse biased and is off.

When Sn="0" and Sn="l", the switching circuit (32) operates in the same way, and the voltage -vL or -
VH is supplied to transistor Q2 as its operating voltage.

Therefore, as shown in FIG. 2, when the amplitude of the signal Sa is small (-4≦Sa≦3), the voltage +VL or -
vL is supplied to the power amplification stage (15), and a high voltage +VH or -V is supplied to the power amplification stage (15) only when the amplitude of the signal Sa is large (Sa≧4 r sa≦−5). High utilization of power supply voltage.

In this case, the switching circuits (31), (3
2) when switching the voltage ±vL+±V, the signal Sd
Although this signal Sd is delayed with respect to the amplitude indicated by
is delayed by the delay circuit (11) and then converted into the signal Sa, so there is no delay in switching the voltage ±VL+ ±V14 with respect to the signal Sa in the power amplification stage (15). No distortion or noise.

〔Effect of the invention〕

According to this invention, the power supply voltage of the power amplification stage (15) is switched to ±VH+±vL in accordance with the amplitude of the signal 5a (D), so the power supply utilization rate is high.Moreover, in this case, the voltage ±VL+± The input digital signal Sd is delayed by a time corresponding to the switching delay of V, and the delayed signal S
Since the signal d is converted into the signal Sa, no distortion or noise occurs during switching.

Further, there is no need to adjust the detection level of signal swing + pg, and there is no aging, resulting in stable operation. Furthermore, it can be integrated with a CD player or the like, resulting in low cost.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining the same. (lO) is the main signal system, (20) is the power supply circuit, (3
1), (32) are switching circuits, (41),
(51) is an amplitude detection circuit.

Claims (1)

[Claims] In a power amplifier that converts an input digital signal into an analog signal and linearly amplifies the power of this analog signal, the amplitude of the analog signal is detected from the input digital signal, and the amplitude of the analog signal is detected from the input digital signal. The voltage supplied to the power amplification stage that performs power amplification of the signal is switched in accordance with the amplitude of the analog signal, and a delay circuit is provided on the signal line of the input digital signal, and the digital signal is converted into the analog signal. is delayed by a time corresponding to the point in time when the voltage supplied to the power amplification stage is switched.