JPS63173371A - Insulated gate field-effect transistor high in breakdown voltage - Google Patents
Insulated gate field-effect transistor high in breakdown voltageInfo
- Publication number
- JPS63173371A JPS63173371A JP540987A JP540987A JPS63173371A JP S63173371 A JPS63173371 A JP S63173371A JP 540987 A JP540987 A JP 540987A JP 540987 A JP540987 A JP 540987A JP S63173371 A JPS63173371 A JP S63173371A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- layer
- gate insulating
- region
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015556 catabolic process Effects 0.000 title claims abstract description 15
- 230000005669 field effect Effects 0.000 title claims description 4
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 238000001020 plasma etching Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は、縦型構造の高耐圧絶縁ゲート型電界効果トラ
ンジスタ（以下高耐圧ＭＯ８ＦＥＴと称す。）において
、全ての電極を素子の表面から取出せ、且つ、素子の小
型化及び表面の平担化を図ることによって集積回路化に
適した構造の高耐圧ＭＯ３ＦＥＴ を得るものである
。[Detailed Description of the Invention] [Summary] The present invention provides a high breakdown voltage insulated gate field effect transistor (hereinafter referred to as a high breakdown voltage MO8FET) with a vertical structure, in which all electrodes can be taken out from the surface of the element, and By reducing the size of the MO3FET and flattening the surface, a high voltage MO3FET with a structure suitable for integrated circuits can be obtained.
本発明は、半導体装置の製造方法、特にその縦型構造の
高耐圧ＭＯ８ＦＥＴに関する。The present invention relates to a method for manufacturing a semiconductor device, and in particular to a high breakdown voltage MO8FET having a vertical structure.
従来の縦型高耐圧ＭＯ８ＦＥＴの構造を、その製造工程
の一例を参照して、第２図（３）〜（Ｆ）Ｋ説明する。The structure of a conventional vertical high voltage MO8FET will be explained with reference to an example of its manufacturing process in FIGS. 2(3) to 2(F)K.
第２図囚〜には、従来の高耐圧ＭＯ８ＦＥＴを製造工程
順に示す断面図である。FIGS. 2-2 are cross-sectional views showing a conventional high-voltage MO8FET in the order of manufacturing steps.
従来の高耐圧ＭＯ８ＦＥＴは先ず第２装置及び（Ｂｌに
示す様に、例えば＜ｉｏｏ＞面のｎ 型のシリコン層か
らなるドレイン領域１上に、ｎ−型のシリコン層からな
る耐圧層２及びｐ型のシリコン層からなるチャネル層３
をそれぞれエピタキシャル成長させる。In the conventional high voltage MO8FET, a second device and a drain region 1 (as shown in Bl), for example, an n-type silicon layer on the Channel layer 3 consisting of a molded silicon layer
are grown epitaxially.
次に、第２図（ｑの様に、例えばレジストからなる拡散
マスク５を形成し、その拡散窓５ａより、例えば砒素（
Ａｓ ）イオンを導入することによシ、ｎ 型のソース
領域４を形成する。Next, as shown in FIG. 2 (q), a diffusion mask 5 made of, for example, resist is formed, and arsenic (for example) is spread through the diffusion window 5a.
By introducing As) ions, an n-type source region 4 is formed.
次に拡散マスク５を除去した後、第２図（Ｄ）の様に、
例えば耐エツチング性の窒化膜からなる工、ツチングマ
スク６を形成し、例えばＫＯＨからなるアルカリ性の異
方性エツチング液によってエツチング窓６ａよシ、耐圧
層２にまで達するＶ溝７を形成する。Next, after removing the diffusion mask 5, as shown in FIG. 2(D),
For example, an etching mask 6 made of an etching-resistant nitride film is formed, and a V-groove 7 extending from the etching window 6a to the voltage-resistant layer 2 is formed using an alkaline anisotropic etching solution made of, for example, KOH.
次にエツチングマスク６を、除去した後、第２図口の様
に例えば通常の熱酸化法によって、表面に酸化シリコン
膜８を形成し、
次に第２図ＣＦ′ｌの様に、ソース領竣４上の酸化シリ
コン膜８上に図示しないエツチングマスクを使用してコ
ンタクト窓を開口した後、全面に例えばアルミニウム（
Ａ７）からなる電極材を形成し、そのパターンニングを
行なうことによって、ソース電極１０及びゲート電極９
を形成すると共に、下面のドレイン領域１上にドレイン
電極１１を形成するものである。Next, after removing the etching mask 6, a silicon oxide film 8 is formed on the surface by, for example, a normal thermal oxidation method as shown in the opening of FIG. After opening a contact window on the silicon oxide film 8 on the finished silicon oxide film 8 using an etching mask (not shown), for example, aluminum (
By forming an electrode material made of A7) and patterning it, the source electrode 10 and the gate electrode 9 are formed.
At the same time, a drain electrode 11 is formed on the drain region 1 on the lower surface.
上記した従来の高耐圧ＭＯ８ＦＥＴは、ゲート電極９を
、ソース領域４及びチャネル層３を介して耐圧層２にま
で達する■溝７の内部に設け、その動作を縦型とするこ
とによって素子の小型化を図ることが可能である。The conventional high-voltage MO8FET described above has a gate electrode 9 provided inside a trench 7 that reaches the breakdown voltage layer 2 via the source region 4 and channel layer 3, and its operation is vertical, resulting in a compact device. It is possible to achieve this goal.
しかし、耐圧層２け、第３図中、ａで示す様に、素子の
逆耐圧を向上させるために、比較的厚く形成されている
。However, the two breakdown voltage layers are formed relatively thick, as shown by a in FIG. 3, in order to improve the reverse breakdown voltage of the device.
そのため通常は、その間の抵抗値の増加を防止し、素子
のＯＮ抵抗を低減するために、第３図の様に、ドレイン
電極１１を素子の下面から取出していた。しかし、全て
の電極を、素子の表面から取出すことができないため、
この耐圧ＭＯ８ＦＥＴを集積回路中に組込むことが困難
であった。Therefore, in order to prevent the resistance value from increasing during that time and reduce the ON resistance of the element, the drain electrode 11 is usually taken out from the bottom surface of the element as shown in FIG. However, since it is not possible to take out all the electrodes from the surface of the element,
It was difficult to incorporate this high voltage MO8FET into an integrated circuit.
本発明は、上記した問題点に鑑み集積回路に適した構造
の耐圧ＭＯ８ＦＥＴを得るために、耐圧層の下部に埋込
層を設け、且つ素子の表面において所定の領域より埋込
層に連結される引出し領域を設け、更に、ゲート絶縁膜
が形成される溝の形状をＵ型とし、その内部においては
導電性物質を埋込むものである。In view of the above-mentioned problems, the present invention provides a buried layer under the breakdown voltage layer and connects to the buried layer from a predetermined region on the surface of the element, in order to obtain a breakdown voltage MO8FET with a structure suitable for integrated circuits. Furthermore, the groove in which the gate insulating film is formed has a U-shape, and a conductive material is buried inside the groove.
本発明の高耐圧ＭＯ８ＦＥＴは、耐圧層の下部に埋込層
を設け、更に基板表面より、埋込層にまで達する引出し
領域が設けられているため、低いＯＮ抵抗でドレイン電
極を、素子の表面から取出すことが可能である。また、
本発明の高耐圧ＭＯ８ＦＥＴ は、ゲート絶縁膜が形成
される溝の形状をＵ型としているため、例えドレインの
引出領域を設けたとしても前記した従来例に比べて素子
の高密度化を図ることができ、更に溝の内部におりては
、ゲート絶縁膜を介して、導電性物質が埋込まれている
ため、表面の平担化が可能である。The high-voltage MO8FET of the present invention has a buried layer below the voltage-resistant layer, and is further provided with a lead-out region that reaches from the substrate surface to the buried layer. It is possible to take it out from. Also,
In the high voltage MO8FET of the present invention, the groove in which the gate insulating film is formed has a U-shape, so even if a drain extraction region is provided, the device can be densely packed compared to the conventional example described above. Furthermore, since a conductive material is buried inside the trench via the gate insulating film, the surface can be made flat.
以下、本発明の高耐圧ＭＯ８ＦＥＴの一実施例を第１図
（Ａｔ −（Ｅ（ｌを参照して詳細に説明する。第１図
（Ａ）〜Ｈは、本実施例を製造工穆順に示す断面図であ
る。Hereinafter, one embodiment of the high voltage MO8FET of the present invention will be explained in detail with reference to FIG. 1 (At-(E(l). FIG.
本実施例は先ず第１図ｆＡ）の様に、例えば、ｐ型のシ
リコン釜飯１２上Ｋｎ＋型の埋込層Ｂを形成し、更に、
その上部に、例えばＣＶＤ法によって、ｎ−型シリコン
の耐圧層１４を形成する。In this embodiment, as shown in FIG. 1fA), for example, a Kn+ type buried layer B is formed on the p-type silicon pot 12, and further,
On top of this, a breakdown voltage layer 14 of n-type silicon is formed by, for example, the CVD method.
次に、第１図（Ｂ）の様に、表面に例えばレジストから
なる拡散マスク１６を形成した後、その拡散窓１６ａよ
り、例えばホウ素（Ｂｌイオンを注入することによって
、ｐ型のチセネル佃塘１５ｆ形成する。Next, as shown in FIG. 1B, after forming a diffusion mask 16 made of, for example, a resist on the surface, by implanting, for example, boron (Bl) ions through the diffusion window 16a, a p-type chisenel Form 15f.
次に第１図（ｑの様に、新たに例えばレジストからなる
拡散マスク１８を設けた後、その拡散窓１８ａより、例
えば砒素（Ａｓ）イオンを注入することによって、ｎ＋
型のソース餠峻１７を形成する。Next, as shown in FIG. 1(q), after newly providing a diffusion mask 18 made of, for example, resist, by implanting, for example, arsenic (As) ions through the diffusion window 18a, n+
Form a sauce mold 17.
次に、第１図（Ｄ）の様に、新たに例メばレジストから
なる拡散マスク２０を形成した後、その拡散窓２０ａよ
り、更に、例えば砒素（Ａｓ）イオンを注入し、ｎ＋型
の引出し領域１９を形成する。Next, as shown in FIG. 1(D), after forming a new diffusion mask 20 made of, for example, resist, for example, arsenic (As) ions are further implanted through the diffusion window 20a to form an n+ type. A drawer area 19 is formed.
次に、第１図ｃＥ）の様に、表面に例えば、通常の熱酸
化法によって、酸化シリコン膜２１を形成した後、その
所定の箇所に、エツチング窓２１ａを形成し、次いで例
えば反応性イオンエツチング（ＲＩＥ）を施すことによ
って、ソース領域１７チヤネル領域１５を介して耐圧Ｎ
１４にまで達するＵ溝２２を形成する。Next, as shown in FIG. 1 cE), after forming a silicon oxide film 21 on the surface by, for example, a normal thermal oxidation method, an etching window 21a is formed at a predetermined location, and then, for example, reactive ion is etched. By performing etching (RIE), the breakdown voltage N is increased through the source region 17 and the channel region 15.
A U groove 22 reaching up to 14 is formed.
次に、第１図［Ｆ］の様に、熱処理を施すことによって
、Ｕ溝２２の内面に酸化シリコン膜２３を形成した後、
全面に例えば通常のＣＶＤ法によって、例えばポリシリ
コン２４を形成する。Next, as shown in FIG. 1 [F], a silicon oxide film 23 is formed on the inner surface of the U-groove 22 by heat treatment.
For example, polysilicon 24 is formed on the entire surface by, for example, a normal CVD method.
次に、第１図（０の様に、全面に例えばスパッタエツチ
ングを施すことによってＵ溝２２中にのみ、ポリシリコ
ン２４を埋込み、次いでソースｆＪｊｔ１７、引出し領
＃１９上の酸イビシリコン膜２１に１コンタクト窓を開
口した後、全面に例えばアルミニウム（Ａｎからなる電
極材を形成し、そのパターンニングを行なうことにより
、ゲート電極２５、ソース電極２６、ドレイン電極２７
を形成するものである。Next, as shown in FIG. 1 (0), polysilicon 24 is buried only in the U groove 22 by performing sputter etching on the entire surface, and then the oxidized bisilicon film 21 on the source fJjt17 and the lead-out region #19 is filled with polysilicon 24. After opening the contact window, an electrode material made of, for example, aluminum (An) is formed on the entire surface and patterned to form the gate electrode 25, the source electrode 26, and the drain electrode 27.
It forms the
上記の様にして形成された本実施例の高耐圧ＭＯ８ＦＥ
Ｔは耐圧層１４の下部に、ｎ＋型の埋込層が形成され、
且つ、素子の表面より埋込層１４にまで達するｎ＋型の
引出し領域１９が設けられているため、低いＯＮ抵抗で
ドレイン電極を素子の表面から取出すことが可能である
。また、ゲート絶縁膜（酸化シリコン膜２３）が形成さ
れる溝は、その形状が反応性イオンエツチング（ＲＩＥ
）によってＵ型に形成されており、更にその内部には、
ゲート絶縁膜を介してポリシリコン２４が埋込ま婢
れているため、素子の小型化及び平挿化が図られる。High voltage MO8FE of this example formed as described above
T is an n+ type buried layer formed under the breakdown voltage layer 14,
In addition, since the n+ type extraction region 19 is provided that reaches the buried layer 14 from the surface of the element, it is possible to extract the drain electrode from the surface of the element with low ON resistance. Furthermore, the shape of the groove in which the gate insulating film (silicon oxide film 23) is formed is etched by reactive ion etching (RIE).
) is formed into a U-shape, and inside it,
Since the polysilicon 24 is embedded through the gate insulating film, the device can be made smaller and can be installed horizontally.
々卦、拡散層１５及び１７の形成は、第１図（０〔発明
の効果〕
以上、述べた様に、本発明の高耐圧ＭＯ８ＦＥＴは全て
の電極を、素子の表面から取出せ、また、素子の小型化
、及び表面の平担化が可能であるため集積回路中に組込
むに適した構造となる。The formation of the diffusion layers 15 and 17 is shown in FIG. Since the structure can be made smaller and the surface can be flattened, the structure is suitable for being incorporated into an integrated circuit.
第１図は、本発明による高耐圧ＭＯ８ＦＥＴの実施例を
説明する図、第２図は、従来の耐圧ＭＯ８ＦＥ″ｒｆ説
明する図、第３図は、従来技術の問題点を説明する図で
ある。
図において、１はドレイン領堵、２及び】４は耐圧層３
及び１５はチャネル領域、４及び１７はソース領域、５
，１６．１８及び２０け拡散マスク、５ａ、 １６ａ、
１．８ａ、及び２０ａは拡散窓、６はエツチングマス
ク、６ａ及び２１ａはエツチング窓、７は■溝、８．２
１及び２３は酸化シリコン膜、９及び２５￥′ｉゲート
ｉｆｔ極、１０及び２６はソース電極、１１及び２７は
ドレイン電極、１２はシリコン基板、１３は埋込層、２
４はポリシリコンであ（、Ｑ）
（Ｂ）
第 ２ ■
（Ｅ）
理水の高耐圧ＭＯδＦＥＴ
第 ２ 刀FIG. 1 is a diagram illustrating an embodiment of a high voltage MO8FET according to the present invention, FIG. 2 is a diagram illustrating a conventional voltage MO8FE″rf, and FIG. 3 is a diagram explaining problems in the prior art. In the figure, 1 is the drain region, 2 and ]4 are the withstand voltage layer 3.
and 15 are channel regions, 4 and 17 are source regions, and 5
, 16.18 and 20 diffusion masks, 5a, 16a,
1.8a and 20a are diffusion windows, 6 is an etching mask, 6a and 21a are etching windows, 7 is a groove, 8.2
1 and 23 are silicon oxide films, 9 and 25\'i gate ift electrodes, 10 and 26 are source electrodes, 11 and 27 are drain electrodes, 12 is a silicon substrate, 13 is a buried layer, 2
4 is polysilicon (,Q) (B) 2nd ■ (E) Risui's high voltage MOδFET 2nd sword
Claims (1)
型のチャネル領域と、該チャネル領域中に一導電型のソ
ース領域が設けられ、更に該チャネル領域及びソース領
域を介して該耐圧層にまで達する溝が形成され、少なく
ともその内部においては、ゲート絶縁膜が設けられてな
る耐圧絶縁ゲート型電界効果トランジンタにおいて、 該耐圧層の下部に一導電型であって、高不純物濃度の埋
込層が設けられ、 表面の所定の領域より、該埋込層に連結されてなる一導
電型であって高不純物濃度の引出し領域が設けられ、 該ゲート絶縁膜が形成される溝の形状をＵ型とし、その
内部においてはゲート絶縁膜を介して導電性物質が埋込
まれてなることを特徴とする高耐圧絶縁ゲート型電界効
果トランジスタ。[Claims] A channel region of one conductivity type and an opposite conductivity type is provided in a low impurity concentration breakdown voltage layer, and a source region of one conductivity type is provided in the channel region, and the channel region and the source region are provided in the channel region. In a voltage-resistant insulated gate type field effect transistor, in which a groove reaching the voltage-resistant layer is formed through a region, and a gate insulating film is provided at least inside the trench, the transistor is provided with a gate insulating film of one conductivity type below the voltage-resistant layer. , a buried layer with a high impurity concentration is provided, a lead-out region of one conductivity type and with a high impurity concentration is provided connected to the buried layer from a predetermined region of the surface, and the gate insulating film is formed. A high breakdown voltage insulated gate type field effect transistor, characterized in that the trench has a U-shape, and a conductive material is buried inside the trench with a gate insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP540987A JPS63173371A (en) | 1987-01-13 | 1987-01-13 | Insulated gate field-effect transistor high in breakdown voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP540987A JPS63173371A (en) | 1987-01-13 | 1987-01-13 | Insulated gate field-effect transistor high in breakdown voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63173371A true JPS63173371A (en) | 1988-07-16 |
Family
ID=11610348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP540987A Pending JPS63173371A (en) | 1987-01-13 | 1987-01-13 | Insulated gate field-effect transistor high in breakdown voltage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63173371A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434435A (en) * | 1994-05-04 | 1995-07-18 | North Carolina State University | Trench gate lateral MOSFET |
| DE19620021A1 (en) * | 1995-05-19 | 1996-11-21 | Nissan Motor | U=shaped trench MOS semiconductor power transistor device |
| KR100230741B1 (en) * | 1996-10-29 | 1999-11-15 | 김영환 | High voltage semiconductor device and method of manufacturing the same |
| US6037633A (en) * | 1996-11-01 | 2000-03-14 | Nissan Motor Co., Ltd. | Semiconductor device |
| JP2005508083A (en) * | 2001-10-30 | 2005-03-24 | ゼネラル セミコンダクター，インク． | Trench double-diffused metal oxide semiconductor device with improved drain contact |
| JP2006303084A (en) * | 2005-04-19 | 2006-11-02 | Denso Corp | Silicon carbide semiconductor device |
| JP2008166775A (en) * | 2006-12-27 | 2008-07-17 | Dongbu Hitek Co Ltd | Semiconductor element and manufacturing method thereof |
| KR20130098913A (en) * | 2012-02-28 | 2013-09-05 | 세이코 인스트루 가부시키가이샤 | Semiconductor device and method for manufacturing the same |
-
1987
- 1987-01-13 JP JP540987A patent/JPS63173371A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434435A (en) * | 1994-05-04 | 1995-07-18 | North Carolina State University | Trench gate lateral MOSFET |
| DE19620021B4 (en) * | 1995-05-19 | 2005-06-02 | Nissan Motor Co., Ltd., Yokohama | Semiconductor device of the trench type |
| DE19620021A1 (en) * | 1995-05-19 | 1996-11-21 | Nissan Motor | U=shaped trench MOS semiconductor power transistor device |
| US5682048A (en) * | 1995-05-19 | 1997-10-28 | Nissan Motor Co., Ltd. | Groove-type semiconductor device |
| KR100230741B1 (en) * | 1996-10-29 | 1999-11-15 | 김영환 | High voltage semiconductor device and method of manufacturing the same |
| US6037633A (en) * | 1996-11-01 | 2000-03-14 | Nissan Motor Co., Ltd. | Semiconductor device |
| JP2005508083A (en) * | 2001-10-30 | 2005-03-24 | ゼネラル セミコンダクター，インク． | Trench double-diffused metal oxide semiconductor device with improved drain contact |
| JP4660090B2 (en) * | 2001-10-30 | 2011-03-30 | ゼネラル セミコンダクター，インク． | Trench double diffused metal oxide semiconductor device with improved drain contact |
| JP2006303084A (en) * | 2005-04-19 | 2006-11-02 | Denso Corp | Silicon carbide semiconductor device |
| JP2008166775A (en) * | 2006-12-27 | 2008-07-17 | Dongbu Hitek Co Ltd | Semiconductor element and manufacturing method thereof |
| KR20130098913A (en) * | 2012-02-28 | 2013-09-05 | 세이코 인스트루 가부시키가이샤 | Semiconductor device and method for manufacturing the same |
| JP2013179171A (en) * | 2012-02-28 | 2013-09-09 | Seiko Instruments Inc | Semiconductor device and manufacturing method of the same |
| CN103295910A (en) * | 2012-02-28 | 2013-09-11 | 精工电子有限公司 | Semiconductor device and method of manufacturing the same |
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