JPS63173363A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent current concentration caused by nonuniformity of contact resistance due to stress concentration generated in GTO, by arranging a very shallow groove part on the gate electrode side of a silicon substrate, vapor-depositing a gate electrode such as Al on the Si substrate surface on which the groove is formed, and burying a metal for the groove part gate electrode at the time of pressuring. CONSTITUTION:Firstly, a four-layered Si substrate of PNPN is formed, the surface the four- layered Si substrate is covered with a photoresist film, and its groove part only is eliminated. Then the vicinity of a part just under the periphery of a contact plate 6 is eliminated to a depth of about 5-15mum by etching and the like. Gate electrode formation in the following process can be performed only by vapor-depositing Al and the like of 10-15mum thick, and eliminating unnecessary part by applying a photoresist film. By arranging grooves, as shown by point P and Q, in the vicinity of a part just under the periphery of a contact plate 6, deformation and transfer of a gate electrode 5 due to pressure at the time of pressuring are enabled. Stress concentration, generated in the gate electrode 5 and the Si substrate in the vicinity of a part just under the periphery of the contact plate 6, can be reduced. Therefor, current concentration caused by nonuniformity of contact resistance due to stress concentration can be prevented, and the gate electrode can be prevented from cutting and alloying.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a large power capacity gate turn-off thyristor (
The present invention relates to a gate electrode structure of a gate electrode (hereinafter referred to as GTO), and particularly relates to a center gate type gate electrode structure.

(Prior Art) The blocking voltage and maximum turn-off current of GTOs have increased rapidly in recent years, and GTOs with withstand voltages on the order of several KV and several KA have been developed. In particular, the maximum turn-off current has been rated at 2500 A due to progress in elucidating the turn-off mechanism and optimization of the impurity concentration profile.
Class products are commercially available.

Under such circumstances, a large off-gate current is required to be sucked out from the gate at the time of gate turn-off, and the peak value exceeds 50 OA. Therefore, importance has been placed on gate electrodes that can efficiently draw current and have a highly reliable structure.

Broadly speaking, there are two methods for electrically connecting the gate electrode on the large-capacity GTO pellet and the gate terminal of the envelope.

One method is called a ring gate, in which a gate electrode formed of aluminum (hereinafter referred to as AN) around the GTO pellet is connected to an external lead wire by bonding or the like.

The other one is called a center gate according to the present invention.

Compared to the bonding method, this center gate type has advantages such as no breakage due to bending of the bonding wire, no time required for the bonding process, and easy assembly, so this center gate type has become mainstream. It's coming.

However, although the center gate type has the above-mentioned advantages, it may cause problems in terms of the life span, which is extremely important for semiconductor devices.

The problem is described using the diagram below.

FIG. 3 is an enlarged view of the vicinity of the center of GT◯ made using the conventional technique. 1 is a GT consisting of four layers of P, N, P, and N.
○It is a pellet. Although not shown in the figure, the same can be applied to a so-called anode short-circuit type GTO pellet in which the P emitter and N base on the anode side are partially shorted. Reference numeral 2 denotes an anode electrode, and 3a and 3b are metals such as i, which are made of a cathode salt and conduct a cathode current. Reference numeral 9 denotes a slit insulator tube made of ceramic or the like to prevent a short circuit between the gate lead wire 7 and the stamp.This is not only for insulation, but also for delivering the pressing force of the ring-shaped leaf spring 12, which will be explained below, to the contact plate 6. It also serves as a means. 1
0 is an insulating plate whose purpose is to prevent the gate lead wire from electrically contacting the upper metal plate 11. Reference numeral 11 denotes a pressure equalizing support plate made of hard metal that distributes the force so that the pressing force of the leaf spring 12 is concentrated only in a corresponding part of the center of the spring and is not transmitted to the lower insulating plate 10. Reference numeral 12 denotes an annular spring for bringing the contact plate 6 and gate electrode 5 into strong contact. The force of this spring passes through the pressure equalizing support plate 11 → insulating plate 10 → insulator tube 9, and connects the contact plate 6 to the gate electrode 5.
to press against. 13 is located above the annular spring 12,
This is a pressure equalizing support plate provided so that the central part of the annular spring 12 does not sink into the stamp 8.

The configuration of the conventional GTO has been described in detail above, but when operating this GTP, a pressure of about 300 to 400 kg/d is applied from both sides of the anode electrode 2 and the metal stamp 80 on the cathode side to turn the current on and off. . Also, a pressure of around 100 kg/cJ is applied to the contact plate 6.
As already mentioned, if the gate is operated for a long time with a large current of several hundred amperes flowing through the gate, the gate electrode 5 directly under the end of the contact plate 6 will disappear as if scattered, as shown in FIG. A groove-like shape with uneven width and depth may occur (point P), or the contact plate 6, gate electrode 5, and semiconductor substrate (Si) may become alloyed (point Q), or cracks may occur in the Sl. This may occur. These accidents are thought to result from an increase in gate current density due to a decrease in the thickness of the gate electrode -> heat generation -> wire breakage -> turn-off failure. On the other hand, in the case of alloyed parts, cracks occur → joint failure → breakdown voltage failure (device destruction), all of which are important problems.

The present invention was devised in view of this problem and is a solution to the above problem, but before describing it, an estimation of the mechanism by which the above problem occurs will be described.

Although there is no known literature on the mechanism by which the above-mentioned problems occur since the development of large-capacity GTOs is short, there are no known documents, but considering the failure state, the following may be considered. One of the problems is that a large number of voids are generated in the gate electrode, for example, Aρ, which ultimately leads to the formation of a groove and then to a disconnection. In this case, electromigration may be considered, but in order for this phenomenon to occur easily, the current flowing through i must have a high density and be at a high temperature. Further, for alloying, it is necessary that the temperature is high.

However, it is thought that there were conditions for high temperatures in both cases. Furthermore, conditions of high current density lead to localized heat generation, so there is a strong relationship between the two. From the above point of view, assuming that the heat generation factor is high current density (current concentration), the following two points are thought to cause current concentration. One of these cases is when the contact resistance between the gate electrode and the contact plate is different between the periphery and the center of the contact plate, and the contact resistance in the periphery where the failure is located is lower than that in the center, and the current distribution is biased toward the periphery. An example of how this can occur is stress non-uniformity occurring in the contact between the contact plate 6, gate electrode 5, and Si during pressurization. FIG. 5(a) is an enlarged view of the vicinity of the gate electrode in FIG. 3. When pressure is applied under this condition, the internal stress generated near the surface of Si (A') becomes as shown in Fig.
101433). In other words, high stress is concentrated in the periphery. This means that AQ on Si is also plastically deformed and receives a similar force. As a result, as shown in FIG. 6, it is thought that the higher the stress, the better the contact, and the lower the contact resistance r.

The idea is that this non-uniformity in contact resistance creates current imbalance, creating areas with high current density around the contact resistance, causing heat generation and, in some cases, electromigration.

The other reason is that the gate electrode shown in Figure 5 (, ) is an extremely thin film with a thickness of usually around 10 lines, so there is lateral resistance and the flow from the gate electrode to the contact plate occurs in the peripheral area of the contact plate. The idea is that heat generation occurs due to current concentration. One way to examine the validity of this idea is to divide the contact plate from the center to the outer periphery into n pieces as shown in Figure 7, and then calculate the lateral resistance per unit volume of the i-electrode as R=R2=. ... = R, 1, Assuming that the contact resistance between AQ and the contact plate is l"1: r, ... = rn, draw it as shown in Figure 8, and use this as an etc. circuit to calculate each branch current. If jLit-4z...J- is found experimentally, the distribution will be as shown in Figure 9.Here, n=7,
The parameters are expressed as a ratio between the lateral resistance R and the contact resistance r.

The vertical axis is the percentage of branch current to the total gate current NGO.

The conclusion from this figure is that if the ratio K (= r / R) of both resistances is 1 or less, the current will concentrate only directly under the periphery of the contact plate, and even in the region of 1 < K < 10, there will be a clear current non-current. It turns out that it is in equilibrium. The branch current flows evenly, preventing current concentration.
It is. In other words, in cases where the contact resistance r is extremely high and the lateral resistance R can be ignored, if the contact resistance r is that high, the forward voltage drop at that point increases and the off-gate current peak value is also suppressed. This is an unlikely condition because it would increase the pressure. Therefore, it is generally considered that current concentration occurs.

The two modes of current concentration have been described above as factors for heat generation, but even if concentration occurs due to one cause or both occur simultaneously and concentration is promoted, the conventional problem of GTO can be solved. In order to do this, it was necessary to remove the current concentration mode mentioned above. In view of this point, the present invention will be described in detail below.

(Problems to be solved by the invention) The present invention has been made in view of the above-mentioned problems.
It is an object of the present invention to provide a semiconductor device that can prevent current concentration caused by non-uniform contact resistance due to stress concentration occurring in the semiconductor device, and can prevent cutting and alloying of a gate electrode.

[Structure of the invention]

(Means for solving problems) The present invention is one of the above-mentioned current concentration generation modes.

This was done with attention to stress concentration, and the purpose is to alleviate the stress concentration that occurs in the gate electrode 5 and the Si substrate immediately below the periphery of the contact plate 6. in particular,
An extremely shallow groove is provided on the gate electrode side of the Si substrate, and a gate electrode made of Al1 or the like is deposited on the surface of the Si substrate with this groove, so that when pressure is applied, the groove gate electrode metal is buried. A cross-sectional view when pressurized is shown in FIG.

(Function) The function of the present invention is to provide a groove in a part of the Si substrate 1 as shown in FIG. 1, which has the effect of dispersing stress. If grooves are provided near the periphery of the contact plate 6 as shown at points P and Q in FIG. 1, the gate electrode 5 can be deformed and moved by the pressure when pressurized.

(Example) As mentioned in the previous section, the present invention first consists of a four-layer S of PNPN.
After forming the i-substrate, as in one embodiment shown in FIG.
15/ffi depth is removed.

This method of partially etching the Si substrate is widely known, so the process diagram is omitted, but the point is to cover the surface of the four-layer Si substrate with a photoresist film, remove only the groove forming part, and then remove the Si substrate. Partially etched. To form the gate electrode in the subsequent step, A11 or the like may be deposited to a thickness of 10 to 15p, and unnecessary portions may be removed using a photoresist film in the same manner as described above. Therefore, the present invention can be easily processed without much difference from conventional manufacturing processes. FIG. 2 shows another embodiment of the present invention, in which the contact plate has a large diameter and is donut-shaped (annular contact plate),
In this case, the idea of the center line is the outer radius R of the contact plate.
Suppose that it is located at the middle Q,,Q2 between □ and the inner radius R2.

Therefore, there are four ends, two at each end.

Four grooves are formed correspondingly.

〔Effect of the invention〕

This invention prevents current concentration caused by uneven contact resistance due to stress concentration caused by conventional technology by adding one step to the technology used to manufacture conventional GT○, and prevents cutting and alloying of the gate electrode. This is to prevent the result,
This is a useful patent that significantly increases reliability.

[Brief explanation of the drawing]

Fig. 1 is an enlarged cross section of a part of the center of a center gate type GTO using the present invention, Fig. 2 is a sectional view showing another embodiment of the present invention, and Fig. 3 is an actual center gate type GTO according to the present invention. Figure 4 is a diagram of the cross-sectional structure of the GTO. Figure 4 is a schematic diagram of the fracture of the GTO. Figure 5 is a stress distribution diagram of the Si substrate during pressure contact. Figure 6 is a hypothetical diagram of the stress distribution and contact resistance distribution of the Si substrate. , FIG. 7 is a structural diagram showing a model of electrical resistance of the gate contact portion, FIG. 8 is a circuit diagram showing an equivalent circuit of FIG. 7, and FIG. 9 is a current measurement diagram of the circuit of FIG. 8. DESCRIPTION OF SYMBOLS 1... Semiconductor base 2... Anode electrode 3a, 3b... Cathode electrode 4a, 4
b...Temperature compensation plate 5...Gate electrode 6
...Contact plate 7...Gate leader line 8.
...Stamp 9...Insulator tube 10...
Insulating plate 11.13...Metal plate 12...
leaf spring. Agent Patent Attorney Nori Chika Yudo Kikuo Takehana

Claims (4)

[Claims] (1) A first contact electrode plate through which a main current flows through the main surface of the semiconductor substrate, a first electrode layer connected to this, a second contact electrode plate through which a current to control the main current flows, and this The semiconductor substrate has a second electrode layer connected to the semiconductor substrate, and the second contact electrode plate is located approximately at the center of the semiconductor substrate, and the second contact electrode plate is located directly below the outer peripheral edge of the second contact electrode plate. A concave portion is provided in the substrate, and a second electrode layer including the concave portion is formed to prevent nonuniformity of stress generated in the second contact electrode plate, the second electrode layer, and the semiconductor substrate during pressurized contact. A semiconductor device characterized by: (2) A semiconductor device according to claim 1, comprising first and second contact electrode plates on two main surfaces of a semiconductor substrate, and first and second electrode layers connected thereto. (3) The semiconductor device according to claim 1, wherein the semiconductor substrate is a gate turn-off thyristor. (4) The semiconductor device according to claim 1, wherein the recess provided in the semiconductor substrate has an annular shape.