JPS63173297A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To heighten integration degree, by dividing a cell array area in a direction orthogonal to the extending direction of a word line, reducing the size of a divided cell array area in the extending direction of the word line by reducing the word line, and setting a second peripheral circuit area in the divided cell array area. CONSTITUTION:The cell array area is divided into three divided cell array areas 12a, 12b, and 12c in the long side direction of a substrate 11. The central divided cell array area 12b is miniaturized by forming the word line extending in a short side direction of the substrate 11 and not shown in figure, smaller than the divided cell array areas 12a and 12c at both sides, and the size in a short side direction is formed smaller th an the divided cell array areas 12a and 12c. The second peripheral circuit area 14 is arranged on the substrate 11 at the both sides in the short side direction of the central divided cell array area 12b, and a signal required for the cell array area is generated by a circuit provided in the area, and it is connected to each divided cell array area with a signal line 23.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor memory devices, and in particular, to distributing peripheral circuit areas to reduce signal delay and improve characteristics without increasing the chip area. The present invention relates to a fully developed semiconductor memory device.

[Conventional technology]

In a conventional semiconductor memory device, a cell array region consisting of a regularly repeating pattern in which a plurality of memory cells connected to mutually orthogonal bit lines and word lines are arranged in rows and columns is located approximately at the center of a semiconductor substrate. It is known that a peripheral circuit area having an irregular pattern is provided on both sides of the cell array area.

FIG. 3 is a layout diagram of each region on a semiconductor substrate in a conventional semiconductor memory device.

One of the reasons for this arrangement is that the width of the package in which the semiconductor memory device is mounted cannot be made larger in the short side direction than in the long side direction.

However, in such a semiconductor memory device, the signal lines for signals required in the cell array area (for example, No. t5 Iw for charging the decoder, etc.) (23) are
If the arrangement is such that it traverses from the peripheral N-path region (13) to the cell array region (12) and in the entire long side direction within the cell array region, its length becomes extremely long. For this reason, even if the signal line is made of a low-resistance joint made of aluminum or the like, the signal delay caused by the host resistance at the far end is too large to ignore, and the semiconductor memory device There was a drawback that there was a risk that the characteristics would be affected. Moreover, as the patterns in semiconductor memory devices become finer in the future, the above-mentioned problem will continue to increase.
Become something.

Therefore, as a semiconductor memory device which solves this drawback, the one shown in FIG. 4 or FIG. 5 is known. Note that the same parts as in FIG. 3 are numbered 4- and their explanation will be omitted.

The device shown in FIG. 4 has a second peripheral circuit area (14) along the long side of the semiconductor memory device. With this arrangement, necessary signals within the cell array area can be The length of the signal line (23) can be shortened, but
Since the second peripheral circuit area is likely to become larger in the short side direction, the second peripheral circuit area must be made extremely small in the short side direction.

On the other hand, what is shown in FIG. 5 is a cell array area (12).
A second peripheral circuit area (14) is provided in between, and the signal delay at the far end of the signal line (23) is approximately half that of the semiconductor memory device shown in FIG. be able to. However, in the semiconductor memory device shown in FIG. 5, the signal lines for signals required within the array area do not cross within the second peripheral circuit area (14); Signal line arrangement if! : Make it complicated.

[Problem that the invention seeks to solve]

In this way, the semiconductor notation shown in FIGS. 4 and 5 above (: indicates that even during manufacturing, various restrictions are imposed on the second peripheral circuit area provided to prevent signal delays, respectively. There was a problem.

[Means for solving problems]

The present invention has been made with the aim of solving both the above-mentioned problems and drawbacks. a cell array region comprising nine regularly repeated patterns in which a plurality of memory cells connected to the word line and the bit m extending in the long side direction are arranged in a matrix; and a cell array region located on both sides of the cell array region in the long side direction. a peripheral circuit area having an irregular pattern, in which the cell array area is divided in the long side direction to set a plurality of divided cell array areas, and at least one divided cell array area; A substrate on at least one side in the short side direction of the divided cell array region in which the dimension in the short side direction is reduced by making the word line shorter than the word line in the other divided cell array region, and the dimension in the short side direction is reduced. It is characterized in that a second peripheral circuit area t-, which is made of an irregular pattern, is set on the top.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows an embodiment of a semiconductor memory device according to the present invention, and is a layout diagram of each region on a semiconductor substrate. It should be noted that the same parts as in the conventional example shown in FIG.

As shown in the figure, the cell array area (12) is located on the substrate (1).
1) Three divided cell array areas (12a) in the long side direction
, (12b), and (12c). The central divided cell array region (12b) is made shorter than the divided cell array regions (12a) and (12c) on both sides of the word line (not shown) extending in the short side direction of the substrate (11). The size is reduced in the side direction, and the dimension in the short side direction is smaller than the divided cell array regions (12a) and (x2c) on both sides. A second peripheral circuit area (14) is arranged on the substrate (11) on both sides of the central divided cell array area (12b) in the short side direction, and the circuit provided in this area provides necessary space for the cell array area. A signal is created and the signal line (
23), each divided cell array area is covered.

Nasp, (21a), (21b), (21c) Fi each divided cell array area (12a), (12b), (12c)
Sareta row Tecota arranged in the long side direction, similar to K (22
a), (22b) 1 (22c) are each divided cell array area (12a), (12b).

(12C) represents column decoders arranged in the short side direction.

Next, the operation of this embodiment will be explained.

In this semiconductor memory device, the second peripheral circuit area (
14) can be placed almost in the center of the cell array area, so the signal line (23)' for the signal required within the cell array area can be shortened, and the signal delay at the far end of the signal line can also be reduced. With small size, the characteristics can be improved.

Further, the second peripheral circuit area (14) has the cell array area (12) t-divided dimension (or the number of divided cell array areas (12a), (12b), (12c)) and the central divided cell array area ( 12b) By appropriately determining the length of the word line, the area can be minimized and the degree of integration can be improved.

Furthermore, since the second peripheral circuit area (14) is arranged in nine divided cell array areas (12b), there is a risk that the signal line in the cell play area and the signal line in the second peripheral circuit area may cross each other. It is easy to design.

[Embodiment 2] FIG. 2 is a layout diagram of each region on a semiconductor substrate showing a second embodiment of the present invention. The same parts as in the embodiment shown in FIG. The explanation will be omitted.

The embodiment shown in FIG. 2 is a case where the semiconductor memory device shown in FIG. 1 has a larger dimension in the long side direction. As the dimension in the long side direction of the semiconductor memory device increases in this way, the second peripheral circuit area (14) is placed almost in the center of the T-cell array area. ), the effect of the present invention cannot be fully exerted because the portion extending in the long side direction becomes long.

Therefore, as shown in FIG. 2, the second peripheral circuit area (14) is also divided into two parts, and each is divided into two parts, W! Set up 1 and signal! (23
) is prevented from increasing in length.

〔Effect of the invention〕

As explained above, the semiconductor memory according to the present invention
In the case of direct alignment, the cell array area is divided into a plurality of divided cell array areas in a direction perpendicular to the extending direction of the word line, and at least one divided cell array area is shortened in the word line extension direction. Since the size of the cell array area is smaller and the second peripheral circuit area is set on at least one side of this divided cell array area, the length of the signal line required in the cell array area can be shortened. It becomes possible to increase the degree of integration by fully determining the dimensions of the divided cell array area and effectively utilizing the substrate, regardless of the size. Furthermore, the arrangement of signals within the second peripheral circuit area can also be simplified.

[Brief explanation of the drawing]

FIGS. 1 and 2 are plan views of substrates showing the layout of the valley area, respectively, showing the first and second embodiments of the semiconductor memory device according to the present invention, and FIGS. FIG. 2 is a plan view of a substrate showing the arrangement of valley areas of a conventional semiconductor memory device. 11...Semiconductor substrate, 12...Cell array area, 12a, 12b, 12c, 12d---Divided cell array area, 13...Peripheral circuit area, 1
4...Second peripheral circuit area, 21a, 2
1b, 21c--Row decoder, 22a. 22b, 22C...Column decoder, 23...
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Claims (1)

[Claims] A plurality of memory cells are arranged in a matrix on a substantially rectangular semiconductor substrate, and connected to word lines extending in the short side direction of the substrate and bit lines extending in the long side direction. a cell array region consisting of a regular repeating pattern arranged in a shape, and a peripheral circuit region consisting of an irregular pattern located on both sides of the cell array region in the long side direction;
In a semiconductor memory device in which a plurality of divided cell array regions are set by dividing the cell array region in the long side direction, a word line of at least one divided cell array region is connected to a word line of another divided cell array region. a second substrate having an irregular pattern on at least one side of the divided cell array region in the short side direction of the divided cell array region having a reduced dimension in the short side direction by being shorter than the word line; A semiconductor memory device characterized in that a peripheral circuit area is set.