JPS63172471A - Write method for nonvolatile memory - Google Patents

Abstract

PURPOSE:To make it possible to shorten programming time, by performing temporary volatile writing before an electric field for nonvolatile writing is applied, and thereafter performing the nonvolatile writing into all nonvolatile memory elements in correspondence with write commands. CONSTITUTION:A first semiconductor region 1 is formed on a substrate. A second region 2 comprising a material, which forms a rectifying junction with the region 1, is provided in the region 1. A terminal 2E is formed on the exposed surface. A gate insulating film 3 is formed on the surface of the semiconductor region. A floating gate 4 as a charge storing mechanism is formed on the gate insulating film 3. An insulating gate 6 is formed through a second insulating film 5. When, e.g., a potential of 5 V is imparted to the first insulating gate 6, volatile writing is carried out. When information is stored in the elements,e.g., a relatively high voltage of about 10 V is applied to the insulating gate 6. When the temporary information is a '1,' a potential accompanied by the application of the voltage into the insulating gate 6 is further added to the surface potential. Thus punch-through occurs. Carriers are injected into a charge storing mechanism, and the nonvolatile storage of the logic information is carried out.

Description

[Detailed Description of the Invention] <Industrial Application Fields> The present invention relates to a non-volatile memory device which is formed by integrating a plurality of unit non-volatile memory elements (memory cells) in a matrix, which can retain information even when the power is turned off. Concerning how to write to sexual memory.

<Conventional technology> MAOS has traditionally been used as a nonvolatile memory element itself.
A variety of configurations have been proposed, including the type, FAMO3 type, and MIOS type.

Naturally, when comparing them individually from a structural standpoint, there are differences. Some use a material (so-called floating gate), while others use an insulating multilayer film or a thin ferroelectric material +1i, and there are also methods for selectively injecting charge into the charge storage mechanism. In addition to avalanche injection and tunnel injection, there are also channel injection methods.

Furthermore, by appropriately combining these charge injection methods, it is possible to electrically erase or rewrite memory contents by re-accumulating a different type of charge in a charge storage mechanism that stores a certain charge. In other words, there are also things called EAROM, E2FROM, etc.

However, considering the basic structure of these various nonvolatile memory elements, they are also semiconductor regions with a surface.

a charge storage mechanism disposed facing the surface of the semiconductor region and capable of nonvolatilely retaining charges supplied from the semiconductor region;

In order to supply the charge from within the semiconductor region to the charge storage mechanism in response to a write command, a non-volatile writing device is electrically coupled to the charge storage mechanism and reaches the semiconductor surface via the charge storage mechanism. and insulated gate means capable of generating an electric field.

It is possible to combine them with those that each have individually.

Furthermore, from this comprehensive perspective, even in a memory array in which a plurality of these nonvolatile memory elements are integrated in a matrix, the procedure for writing a predetermined memory pattern in a nonvolatile manner is almost the same. It became.

To put it simply, conventionally, the supply of the information content to be written and the non-volatile write command to the charge storage mechanism by the generation of the electric field are performed at substantially the same point in time for each memory element. Ta.

That is, for example, a logic "1" indicates a state in which charges are accumulated and held in the charge storage mechanism, a logic "0" indicates a state in which charges are not accumulated, and a logic "1" indicates a state in which charges are not accumulated in the charge accumulation mechanism. When writing in a non-volatile manner, a first potential is applied to the semiconductor surface under the charge storage mechanism when an electric field for non-volatile writing is generated due to voltage application to the insulated gate, and a logic "0" is applied to the semiconductor surface under the charge storage mechanism.
When writing ", a second potential is applied. When writing a predetermined logic value to each element in a non-volatile manner, a predetermined voltage is applied to the insulated gate to cause non-volatile writing, and at the same time the logic value to be written is Accordingly, when non-volatile writing of specific information to the first and second type memory elements is performed on the semiconductor surface, the non-volatile writing operation and the provision of the information to be stored thereby are performed substantially simultaneously or almost simultaneously. In practice, such operations were performed for each address line to which a plurality of nonvolatile memory elements were connected.

On the other hand, it is also known that the time required to perform nonvolatile writing to such a nonvolatile memory element is generally on the order of milliseconds, which is quite long.

Therefore, in the conventional method as described above, when looking at the memory array or the memory field as a whole, the initial batch erase operation for all nonvolatile memory elements is not taken into account when nonvolatile writing of a predetermined memory pattern is performed. In both cases, the time required for non-volatile writing of each element is multiplied by the number of address lines, and in practice this is quite a long time, and there is a problem that it becomes longer as the integration density increases.

For example, if the non-volatile write time required for each element or one address line is 10s, even if the address line configuration is 8.5 times, the time required for non-volatile write of all memory fields will be IOX 10-3X.
It will take 8 x 103 = 80 (seconds).

The present invention has been made in view of this point, and even if the time required for nonvolatile writing of information to each nonvolatile memory element is the same or cannot be changed, the entire memory field is When viewed as such, the objective is to provide a writing method that can reasonably shorten the time.

<Means for Solving the Problems> In order to achieve the above object, the present invention relates to non-volatile writing of information to each bit (individual non-volatile memory element), and finally writes the information in a non-volatile manner. We propose a method of temporarily writing volatile information to the relevant bit before writing.

Then, at predetermined intervals, or each time a predetermined number of elements are written to the board, all bits that have been volatilely written to the board are finally Issues a non-volatile write command.

Therefore, the present invention can be defined by the following configuration.

a semiconductor region having a surface; a charge storage mechanism disposed facing the surface of the semiconductor region and capable of nonvolatilely retaining charges supplied from the semiconductor region; insulated gate means electrically coupled to the charge storage mechanism and capable of generating an electric field for non-volatile writing through the charge storage mechanism to the semiconductor surface for said supply of charge into the structure; A method for writing to a non-volatile memory in which a plurality of semiconductor non-volatile memory elements are arranged in a matrix; Prior to applying the electric field for nonvolatile writing, the surface of the semiconductor region of each nonvolatile memory element is heated to a first potential that can supply the electric charge to the charge storage mechanism by the electric field, and a second electric potential that suppresses the supply. After performing volatile board writing by applying a potential to either one of the above; In response to the above write command, the electric field of the above non-volatile write river is generated at once in all the non-volatile memory elements to be written; A method for writing to a non-volatile memory, comprising: writing the information written on the board in a non-volatile manner into the charge storage mechanism.

(Operations and Effects) The present invention provides a new writing method for a nonvolatile memory array as defined in the first part of the summary, and it is possible to write to each element, which was conventionally viewed at the same time. The provision of information and the non-volatile write operation are clearly distinguished and captured, and volatile board writing is performed in advance on each non-volatile memory element constituting the non-volatile memory array at any time or at a predetermined timing, and then The main write, that is, the non-volatile write is performed all at once.

For example, as already described in connection with the conventional example, logic "1"
Assuming that a first potential is applied to the surface of the semiconductor region when non-volatile writing is performed to the charge storage mechanism, and a second potential is applied when non-volatile writing of logic "0" is performed, each non-volatile Such a potential is selectively applied in advance to the surface of the semiconductor region depending on the information content to be written to each memory element.

In other words, the information that will be non-volatilely written in the future to each non-volatile memory element is provided in advance in a volatile manner in the form of the potential on the surface of the semiconductor region of the element. When writing to a logic "," the electric field generated by the voltage applied to the insulated gate in the future non-volatile write phase provides a first potential that allows charge to be transferred from the surface of the semiconductor region to the charge storage mechanism; When writing 0'' in a non-volatile manner, a second potential is applied that prevents or at least suppresses charge transfer to the charge storage mechanism even if a non-volatile write electric field is generated in the future.

However, the potential information on the surface of the semiconductor region used for such board writing is volatile in this type of semiconductor nonvolatile memory element, regardless of the structure, and therefore nonvolatile write commands are sent to all bits to be written. In this way, once all bits or a predetermined number of bits in the memory array have been written to the memory array in the current writing phase, those writings are then completed. All the non-volatile memory elements that have been stored are put into the non-volatile write phase at once, and board write information is fully written in a non-volatile manner.

According to the method of the present invention, the time required to program the memory array as a whole can be significantly reduced.
Moreover, compared to the conventional method, the shortening effect becomes more pronounced as the integration density increases.

The reason is that, even in the past, the time required to apply a predetermined potential corresponding to the logical information to be stored to the surface of a semiconductor region under a charge storage mechanism ranges from several nanoseconds to several tens of nanoseconds at most. It is.

This means that when changing to the writing method of the present invention, the total time required to write to all non-volatile memory elements in the memory array will not be that long in total; Therefore, non-volatile writing, which takes a long time on the order of milliseconds even if it is short as mentioned above, is possible regardless of the integration density.
As a result, the overall memory programming time is considerably reduced.

For example, as in the previous conventional example, consider an address line configuration of 8, -8 bits per address line, board writing time of 1 Ons, and non-volatile writing time of 10m5.
The programming time for the entire memory array when the present invention is applied is the time required for board writing of all elements 8 x
The sum of 8 x 103x 10x 1O-9 (seconds) and the main writing time 10x 10-' (seconds) as the non-volatile writing time that can be completed only once is sufficient, and the former board writing time is essentially reduced to the latter. In comparison, two fingers can be ignored because it is on the small order, and in the end, it is sufficient to take about 10-2 seconds, which is close to the non-volatile writing time itself.

This is a big difference from the conventional method, which takes 80 seconds as mentioned above.

Furthermore, according to the present invention, each bit of logical information does not require any ordering in principle, and can be stored in advance literally whenever the need arises. It doesn't matter how many devices there are, even if information is written on several boards at the same time.

Furthermore, it is possible to perform an operation similar to that of a random access memory using only a volatile board write operation.

Note that the memory array to which the present invention is applied or the individual non-volatile memory elements constituting such a memory array include elements that have been appropriately modified by the applicant in the embodiments described below, as well as elements that have been appropriately modified by the applicant. Conventional configurations can be used as well as long as they satisfy the definitions in the first part, and in practice, the present invention can be applied to any suitable nonvolatile memory element structure of most existing configurations. An example is shown. Compared to elements with conventional structures, the present applicant has added innovations to this structure.

First, to explain the structure of this element itself, inside the semiconductor region 1, which is configured as a semiconductor substrate or formed on a separate substrate, there is a groove made of a material that forms a rectifying junction with the semiconductor region 1. Two areas 2 are provided.

Therefore, this second region may be an impurity region of the opposite conductivity type, or may be silicide or the like when the semiconductor region 1 is an n-type semiconductor.

In the illustrated case, the second region 2 has one end extending to the surface region of the first semiconductor region 1, and a terminal 2E is formed on the exposed surface.

An insulating film 3 shown conceptually is formed on the surface of the first semiconductor region 1, and a floating gate 4 is formed thereon as an example of a charge storage mechanism. A second insulating film 5 is provided above.
An insulated gate 6 is formed through the gate.

The insulated gate 6 controls the electric field of the insulating film 3 and the surface potential of the first semiconductor region 1.

FIG. 2 is an energy band diagram illustrating the inventive writing method applied to the nonvolatile memory device as shown in FIG. 1 above.

The solid line in the same figure (^) indicates that when board writing is performed on the surface of the first semiconductor region 1, and for example a first high potential corresponding to logic "1" is written, the solid line in the same figure (B) A case is shown in which a low potential is written on the surface of the first semiconductor region l, for example, as an absolute value corresponding to logic "0".

In practice, the state shown in FIG. This can be obtained by controlling the surface potential to approximately 2φP by applying a forward bias to the region 2 and injecting carriers into the semiconductor region. Note that φP is the Fermi level measured from the midgap of the first semiconductor region 1.

Volatile board writing in the present invention is performed in this way, but when attempting to fully store the board-written information in the element, that is, in the main writing or non-volatile writing phase, the insulated gate 6 has, for example, 1Ov. Apply a relatively high voltage of about

At this time, if the information written on the board before that was information "1" shown in Figure 2 (^),
Since the potential accompanying the voltage application to the insulated gate 6 is added in the same direction to the surface potential already written on the semiconductor surface, the bending of the band increases as shown by the imaginary line in the figure. , as shown in Figure 2 (B), if the information written on the board is logic "O" and is attached to a low potential in absolute value, the voltage applied to the insulated gate The increase in surface potential is not that great, so no significant band bending occurs.

Therefore, in the case shown in the same figure (^), carrier injection occurs into the semiconductor region 1, is accelerated there, and is injected into the charge storage mechanism to perform non-volatile storage of predetermined logical information. .

Such punch-through can be caused satisfactorily by appropriately designing the thickness of the insulating film 3.4, the thickness of the first semiconductor region 1, and the impurity concentration.

On the other hand, as shown in FIG. 2 ([I), logic “0”
”, punch-through does not occur during the non-volatile write operation, and therefore no significant charge is injected into the charge storage mechanism. However, of course, in the subsequent device state, no charge is injected into the charge storage mechanism. Due to the fact that ``O'' is not stored, the predetermined logic "O" is written in a non-volatile manner. 'For this reason, a memory in which non-volatile memory elements are arranged in a matrix as shown in Fig. 1. , the overall programming time can be significantly shortened, and conversely, the equivalent writing time per unit element can be extremely shortened. This is because non-volatile writing as tree writing only needs to be performed once.

In fact, when the writing method of the present invention is applied, as explained above with an example in the operation section, the entire memory can be written in almost the same amount of time as the time required for non-volatile writing to a single element. Can be programmed into the field.

In addition, this shortening effect becomes larger as the integration density increases,
Therefore, it is extremely promising for the future.

In addition, there is no limit in principle to the timing of writing information to each element, so if necessary, it is possible to write to the board at any time, and under the board writing phase, it operates like a random access memory. You can also do it.

A structure in which region 2 in FIG. 2 is omitted from the structure shown in FIG. 1,
Therefore, the writing method of the present invention can be implemented even if the structure is substantially the same as the basic structure of existing nonvolatile memory elements such as FAMOS type and MIOS type.

Semiconductor area 1 according to the information to be written when writing on the board
Controlling the surface potential of is the same as in the case described above. However, during actual writing, a second high voltage is naturally applied to the insulated gate 6, and avalanche breakdown and Zener breakdown are used to inject charge into the charge storage mechanism.

In such a case, it is also desirable that the surface of the semiconductor region l be provided with a high impurity concentration. Of course, the semiconductor region 1 may be the semiconductor substrate itself, or may be a thin film formed on a suitable semiconductor substrate or insulating substrate.

Furthermore, although not shown, as seen in known non-volatile memory elements of this type, information called sources, drains, etc. is provided on both sides of the charge storage mechanism on the surface of the semiconductor region. A readout area may be provided separately.

Further, as mentioned above, the charge storage mechanism is not limited to the floating gate shown in the figure, but may have any suitable structure. Therefore, if the charge storage mechanism used is insulating, the insulated gate 6 is insulated. It can also be formed directly on the charge storage mechanism without using +1i5.

FIG. 3 shows yet another structural example devised by the applicant as a nonvolatile memory element to which the writing method of the present invention can be applied.

The same reference numerals as in FIG. 1 indicate the same or similar components, and therefore the structure includes a semiconductor region 1, a gate insulating film 3, a charge storage mechanism 4, a second insulating film 5, and an insulating layer 6. ing. However, if the charge storage mechanism is insulative as described above, the second insulating film 5 is not necessary.

This element is designed to use avalanche breakdown for non-volatile writing, so there is no separate second region 2 in the first illustrated embodiment, and the region 2 that supplies carriers during non-volatile writing by avalanche breakdown is , so to speak, it is the semiconductor region 1 itself.

A channel forming region 11 is provided which communicates with the semiconductor region 1 and can selectively form a channel along the surface portion, and furthermore, an information writing/reading region 12 is provided in contact with this channel forming region 11.

The information write/read region 12 is of a conductivity type opposite to that of the semiconductor region 1, or is made of a material capable of forming a rectifying junction with the semiconductor region 1, such as a suitable metal or silicide.

In order to selectively form a channel in the channel formation region 11, a second insulated gate 16 is provided through the insulating film portion 15, and of course, the information write/read region 12, the second insulated gate 16, the first insulated gate Each insulated gate 6 is provided with an external lead terminal.

To explain the operation when the writing method of the present invention is applied assuming that the semiconductor region 1 is p-type, first, in the board writing phase, a first high voltage is applied to the first insulated gate 6 and the second insulated gate 16. (For example, 5V) is applied to the information writing/reading area 12 according to the information content.
A relatively high voltage or low voltage (for example, Ov) is applied to the voltage. For example, a relatively high voltage may correspond to a logic "1" and a relatively low voltage may correspond to a logic "0".

Next, the second insulated gate 16 is set to a low voltage, for example Ov, to turn off the channel on the surface of the channel forming region 11.

In a memory to which the present invention is actually applied, a large number of such elements are arranged in a matrix, so the conventional procedure in the board writing phase is performed on each element constituting the memory array at any time or in a predetermined sequence. Leave it there.

However, as mentioned earlier, the time required for such board writing is only a few tens of nanoseconds per element at most, so even in a memory array with a fairly high integration density, the time required for writing to each element is still small compared to the non-volatile writing time to each element. The time it takes is so short that it can be almost ignored.

After completing the board writing for all or all of the elements to which nonvolatile writing is to be performed, the first insulated gate 6 is applied to a second high voltage (for example, 12 V) in the main writing or nonvolatile writing phase.

Therefore, if a relatively high potential is applied to the surface of the semiconductor region according to the logic "1" during board writing, an avalanche breakdown will occur on the surface of the semiconductor region 1, and charges will be transferred from the surface of the semiconductor region to the charge storage mechanism 4. If the charge is injected into the charge storage and held there in a non-volatile manner, and if a logic "0" is written, the avalanche breakdown described above will not occur, and there will be no change in the storage state of the charge storage mechanism. This indicates completion of non-volatile writing of logic "0".

In the case of the device used in this embodiment, reading the information non-volatilely written in this way applies a relatively low voltage to the write/read region 12, and at the same time applies a relatively low voltage to the second insulated gate 16. The relatively high voltage of
Also, the first insulated gate 6 is applied to the intermediate value of the previous high and low voltage values (
This can be achieved by providing a gate threshold voltage (approximately the same as the gate threshold voltage after non-volatile writing).

If a logic “1” is written (charge is stored in the charge storage mechanism 4), the first insulated gate 6
No electron charge is read out on the surface of the underlying semiconductor region, but if a logic “0” is written (if no charge is stored in the charge storage mechanism), electrons are induced through the adjacent channel. It's coming.

Therefore, the presence or absence of this electron is written in the readout area 1.
By inverting the data through 2 and reading it differentially, it is possible to know the information content that has been written in a non-volatile manner.

The element shown in FIG. 3 can be reconfigured symmetrically with respect to the line A-A in the figure, and if an information write/read region 12 and a second insulated gate 16 are also provided on the right side in the figure, A pair of configured information writing/reading areas 12.
Information sensing can also be performed using a field effect transistor with 12 as a source and a drain.

Furthermore, if it is desired to utilize the punch-through phenomenon explained in connection with FIG. 1 for non-volatile writing of information, as shown in FIG.
It is also possible to consider a structure in which this is added to the configuration shown in FIG.

In this case, rationally, the surface terminal area 2E of the second area 2 can be configured as a common area with the information writing/reading area 12.

Of course, the writing method of the present invention that has been described so far can be applied in exactly the same manner to a memory array formed by integrating a large number of nonvolatile memory elements shown in FIG.

Also in the elements shown in FIGS. 3 and 4,
The semiconductor region 1 is not limited to a region continuous to a suitable semiconductor substrate, but may be provided as a thin film region formed on a semiconductor substrate or an insulating substrate.

Furthermore, as has already been stated several times, the present invention is not limited to the memory array using nonvolatile memory elements illustrated in FIGS. It can be applied to almost all memory arrays. This is because these nonvolatile memory elements also have the same terminal structure for controlling the potential of the surface portion of the semiconductor region under the charge storage mechanism according to at least the information content to be written.

However, as seen in the above embodiments, as a memory element to which the present invention is applied, a charge supply means (No. 1.4
In the illustrated device, an independent area 2 (in the third illustrated embodiment, an area 2 common to area 1) is used, and after setting the surface potential of the semiconductor device in advance by writing on a board, If the carrier charges to be written into the charge storage mechanism are injected at an accelerated rate from the semiconductor surface according to the information, the present invention will be faster than when the present invention is applied to a memory element with a simpler structure that does not have the charge supply means as described above. , is desirable in that carrier charges can be injected more reliably.

Note that EAROMJP is not limited to ROMs that cannot be electrically rewritten as described in the previous embodiments.
The present invention can be similarly applied to electrically rewritable memories, such as E2PROM, with regard to selective non-volatile writing of two pillars of charge.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a first structural example of a nonvolatile memory element to which the nonvolatile memory writing method of the present invention can be applied;
FIG. 2 is an explanatory diagram when the writing method of the present invention is applied to the element shown in FIG. 1, and FIG. 3 and FIG. FIG. 2 is a schematic configuration diagram of an example of a memory element structure. In the figure, 1 is a semiconductor region, 2 is a second region, 3 is a gate insulating film, 4 is a charge storage mechanism, 6 is an insulated gate, 11 is a channel formation region, 12 is an information write/read region, and 16 is a second insulator. It is a gate.

Claims (1)

[Scope of Claims] A semiconductor region having a surface, a charge storage mechanism disposed facing the surface of the semiconductor region and capable of non-volatilely retaining charges supplied from the semiconductor region, an insulated gate electrically coupled to the charge storage mechanism for supplying charge from within the region into the charge storage mechanism and capable of generating an electric field for non-volatile writing through the charge storage mechanism to the semiconductor surface; A method for writing to a non-volatile memory in which a plurality of unit semiconductor non-volatile memory elements each having means are arranged in a matrix; , the surface of the semiconductor region of each nonvolatile memory element is set at a first potential that can supply the charge to the charge storage mechanism by the electric field, and the supply After performing volatile board writing by attaching the potential to one of the second potentials that suppresses the voltage; In response to the write command, the electric field for non-volatile writing is A method for writing to a non-volatile memory, characterized by: causing the information written on the board to occur at once and writing the information written on the board into the charge storage mechanism in a non-volatile manner.