JPS63172465A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the junction area of an emitter and a base and to increase junction breakdown strength, by forming an Si single crystal layer at a low temperature, and using the layer as the emitter. CONSTITUTION:An n-type Si layer is epitaxially grown on an n<+> embedded layer on an Si substrate. P ions are implanted in the substrate, and a collector layer 3 is formed. Elements are isolated with a field oxide film 5. A base region 2 and a base contact region (P<+> region) 6 are formed by the implantation of B ions. Then an a-Si 7 is deposited on an emitter opening part by evaporation from an Si evaporation source including P. The device is annealed in an electric furnace. The a-Si is made to be a single crystal by a solid-phase growth based on the crystal information of the Si substrate, which is exposed in the emitter opening part. The P, which is doped at the same time as the solid-phase growth, is activated and the growth layer becomes n<+>. The emitter can be formed with C-Si without diffusing P in the substrate Si.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a bipolar transistor.

[Conventional technology]

The current emitter formation method for shallow junction bipolar transistors is as follows: 1. As shown in Fig. 2, the S
A method for forming an i-substrate.

2, doped poly-8i, or.

Deposit dopad a-8i in the emitter opening.

There are two main methods: using it as an emitter.

Regarding these technologies, 1. For more information, click here.Nical Digest IEE International Electron Device Meeting Paper No. 2
*4 Dec, 1985 (Technical Di
gest IEEE International E
lectron DeviceMeeting paper number 2.4 Dec, 1985), 2. For Technical Digest IE International Electron Device Meeting Paper No. 32
*3 Dec, 1984 (Tachnical Di
gest IEEE International E
Electron Device Meeting Paper No. 32, 3 Dec, 1984).

[Problem that the invention attempts to solve]

The above prior art has the following problems in cases 1 and 2.

1. Since this is a process in which As is driven in from Poly-8i, the shape of the n+ region is as shown in FIG.

The result is as shown in FIG. 3(a). Therefore, the emitter-base junction area is calculated by dividing area A by area as shown in FIG. 3(a). In other words, the area A is larger than the area B of the emitter opening.
The junction capacitance increases by the portion . Also, the third
The base concentration profile of region A in Figure (a) is shown in Figure (a).
b) The concentration is medium α, which is higher than the designed base concentration β. Therefore, the emitter-base breakdown voltage becomes smaller than the value expected based on the concentration of β.

2. When doped poly-8i, a-8i is deposited to form the emitter region, 1. There are no such problems.

However, the emitter-base junction.

po'ly-8i/C-5i or a-8i/C
-8i, the bonding is unstable compared to the case of C-5i/C-8i.

The purpose of the present invention is to solve the above problems.

For example, in the case of an npn transistor, n-type C-8i is formed on p-type Si without diffusing the n+ region in a Si substrate, and that portion is used as an emitter. That is, the purpose is to fabricate a bipolar transistor having the structure shown in FIG. 1(e).

[Means for solving problems]

The above object can be achieved by forming a Si single crystal layer at such a low temperature that diffusion of impurities can be ignored and using it as an emitter. Techniques for forming single crystals at low temperatures include molecular beam epitaxy (MBE) and in-phase epitaxy (SPE).

Therefore, the above object can be achieved by forming an emitter on a Si substrate using a technique such as MBE or SPE.

[Effect]

SPE method or MBE method (both ~600℃ or less)
By epitaxially growing Si on the base and making that part an emitter, the emitter-base junction area coincides with the emitter opening (region B in Figure 3(a)), and the emitter is grown in the Si substrate. The emitter-base junction area is reduced compared to the case of diffusion.

Furthermore, since the emitter is not diffused into the base region, the concentration α portion shown in FIG. 3(b) does not exist.

Therefore, the emitter-base junction breakdown voltage matches the breakdown voltage expected from the base peak concentration β of the intrinsic bipolar portion.

In other words, when comparing the case where the base peak concentration of the intrinsic bipolar part is the same, the emitter of the present invention is better than the conventional case where the emitter is formed by diffusion and the case where the emitter is formed by the present invention.
The base pressure resistance is high.

Furthermore, another effect of the present invention is an increase in emitter injection efficiency. This is due to the feature that impurities can be activated simultaneously with the epitaxial growth of the emitter.

That is, when forming an emitter by diffusion.

However, since heat treatment at high temperature is required, the impurity profile of the emitter becomes low in concentration near the emitter-base junction, as shown in FIG.

In the case of the present invention, impurities are mixed into the Si vapor deposition source, or impurities are introduced in parallel with the Si vapor deposition.
Similarly, if it is made uniform in the emitter as shown in Figure 6,
Since activation annealing at high temperature is not required, this distribution can be directly used as the impurity distribution of the emitter.

It depends on that.

〔Example〕

The present invention will be explained in detail below. First, the case of a normal bipolar transistor (FIG. 1) will be explained. n on ten buried layers! P ions are implanted into the Si substrate on which the JAsi layer is epitaxially grown, and the collector N! Form I3 and perform device isolation with field oxide film 5. Form base region 2 and base contact region (P+ region) 6 by B ion implantation. a-5i7 by evaporation from a Si evaporation source containing P at a concentration of ˜0.
Deposit 5 μm. Then annealed at 600℃ in an electric furnace.
This is carried out for 0 minutes, and a-8i is single-crystalized by solid phase growth based on the crystal information of the Si substrate exposed in the emitter opening. P doped with ~1x10”O/ad simultaneously with solid phase growth
is activated and the growth layer becomes n0. In this way, an emitter can be formed from C-8i without diffusing P into the Si substrate (into the base).

Next, an example applied to a selfline bipolar will be described. P÷ territory P+B from Po1y-8i8
The process is the same as that described above except that the base contact 6 is formed on the P+Po1y-5i. The unique effects of this embodiment in which the emitter is formed by solid phase growth are a-8i and C-8i.
The difference in etch rate during dry etching of Si can be used to form an emitter in the emitter opening with a self-aligned line. In other words, when Si is etched by dry etching after solid-phase growth reaches the state shown in Figure 5, a-8i, which has a higher etch rate than C-8i, is etched first, resulting in a state as shown in Figure 4(f). It becomes an emitter of a shape.

〔Effect of the invention〕

According to the present invention, the emitter can be formed of a single crystal without diffusing impurities that determine the conductivity type of the emitter into the Si substrate (in the base). Therefore, the emitter-base junction area decreases, and the emitter-base junction capacitance decreases. Similarly, since the emitter is not formed in the base by diffusion, the region A in FIG. 3(a) with the concentration of profile α in FIG. 3(b) does not exist, so the emitter-base junction breakdown voltage also increases. do. Furthermore, since the emitter is formed from a single crystal, the emitter-base junction is C-8i/
C knee Si, doped poly-5 emitter
The bonding stability is superior to that formed using A-8i or doped A-8i.

[Brief explanation of the drawing]

Fig. 1 is a basic structural diagram explaining one embodiment of the present invention;
The figure is a structural diagram of a conventional poly-8i emitter bipolar transistor, FIG. 3 is an explanatory diagram showing the shape and concentration profile of the emitter part of the poly-8i emitter transistor, and FIG. 4 is an explanatory diagram. FIG. 5 is a cross-sectional view showing an example in which the present invention is applied to Selfaline bipolar, FIG. 5 is a diagram showing solid phase growth, and FIG. 6 is a diagram showing increase in emitter injection efficiency. DESCRIPTION OF SYMBOLS 1...Emitter, 2...Base, 3...Collector, 4...poly-8i (P+), 5-
8 iOa, 7-a -8i-t ゛Agent Patent attorney Katsuma Ogawa (c)

Claims (1)

[Claims] 1. In a method for manufacturing a bipolar transistor, a base and a collector are formed in a Si substrate, and then impurities that determine the conductivity type of the grown layer are diffused into the Si substrate based on crystal information of the Si substrate. 1. A method for manufacturing a semiconductor device, characterized in that Si is epitaxially grown without any process, and this portion is used as an emitter.