JP3505892B2 - Manufacturing method of bipolar transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor having a heterojunction.

[0002]

2. Description of the Related Art In order to increase the speed of a bipolar transistor, it is essential to form a high concentration and thin base layer. However, in the conventional ion implantation technique, it is difficult to realize a base width thinner than 40 nm due to channeling of implanted impurities.

As one of the solutions to this problem, a method of forming a base layer by using an epitaxial technique without channeling is disclosed. By doping impurities in the process of epitaxial growth, it is possible to form a high-concentration and thin base layer, and a base layer width of 30 nm or less can be realized. With this technology, the maximum cutoff frequency f
High-speed bipolar transistors exceeding Tmax = 50 GHz have been realized. In the above structure, the base resistance (Rb)
Therefore, even though the maximum cutoff frequency (fTmax) is high, the maximum oscillation frequency fmax can be realized only at about 30 GHz.

In order to further increase the concentration of the base layer in order to lower the base resistance (Rb), it is necessary to increase the concentration of the emitter at the same time in order to secure the current amplification factor (hFE). When the concentration of the emitter is excessively high, the injection efficiency decreases due to bandgap narrowing, the emitter / base breakdown voltage deteriorates, and the emitter-base junction charge / discharge time constant τEB
Come to an increase. Since these parameters have a contradictory relationship, there is a limit to the speedup of the bipolar transistor.

Therefore, it has become possible to eliminate the above-mentioned contradictory relationship by utilizing a heterojunction in which the band gap is changed between the emitter and the base. For example, a heterojunction using silicon germanium (SiGe) having a smaller bandgap than silicon as a base material is known as a practical one. Heterojunctions allow for greater injection of carriers from the emitter to the base than homojunctions. By utilizing this, it becomes possible to secure the current amplification factor (hFE) without increasing the base resistance (Rb) and the emitter-base junction charge / discharge time constant τ EB, and the maximum oscillation frequency fmax = about 50 GHz. A bipolar transistor can be realized.

In order to realize a heterojunction bipolar transistor, it is important to control the distribution of P-type impurities and germanium (Ge) in the base layer. If the heterojunction and PN junction are misaligned, the parasitic conduction band barrier
The current amplification factor (hFE) and the Arsoe voltage (VA) are reduced by the action barrier.

A conventional method for manufacturing a heterojunction bipolar transistor will be described with reference to the manufacturing process chart of FIG.

As shown in FIG. 5A, an N ⁺ type buried collector layer 112 is formed on the surface layer of the silicon substrate 111 by the solid phase diffusion method. Then, an N-type impurity is added to the silicon substrate 111 by an epitaxial growth method.
Epitaxial layer 113 containing about 10 ¹⁶ pieces / cm ³
To form. Furthermore, a local oxidation method [eg, LOCOS
(Local Oxidation of Silicon) method, an element isolation oxide film 114 is formed on the epitaxial layer 113. Then, the surfaces of the epitaxial layer 113 and the element isolation oxide film 114 are flattened. Then the P ⁺ -type isolation diffusion layer 115 is formed on the lower surface side of the element isolating oxide film 114 by ion implantation, and joined by another ion implantation into the collector layer 112 buried in the N ⁺ -type N ⁺
A collector collector diffusion layer 116 of the mold is formed.

Then, as shown in FIG. 5B, silicon germanium (Si _0.8) containing about 3 × 10 ¹⁹ P-type impurities of boron (B) / cm ³ is formed on the entire upper surface of the epitaxial layer 113. A Ge _0.2 ) film is formed to a thickness of 30 nm. Furthermore, 3 × 10 ¹⁸ N-type impurities / c
A silicon film containing about m ³ is formed to a thickness of 50 nm to 80 nm.

Then, in order to make contact with the electrodes, ion implantation and activation annealing are carried out, and the emitter layer 118 is heavily doped with N-type impurities (for example, 1 × 10 ²⁰ / c).
The emitter contact layer 119 is formed by doping at least m ^{3 and} below the saturated state). The activation annealing at this time requires a temperature of about 850 ° C. to 900 ° C. Then, patterning is performed to form a base layer and an emitter layer on the base layer.

After that, as shown in FIG. 5C, after forming an interlayer insulating film 121, contact holes 122 and 123 for connecting electrodes to the base layer 117, the emitter contact layer 119, and the collector extraction diffusion layer 116. ，
124, and each electrode 125, 126, 127
To form.

As a second example of the prior art, there is a method of epitaxially growing a base layer, an emitter layer and an emitter contact layer at a low temperature.

As a third example of the prior art, after the base layer and the emitter layer are epitaxially grown at a low temperature,
There is a method of forming an N-type impurity region by an ion implantation method.

[0014]

However, in the manufacturing method of the first example, when the temperature of the heat treatment performed after forming the base layer exceeds 800 ° C., boron (B) or germanium ( Ge) diffuses. Therefore, the base width is widened and the positions of the heterojunction and the PN junction are displaced. Further, since the base layer made of silicon germanium (SiGe) is formed with a thickness exceeding the critical film thickness determined by thermal equilibrium theory, dislocation occurs due to plastic deformation when high temperature is applied. That causes a leak.

Further, as shown in the impurity distribution chart of FIG.
Immediately after the epitaxial growth, the distribution of boron (B) in the base layer formed by the epitaxial growth method is in a narrow range as indicated by the broken line, which coincides with the silicon-germanium mixed crystal region. Then, through the heat treatment step, boron (B) was diffused and the distribution of boron was broadened as shown by the solid line. Therefore, the base width is widened by the heat treatment process, which makes it difficult to increase the speed. The vertical axis of FIG. 6 represents the impurity concentration, and the horizontal axis represents the depth in the emitter, base and collector directions.

In the second example of the above-mentioned prior art, 800
If the N-type impurities in the atmosphere during the epitaxial growth increase at a low temperature of about C or lower, the silicon surface becomes chemically inactive due to the adsorption of the group V element. for that reason,
The growth rate is remarkably reduced, and it does not reach a practical level in industrial production.

Further, in the third example of the prior art described above, heat treatment at a relatively high temperature is required for activation and recovery of crystallinity. Further, there is a problem that interstitial silicon is released during the crystal recovery process, and the diffusion of boron (B) increases by two digits or more.

Further, the emission of interstitial silicon by the ion implantation method becomes a problem even when the emitter is made of polycrystalline silicon. The adoption of so-called in-situ doped polycrystalline silicon eliminates the accelerated diffusion of boron (B) due to the emission of interstitial silicon. However, it is difficult to stably form polycrystalline silicon without growing a natural oxide film at the interface between the polycrystalline silicon and silicon, and thus there is a problem that the emitter resistance increases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a heterojunction bipolar transistor which does not diffuse impurities in a base layer at an accelerated rate.

[0020]

SUMMARY OF THE INVENTION The present invention is a method of manufacturing a bipolar transistor, which has been made to achieve the above object.

That is, a step of forming a first conductive type semiconductor film to be a base layer on a semiconductor substrate, and a step of forming a second conductive type semiconductor film to be an emitter layer on the first conductive type semiconductor film. And the second by plasma doping
And a step of forming a second-conductivity-type high-concentration layer by doping the surface layer of the conductivity-type semiconductor film with an impurity so that the impurity concentration is higher than that of the second-conductivity-type semiconductor film. To do. Or, element formation on the surface side of the semiconductor substrate
A step of forming an element isolation region for isolating the region,
Form a polycrystalline silicon film over the entire surface of the semiconductor substrate.
After the formation, the polycrystalline silicon on the device isolation formation region is formed.
The step of forming an opening in the film and the front surface side of the semiconductor substrate
A first conductivity type semiconductor film to be a base layer is formed on the entire surface of
And then becomes an emitter layer on the semiconductor film of the first conductivity type.
Forming a second conductivity type semiconductor film, and the second conductivity type
Of a higher concentration than the semiconductor film of the second conductivity type on the semiconductor film of
Forming a dielectric film containing impurities of the second conductivity type;
The second conductivity type is obtained by solid phase diffusion from the dielectric film.
Is more impure than the second conductivity type semiconductor film on the surface layer of the semiconductor film of
The solid phase diffusion of impurities in the state that the
Forming a high-concentration layer of the second conductivity type that becomes the contact layer
Process, and patterning the dielectric film to form an emitter layer.
Before forming an etching mask for forming
By the etching using the etching mask,
By patterning the high-concentration layer of the second conductivity type,
A tact layer is formed and the second conductivity type film is patterned.
Ningu to is characterized in that example Bei and forming the emitter layer. Alternatively, a step of forming a first conductive type semiconductor film to be a base layer on a semiconductor substrate, a step of forming a second conductive type semiconductor film to be an emitter layer on the first conductive type semiconductor film, Due to solid-phase diffusion from a film containing impurities of the second conductivity type formed on the semiconductor film of the second conductivity type, the semiconductor film of the second conductivity type is formed on the surface layer of the semiconductor film of the second conductivity type more than the semiconductor film of the second conductivity type. In the method of manufacturing a bipolar transistor, the method comprises: solid-phase diffusing impurities to form a second-conductivity-type high-concentration layer with a high impurity concentration, wherein the first-conductivity-type semiconductor film is silicon-germanium. It is characterized by being made of a compound semiconductor.

In the above bipolar transistor manufacturing method, since the high-concentration emitter contact layer is formed by plasma doping or the emitter contact layer is formed by solid-phase diffusion, impurities in the base layer,
For example, the temperature at which boron (B) diffuses is not applied. Therefore, when forming the emitter contact layer,
The diffusion of impurities in the base layer can be suppressed.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An example of the first embodiment of the present invention will be described.
This will be described with reference to the manufacturing process diagrams of FIGS. 1, 2 and 3.
1 shows a manufacturing process which is a feature of the present invention, FIG. 2 shows a process prior to the process shown in FIG. 1, and FIG. 3 shows a process subsequent to the process shown in FIG.

As shown in FIG. 2A, a silicon oxide film 12 of, for example, 33 is formed on a <100> first conductivity type (hereinafter referred to as P type) silicon substrate 11 by a thermal oxidation method.
It is formed to a thickness of 0 nm. By a lithography technique (for example, formation of a resist film by resist application, exposure, development, baking, etc.) and a dry etching technique using the resist film (not shown) as an etching mask, the above-mentioned region on the collector is formed. The opening 13 is formed in the silicon oxide film 12. Then, the resist film is removed by ashing and cleaning.

Then, by solid phase diffusion using antimony oxide (Sb ₂ O ₃ ), a second conductivity type (hereinafter referred to as N type), that is, N ⁺ type collector buried region 14 is formed on the upper layer of the silicon substrate 11. To form. At this time, the silicon oxide film 12 serves as a mask for this solid phase diffusion. The solid-phase diffusion conditions are, for example, diffusion temperature: 1200
C., diffusion time: 1 hour.

After that, the silicon oxide film 12 is removed by etching. Then, as shown in (2) of FIG. 2, an N-type epitaxial layer 15 is formed on the silicon substrate 11 which has been subjected to the above-mentioned treatment, by a known epitaxial growth technique. The epitaxial layer 15 has, for example, a sheet resistance of 0.1 Ωcm to 1.0 Ωcm and a thickness of:
It was formed in each range of 0.5 μm to 1.5 μm.

Next, a silicon oxide film (not shown) is formed on the surface of the epitaxial layer 15 by thermal oxidation to a thickness of, for example, about 50 nm. Then, chemical vapor deposition (hereinafter, referred to as CVD, is a chemical vapor deposition
Deposition) method is used to produce silicon nitride (Si ₃ N
₄ ) A film (not shown) is formed with a thickness of 100 nm, for example. Next, the epitaxial layer 15 is etched to a depth corresponding to about half the thickness of the element isolation region to be formed. After that, a local oxidation method [eg, LO
COS (Local Oxidation of Silicon) method]
The element isolation region 16 is formed in the etched portion, for example, 80
It is formed to a thickness of 0 nm. In this way, the substrate 10 is formed. The element isolation region 16 is the active region 17
And collector extraction region 18 are separated.

After that, the silicon nitride film (not shown) used in the local oxidation method is removed by etching. Next, a resist mask (not shown) having an opening (not shown) is formed on the collector extraction region 18 by a lithography technique (for example, resist film formation by resist coating, exposure, development, baking, etc.). After that, the silicon substrate 11 is doped with N-type impurities by an ion implantation method using this resist mask. The ion implantation conditions are set, for example, as follows: implantation impurities: phosphorus ions (P ⁺ ), ion implantation energy: 70 keV, dose amount: 5 × 10 ¹⁵ / cm ² . Then, heat treatment is performed to form an N ⁺ -type sinker region 19 that is joined to the collector buried region 14 in the epitaxial layer 15. As an example, the heat treatment conditions are set as follows: heat treatment temperature: 1000 ° C., heat treatment time: 30 minutes.

After that, the so-called bird's head formed in the element isolation region 16 formed by the local oxidation method is removed by the existing method, and the element isolation region 16 is removed.
Form the top flat.

Next, a resist mask having an opening (not shown) is formed on a region where an element isolation diffusion layer is to be formed by a lithography technique (for example, formation of a resist film by applying a resist, exposure, development, baking, etc.). After that, the element isolation diffusion layer 20 is formed below the element isolation region 16 by an ion implantation method using the resist mask.
To form. The above-mentioned ion implantation conditions are, for example, implanted impurities: boron ions (B ⁺ ), ion implantation energy: in the range of 200 keV to 500 keV, dose amount: 1 × 10 ¹³ / cm ² to 1 × 10 ¹⁵ / cm.
Set to the range of ² .

Then, by etching, the silicon oxide film (not shown) used as the mask for the above-mentioned local oxidation method formed on the active region 17 is removed. Subsequently, as shown in (1) of FIG. 1, a P ⁺ -type polycrystalline silicon film 21 having a thickness of, for example, 20 nm to 80 nm is formed on the entire surface of the substrate 10 on the side where the silicon oxide film is removed by the CVD method. A film is formed to a predetermined thickness. After that, the polycrystalline silicon film 21 is doped with a P-type impurity by an ion implantation method. The above-mentioned ion conditions are, for example, implanted impurities: boron difluoride ion (BF ₂ ⁺ ), ion implantation energy: in the range of 20 keV to 80 keV, dose amount: 5 × 10 ¹⁴ / cm ^{2 to} 7 × 10 ¹⁵ / cm
Set to the range of ² .

The polycrystalline silicon film 21 is made of CV.
It is also possible to form so-called in-situ doped polycrystalline silicon by the D method. The polycrystalline silicon film 21 is formed to reduce the resistance of the base lead electrode portion and to ensure hydrogen passivation in the subsequent step of hydrofluoric acid cleaning.

Next, the polycrystalline silicon film 21 on the active region 17 is removed by a lithographic technique (for example, resist film formation by resist coating, exposure, development, baking, etc.) and an etching technique to remove the opening 22. To form.

Subsequently, as shown in FIG. 1B, cleaning with hydrofluoric acid is performed to form hydrogen passivation on the entire surface. Then, by any one of ultra-high vacuum CVD method, molecular beam epitaxy and low pressure CVD method,
A P ⁺ type silicon germanium film 23 and an N ⁻ type silicon film 24 are sequentially formed on the entire surface of the polycrystalline silicon film 21 side.

For example, in the case of the low pressure CVD method, after performing hydrogen (H ₂ ) prebaking at 1000 ° C. for 10 minutes, if necessary, a base layer to be a base layer is formed under the following film forming conditions. A P ⁺ type silicon germanium film 23 is formed as a semiconductor film of one conductivity type. The film forming conditions are, for example, reaction gas: dichlorosilane (SiH ₂ Cl ₂ ) + monogermane (GeH ₄ ) + diborane (B ₂ H ₆ ), pressure of film forming atmosphere: 8 kPa, film forming temperature: 700 ° C. Set to. Then, film formation was performed under these conditions to form the P ⁺ -type silicon germanium film 23 with a predetermined thickness in the range of 20 nm to 80 nm. In the above film formation, the concentration of boron (B) is 5 × 10 ¹⁸ pieces / cm ^{3 to} 5 × 1.
The content was set to 0 ¹⁹ pieces / cm ³ , and the mixed crystal composition ratio of silicon germanium was set to 5 atomic% to 20 atomic% of germanium.

Then, an N ^-- type silicon film 24 is formed as a second conductivity type semiconductor film to be an emitter layer by a low pressure CVD method. The film forming conditions are, for example, reaction gas: monosilane (SiH ₄ ) + phosphine (PH
₃ ), pressure of film forming atmosphere: 8 kPa, film forming temperature: 750 ° C. Then, film formation was performed under these conditions to form an N ⁻ type silicon film 24 with a predetermined thickness in the range of 100 nm to 200 nm. In the above film formation, the phosphorus (P) concentration is 1 × 10 ¹⁸ pieces / cm ³ to 1 × 10 ¹⁹ pieces / c.
The range was m ³ . P ⁺ type silicon germanium film 2
For both the 3 / N ⁻ type silicon film 24, single crystal silicon was grown on the single crystal silicon, and polycrystalline silicon was grown on the polycrystalline silicon.

Subsequently, as shown in (3) of FIG.
By the doping method, N^-Type silicon film 24 table
The layer is doped with a group V element at a high concentration to obtain an impurity concentration
Is 5 × 10¹⁹Pieces / cm³~ 5 x 10^{twenty one}Pieces / cm³Demon
Enclosure, preferably with an impurity concentration of 1 × 10²⁰Pieces / cm³~ 2
× 10^{twenty one}Pieces / cm³High density layer with specified density in the range
Becomes N⁺Type silicon layer 25, for example, 50 nm to 1
It is formed to a predetermined thickness in the range of 50 nm. This
The raising conditions are, for example, Doping gas; phosphine diluted with helium (He)
(PH₃), Pressure of doping atmosphere: 5 Pa , The glow discharge generates plasma, and the
N, which is a cathode, accelerated by a sheath (not shown)^-Type
The impurity concentration of the surface layer of the silicon film 24 is 1 × 10 ^{twenty one}Individual/
cm³So that its thickness is 80 nm, N type impurity
Doped things.

The plasma doping is performed at 200 ° C. to 6 ° C.
It is possible to perform high-concentration doping at a predetermined temperature in the temperature range of 00 ° C. Therefore, boron (B) or germanium (Ge) in the silicon-germanium film 23 which will be the base layer is diffused to widen the base width, and the heterojunction and the P-N junction are not displaced from each other.
Further, accelerated diffusion of boron (B) due to the emission of interstitial silicon does not occur. In addition, silicon germanium (SiG
e) The mixed crystal does not undergo plastic deformation, and a dislocation-free crystal is maintained.

Then, as shown in (4) of FIG.
By the method, a silicon oxide film is formed on the entire surface of the N ⁺ type silicon layer 25 to a thickness of 100 nm, for example.
After that, the active region 17 is formed by a lithography technique (for example, resist film formation by resist coating, exposure, development, baking, etc.) and an etching technique.
A silicon oxide pattern 26 is formed on the emitter formation region in, leaving the silicon oxide film. At this time, the silicon oxide pattern 26 is formed on the single crystal region and not on the polycrystalline region.

Then, as shown in FIG. 3A, the silicon oxide pattern 26 is formed by wet etching using a mixed solution of potassium hydroxide (KOH) and potassium carbonate (K ₂ CO ₃ ) as an etching solution. the N ⁺ -type silicon layer 25 and N as an etching mask ^- by patterning the silicon film 24, to form the emitter contact layer 27 made of N ⁺ -type silicon layer (25), N ^- -type An emitter layer 28 made of a silicon film (24) is formed. In the above wet etching, the selection ratio to silicon germanium (SiGe) is 20.
Since it becomes ~ 30, P ⁺ type silicon germanium film 2
It becomes possible to suppress the over-etching of No. 3.

Subsequently, the silicon oxide pattern 26 is removed by wet etching using hydrofluoric acid. afterwards,
The P ⁺ -type silicon germanium film 23 and the P ⁺ -type polycrystalline silicon film 21 are patterned by a lithography technique (for example, formation of a resist film by resist coating, exposure, development, baking, etc.) and an etching technique. Then, the base layer 29 is formed on the active region 17 and the base lead electrode 30 bonded to the base layer 29 is formed.

Next, as shown in (2) of FIG.
By the method, a silicon oxide film 31 is formed on the entire surface on the side of the emitter contact layer 27 to have a predetermined thickness in the range of 300 nm to 500 nm, for example. Thereafter, the emitter electrode opening 32, the base electrode opening 33, and the collector electrode are formed in the silicon oxide film 31 by a lithography technique (for example, a resist film formation by resist coating, exposure, development, and baking) and an etching technique. The opening 34 is formed. Then, after forming a barrier metal layer and a metal wiring layer, patterning is performed to form the emitter electrode opening 32, the base electrode opening 33, the collector electrode opening 34, the emitter electrode 35 connected to the emitter contact layer 27, and the base extraction. A base electrode 36 connected to the electrode 30 and a collector electrode 37 connected to the N ⁺ type sinker region 19 are formed. At this time, in the emitter, since there is the emitter contact layer 27 formed at a high concentration of about 1 × 10 ²⁰ , the ohmic contact can be established.

In this way, the bipolar transistor 1 having the high concentration and thin base layer 29 can be realized.

In the method of manufacturing the bipolar transistor 1, since the high-concentration emitter contact layer 27 is formed by plasma doping, impurities in the P ⁺ -type silicon germanium film 23 which will become the base layer 29,
For example, a temperature at which boron (B) or germanium (Ge) diffuses cannot be applied. Therefore, when the emitter contact layer 27 is formed, diffusion of impurities in the P ⁺ type silicon germanium film 23 can be suppressed.

Next, as a second embodiment of the present invention, an example of a method of forming an emitter contact layer by solid phase diffusion will be described with reference to the manufacturing process chart of FIG. In FIG. 4, the same components as those shown in FIGS. 1 to 3 are designated by the same reference numerals.

(1) and (2) of FIG. 2 and FIG.
Similar to the first embodiment described above, the steps up to forming the N ⁻ type silicon film 24 to be the second conductivity type semiconductor film to be the emitter layer are performed. Next, as shown in (1) of FIG. 4, a phosphorus-doped SOG (Sp) film, which is a dielectric film, is formed on the N ⁻ type silicon film 24 by a coating method.
in on glass) film 41, for example, 100 nm to 150 n
It is formed in a predetermined range in the thickness of m. Since phosphorus (P) is the second conductivity type impurity, the SOG film 41 contains the second conductivity type impurity. Then, 200 ℃ ~ 4
After baking at a predetermined temperature in the range of 00 ° C., a halogen lamp is irradiated in a nitrogen (N ₂ ) atmosphere to radiate it in the range of 500 ° C. to 750 ° C., preferably 600 ° C. to 70 ° C.
Heat treatment is performed at a predetermined temperature in the range of 0 ° C. For example, by heating at 650 ° C. for 30 minutes, the phosphorus (P) in the phosphorus-doped SOG film 41 is an N ⁻ -type silicon film 24.
On the surface layer of the N ⁻ type silicon film 24.
A concentration region of about × 10 ²⁰ pieces / cm ³ is formed with a thickness of about 100 nm. It becomes the N ⁺ type silicon layer 25 corresponding to the high concentration layer.

Since solid-phase diffusion can perform high-concentration doping even at a so-called low temperature of 750 ° C. or lower, boron (B) or germanium (Ge) in the silicon germanium film 23 serving as a base layer diffuses. As a result, the base width is widened and the positions of the heterojunction and the P-N junction are not displaced. The enhanced diffusion of boron (B) due to the emission of interstitial silicon does not occur. Also, silicon germanium (S
The iGe) mixed crystal does not undergo plastic deformation, and a dislocation-free crystal is maintained.

Next, as shown in FIG. 4B, the SOG film 41 is patterned by a lithography technique (for example, resist film formation by resist application, exposure, development, baking, etc.) and an etching technique. Then, the silicon oxide pattern 42 made of the SOG film (41) is formed on the emitter formation region in the active region 17.
To form. The silicon oxide pattern 42 corresponds to the silicon oxide pattern (26) described in the first embodiment. In the patterning, the silicon oxide pattern 42 is formed on the single crystal region so as not to cover the polycrystalline region.

The subsequent steps are performed in the same manner as described in the first embodiment. The heat treatment for forming the N ⁺ -type silicon layer 25 is performed by patterning the SOG film 41 to form a silicon oxide pattern 42 serving as an etching mask.
After forming, a high concentration emitter contact layer (27)
Can also be performed after formation of or after formation of the emitter layer (28).

In the second embodiment, since the N ⁺ type silicon layer 25 which becomes the high-concentration emitter contact layer is formed by solid phase diffusion, the P ⁺ type silicon germanium film 23 which becomes the base layer is formed. No temperature is added during the process such that impurities such as boron (B) or germanium (Ge) diffuse. Therefore, when the emitter contact layer 27 is formed, diffusion of impurities in the P ⁺ type silicon germanium film 23 can be suppressed. Further, in the second embodiment, the SOG film 41 used for doping can be used instead of forming the silicon oxide film serving as the mask for wet etching described in the first embodiment. Therefore, the number of steps can be reduced.

Alternatively, in the second embodiment, the silicon oxide pattern 42 is formed on the SOG film 41 before the solid phase diffusion.
Either by forming the emitter layer with the N ⁻ type silicon film 24 by etching using the silicon oxide pattern 42 as an etching mask, by solid phase diffusion from the silicon oxide pattern 42. An emitter contact layer having a higher concentration than this emitter layer may be formed on the surface layer of the emitter layer.

In the above description of each embodiment, the NPN heterojunction bipolar transistor has been described, but the present invention can be applied to the PNP heterojunction bipolar transistor. In that case, the conductivity type in the above description may be reversed.

[0053]

As described above, according to the present invention,
Since the high-concentration emitter contact layer is formed by plasma doping or solid phase diffusion, a high temperature such as diffusion of impurities in the base layer is not applied. Therefore, the impurity diffusion in the base layer does not occur, so that the base layer can be formed with a high concentration and thinly. Therefore, a high speed bipolar transistor can be realized.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram illustrating the first embodiment.

FIG. 3 is a manufacturing process diagram illustrating the first embodiment.

FIG. 4 is a manufacturing process diagram according to the second embodiment of the present invention.

FIG. 5 is a manufacturing process diagram according to a conventional technique.

FIG. 6 is an explanatory diagram of impurity distribution.

[Explanation of symbols]

1 bipolar transistor 10 substrate 23 P ⁺ type silicon germanium film 24 N ⁻ type silicon film 25 N ⁺ type silicon layer 28 emitter layer 29 base layer

Claims (5)

(57) [Claims] 1. A step of forming a first conductive type semiconductor film which becomes a base layer on a semiconductor substrate, and a step of forming a second conductive type semiconductor film which becomes an emitter layer on the first conductive type semiconductor film. And by plasma doping, impurities are doped into the surface layer of the second-conductivity-type semiconductor film such that the impurity concentration is higher than that of the second-conductivity-type semiconductor film to form a second-conductivity-type high-concentration layer. A method of manufacturing a bipolar transistor, comprising: 2. The method for manufacturing a bipolar transistor according to claim 1, wherein the first conductive type semiconductor film is made of a silicon-germanium compound semiconductor. 3. A process for forming a device isolation region for isolating an element forming region on the surface side of the semiconductor substrate, after forming a polycrystalline silicon film over the whole surface on the front side of the semiconductor substrate, the element isolation formed Forming an opening in the polycrystalline silicon film on the region, and forming a first conductive type semiconductor film serving as a base layer on the entire surface of the semiconductor substrate on the front surface side, and then forming the first conductive type semiconductor film Forming a second conductive type semiconductor film to be an emitter layer thereon; and including a second conductive type impurity having a higher concentration than the second conductive type semiconductor film on the second conductive type semiconductor film. By the step of forming a dielectric film and the solid phase diffusion from the dielectric film, impurities are added to the surface layer of the second conductivity type semiconductor film so that the impurity concentration is higher than that of the second conductivity type semiconductor film. Second solid-phase diffusion to form emitter contact layer A step of forming a high-concentration layer of a conductive type; a step of patterning the dielectric film to form an etching mask for forming an emitter layer; and a step of etching using the etching mask. And a step of patterning the high-concentration layer to form an emitter contact layer and patterning the second conductivity type film to form an emitter layer. 4. The method for manufacturing a bipolar transistor according to claim 3, wherein the first conductive type semiconductor film is made of a silicon-germanium compound semiconductor. 5. A first conductive material serving as a base layer on a semiconductor substrate.
-Type semiconductor film forming step, and second-conductivity-type semiconductor layer to be an emitter layer on the first-conductivity-type semiconductor film
The step of forming a semiconductor film, and the second conductivity type semiconductor containing impurities of the second conductivity type.
By the solid phase diffusion from the membrane formed on the body membrane, the second
The second conductivity type semiconductor film is formed on the surface of the conductivity type semiconductor film.
Even if the impurity concentration is high,
A method of manufacturing a bipolar transistor, comprising the step of forming a second-concentration-type high-concentration layer , wherein the first-conductivity-type semiconductor film is made of a silicon-germanium compound semiconductor. Of manufacturing bipolar transistor.