JPS63172458A - Dynamic memory cell - Google Patents

Abstract

PURPOSE:To improve an integration density without hampering the operation of a memory element, by arranging a memory capacitor and a switching transistor in a vertical direction, and completely isolating each switching transistor with an insulating film. CONSTITUTION:A capacitor is constituted by a first electrode 101 of the capacitor, a second electrode 105a of the capacitor and a second insulating film 104 between both electrodes. Electrons held in the capacitor are moved to a bit line 111 by the ON/OFF actions of a switching transistor including a gate insulating film 107 between a gate electrode 108 and a channel region 106. Thus a potential is made 'High' or 'Low'. The memory capacitor and the switching transistor are arranged in the vertical direction, and each switching transistor is completely isolated with an insulating film. Thus an SOI structure is provided. Therefore, the area of a cell can be reduced and a high integration density can be implemented without hampering the intrinsic operation as a storage element. The switching transistor having a short channel length can be manufactured with good controllability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a dynamic random access memory device.

[Conventional technology]

The configuration of a conventional dynamic random access memory device of this type is shown in FIG.
1 is a P-type silicon semiconductor substrate, 302 is an isolation region between elements, 305 and 307 are first and second polysilicon layers formed on the main surface of the substrate 301 with an insulating film interposed therebetween; 31)
is a bit line formed by an n-type diffusion layer.

In this configuration, the first polysilicon layer 305
The electrons held in the capacitor via the insulating film below the second polysilicon layer 307 are transferred to the bit line 31) by the on/off action of a field effect switching transistor whose gate insulating film is the insulating film below the second polysilicon layer 307. In other words, in a dynamic random access memory device composed of one memory capacitor and one field effect switching transistor, the potential is kept high or low. The memory retention state is determined depending on whether or not electrons are stored in the memory capacitor.

[Problem that the invention seeks to solve]

In the conventional dynamic random access memory device configured in this way, the memory capacitor and the switching transistor, which are the constituent elements, are arranged side by side on the surface of the same semiconductor substrate, so it takes up a certain area. In particular, the capacitance of the source capacitor is proportional to its area, and its minimum area is determined by constraints on circuit operation. Furthermore, with recent advances in integrated circuit technology, there is a trend toward further miniaturization of the elements themselves, and reducing the area of the memory capacitor in this way is significant in terms of increasing the degree of integration. However, soft errors caused by the incidence of charged particles such as so-called alpha rays, which disturb the storage and retention of electrons, which are information, can impede the original function of the memory element.

In view of these conventional circumstances, the present invention provides a dynamic memory cell that can meet the demand for increasing the degree of integration of devices by changing the arrangement of field effect switching transistors that make up the device. is intended to provide.

[Means for solving problems]

In the dynamic memory cell according to the present invention, memory capacitors and switching transistors, which are constituent elements, are arranged vertically, and each switching transistor is completely separated by an insulating film.

■It has a structure.

[Effect]

In this invention, since the memory capacitor and the switching transistor are arranged vertically, and each switching transistor is completely separated by an insulating film, the Sol structure is adopted, so that the original function as a memory element is not inhibited. The degree of integration of the device can be increased.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figure (a) is a top view showing one embodiment of the present invention, and Figure 1 (
b) is a cross-sectional view thereof, in which 101 is a first electrode of a memory capacitor made of a p-type semiconductor substrate;
2 is a first insulating film that separates the first electrode 101 of the capacitor from each part of the switching transistor; 103 is a high concentration p-type semiconductor region; and 104 is a second insulating film for accumulating charge between both electrodes of the capacitor. The film 105a is a second electrode of a capacitor made of an n-type semiconductor or a high melting point metal;
105b is a source region of a switching transistor made of a highly doped n-type semiconductor; 106 is a channel region of a switching transistor made of a highly doped p-type semiconductor; 107
is the gate insulating film of the switching transistor, 10B is the gate electrode (word line) of the switching transistor, 109 is the drain region of the switching transistor, 1) 0 is the wiring 1 between the drain region 109 and the bit line
) 1, 1) 1 is the bit line wiring, 1) 2 is the gate electrode 108 of the switching transistor and the drain region 1 of the switching transistor.
09 and the bit line wiring 1) is an insulating film between the eyebrows for insulating 1.

Next, the operation will be explained.

In this configuration, the first electrode 101 of the capacitor, the second electrode 105a of the capacitor, and the second insulating film 1 between them.
04 is transferred to the bit line 1)1 by the on/off action of the switching transistor including the gate insulating film 107 between the gate electrode 108 and the channel region 106. is set as “High” or “Low”.

That is, in such a dynamic random access memory device composed of one memory capacitor and one field effect switching transistor, the memory retention state is expressed depending on whether or not electrons are Mlil in the memory capacitor. I try to do that.

In the device of this embodiment, the memory cell capacitor and the switching transistor are arranged vertically, and each switching transistor is completely separated by an insulating film.
Since the I structure is adopted, the cell area can be reduced without hindering the original function as a memory element, and high integration can be achieved, and a switching transistor with a short channel length can be manufactured with good controllability.

In the above embodiment, the channel region 106 is entirely made of a p-type semiconductor, but as shown in FIG. 213, and by doing so, in addition to the effect of the above embodiment, bunch through current can be suppressed, and the source region 105
The portion b that is not in contact with the insulating film may be formed of an insulating film. Furthermore, by dividing the drain region into a highly doped n-type semiconductor region 209 and a lightly doped n-type semiconductor region 214 near the channel region (LDD structure), electric field concentration in the channel region near the drain can be suppressed.

[Effects of the Invention] As described above, according to the dynamic memory cell according to the present invention, since the memory capacitor and the switching transistor are arranged vertically, the cell area can be reduced and high integration can be achieved. In addition, in realizing an LDD structure, there is an effect that electric field concentration near the drain can be suppressed without increasing the source resistance (there is also an effect that a switching transistor with a short channel length can be manufactured with good controllability).

[Brief explanation of the drawing]

FIG. 1(a) is a top view showing a dynamic memory cell according to an embodiment of the present invention, FIG.
This figure is a sectional view showing another embodiment of the present invention, and FIG. 3 is a sectional view showing a conventional dynamic memory cell. 101... First electrode of memory capacitor, 102...
- First insulating film, 103...high concentration p-type semiconductor region,
104... Second insulating film, 105a... Second electrode of capacitor, 105b... Source region of switching transistor, 106... Channel region of switching transistor, 107... Gate insulating film of switching transistor , 108... Gate electrode (word line) of switching transistor, 109... Drain region of switching transistor, 1) 0... Through hole, 1) 1... Wiring of bit line, 1) 2...・
Interlayer insulating film, 209...High concentration n-type semiconductor region in the drain region, 213...Insulating region in the channel region, 214...Low concentration n-type semiconductor region in the drain region. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (5)

[Claims] (1) In a semiconductor memory device having a memory cell whose main components are a field effect switching transistor and a memory capacitor, at least a part of one main surface thereof is covered with a first insulating film,
and a first electrode portion of a capacitor made of a conductive substrate having a recess covered by a thin second insulating film, and an n-type semiconductor or high melting point metal adjacent to the thin second insulating film and embedded in the recess. The second capacitor consisting of
an electrode portion; a source region of a switching transistor made of a highly doped n-type semiconductor adjacent to the first insulating film and at least partially buried in the recess; and a first electrode of the capacitor in contact with the source region; A channel region of a switching transistor made of a low-concentration p-type semiconductor formed on a concave portion of the substrate protruding perpendicularly to the main surface of the substrate, a drain region of the switching transistor formed on the channel region, and a connection to the drain region. a thin gate insulating film formed on the side wall of the channel region; a source region, channel region and A dynamic memory cell comprising a word line electrode section consisting of a gate electrode of a switching transistor and insulated from any of the bit line electrode sections. (2) The dynamic memory cell according to claim 1, wherein the conductive substrate is a p-type semiconductor substrate. (3) The dynamic memory cell according to claim 2, wherein a portion of the p-type semiconductor substrate in contact with the thin second insulating film is a highly doped p-type semiconductor. (4) A portion of the channel region or source region of the switching transistor that is not in contact with the gate insulating film or the first oxide film is formed of an insulating film. Dynamic memory cell according to any one of items 1 to 3. (5) The drain region of the switching transistor is characterized in that the n-type impurity concentration in the vicinity of the channel region is significantly lower than in other parts. Dynamic memory cell.