JPS63172337A - Multiplication circuit - Google Patents

Abstract

PURPOSE:To realize the arithmetic tasks at a high speed with a multiplication circuit totalizing the shifts of the lower and higher rank sum shifters concurrently with totalization carried out by a carry storing computing element among the outputs of the higher and lower rank sum shifters and the integer multiple value of a multiplicand and repeating the totalization and the shift by a fixed frequency to obtain a product of a multiplier and a multiplicand. CONSTITUTION:The output of a multiplicand shifter 2a, the value of a higher rank sum register 12 and the value of a higher rank carriage register 13 are supplied to a carry storing computing element 6a. Then an arithmetic task decided by an arithmetic control circuit 7a is carried out and the S (total sum) output obtained from said arithmetic task is shifted arithmetically to the right by 2 bits via a higher rank sum shifter 10 to be stored into the register 12. The C (total carry) output is shifted arithmetically to the right by 2 bits via a higher rank carry shifter 8 and stored into the register 13. At the same time, the digit overflow produced from the shifter 10 is used as a carry input and the numerical value held by a lower rank sum register 14 is shifted to the right by 2 bits via a lower rank sum shifter 11. These arithmetic and shift tasks are repeated by the frequency equal to the value obtained by dividing the length of a multiplier by 2 if the multiplier has the even bit length and the frequency equal to the value obtained by dividing the bit length of the multiplier plus 1 by 2 when the multiplier has the odd bit length.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiplication circuit that performs signed multiplication.

Disclosure Bulletin Mol
, 27 Δhills 11 people pri11985.

FIG. 3 shows a block diagram of this conventional multiplier circuit, in which 1 is a multiplicand register for inputting and holding the multiplicand;
is a multiplier register that inputs a multiplier at the start of multiplication and holds the multiplier that is right-tufted by 2 pits during the calculation process.
3 is a high-order product register that holds the high-order part of the accumulated partial product during calculation processing, and stores the high-order value of the product that is the calculation result when the calculation ends; The lower product register holds the lower part and stores the lower part of the product when the calculation is completed. 6b is an arithmetic circuit that performs the calculation between the two inputs of person and B. 7b is the lower 2 bits of multiplier register 3 and a carry flag to be described later. 6 is an arithmetic control circuit that controls the arithmetic operation executed by the arithmetic circuit 6b and the selection of the B input of the arithmetic circuit 6b; 4 is a control circuit that shifts the value held in the multiplier register 3 by 2 bits to the right and transfers the result back to the multiplier register 2;
A multiplier shifter 22 arithmetic shifts the output of the arithmetic unit v8sb, which is the upper part of the cumulative partial product, to the right by 2 bits (the sign bit is copied from the left) and stores it in the upper product register 2.
The upper cumulative partial product shifter 21 stores the overflow of the upper cumulative partial product shifter 22 from the left as a carry input, and moves the lower part of the cumulative partial product held in the lower product register 20 to the right. A lower accumulation partial product shifter that shifts the result by 2 bits and stores the result in the lower product register 20 again; 6 is a carry flag that maintains the overflow of the multiplier shifter 4; 26 is a doubling circuit for obtaining the double value of the multiplicand; 24 is a selection circuit that selects the multiplicand or the double value of the multiplicand based on the output of the arithmetic control circuit 7b and adds it to the B input of the arithmetic circuit 6b.

The operation of the conventional multiplication circuit configured as described above will be described below.

Booth's algorithm is a multiplication method.

This conventional multiplier circuit is based on the 3-bit Booth algorithm ("Looking at multiplier circuit systems based on parallel operation methods, which are increasingly becoming LSI", Nikkei Electronics 1978.5,
29pp, 76-90), and the LSB of the multiplier
The product is obtained by cutting out three bits from each side (one bit of which is an overlamp), selecting partial products, and accumulating the partial products. FIG. 4 is a control table diagram of the arithmetic control circuit 7b based on this algorithm, in which the lower two bits of the multiplier register 2 and a total of three bits of the carrier lag are decoded to perform the arithmetic operation of the arithmetic circuit 6b and the B of the arithmetic circuit 6b.
It determines the input.

The operation of the circuit will be explained below.

First, a multiplicand and a multiplier are input into multiplicand register 1 and multiplier register 3, respectively, and upper product register 23, lower product register 2o, and carry flag 6 are cleared to zero.

The calculation and B input of the calculation circuit 6b are determined from the lower two bits of the multiplier register 3 and the carry flag 6, and if the calculation column in FIG. -1-B", the result is the addition of the A input and the B input, and "mu B", the result is the subtraction of the B input from the mu input. In addition, the B input is selected by the selection circuit 24 as "X".
If the multiplicand register 1 is 2x'', then the double circuit 26
output is selected. After the calculation, the multiplier shifter 4, the upper cumulative partial product shifter 22, and the lower cumulative partial product shifter 21 all perform an arithmetic shift to the right by 2 bits, and store the shift results in respective predetermined registers.

The above operations and shifts are repeated twice when the multiplier has an even bit length, and (multiplier bit length+1)÷2 times when the multiplier has an odd bit length.

The multiplication results are held in the upper product register 3b and the lower product register 4 separately into upper and lower parts.

Problems to be Solved by the Invention However, the above configuration has the problem that the calculation time in the diameter calculation circuit 6b, where the bit length of the multiplicand is long, increases due to the carry propagation time in the calculation circuit 6b. Was. .

In view of this, an object of the present invention is to provide a multiplication circuit capable of high-speed calculation using an arithmetic circuit whose calculation time does not depend on the bit length of the multiplicand.

Means for Solving the Problems The present invention provides a three-input carry save arithmetic unit used for accumulation processing, an upper thumb shifter for shifting the sum output of the carry save arithmetic unit, and a carry input for overflow of the upper thumb shifter. an upper carry shifter that shifts the carry output of the carry save arithmetic unit, and a lower carry shifter that takes the overflow of the upper carry shifter as a carry input; and the output of the upper carry shifter and an integer multiple of the multiplicand, a shift of the lower thumb shifter and a shift of the lower carrier 7 are performed together with the accumulation, and the accumulation and the shift are repeated a fixed number of times. The multiplication circuit is characterized in that it obtains the product of a multiplier and the multiplicand.

Effect: Since the present invention includes a carry-existence arithmetic unit without carry propagation, high-speed multiplication is possible without depending on the bit length of the multiplicand.

Embodiment FIG. 1 shows a block diagram of a multiplication circuit in an embodiment of the present invention. 1 is a multiplicand register that inputs and holds a multiplicand, 2 is a multiplicand register that is specified by the arithmetic control circuit T& described later and shifts the Q bit or 1-bit multiplicand, and 3 is a multiplicand register that inputs a multiplicand at the start of multiplication and 2 during arithmetic processing. 4 is a multiplier shifter that shifts the value held in multiplier register 3 to the right by 2 bits and holds it again; 6 is a multiplier shifter that holds the value held in multiplier register 3. A carry flag holds the digit shift when shifted to the right, and 12 is an upper sum register that holds the upper part of the accumulated value (hereinafter referred to as accumulated sum) that does not include carry by accumulating partial products during arithmetic processing. , 13 is an upper carry register that holds the upper part of the carry (hereinafter referred to as accumulated carry) generated by accumulation of partial products during arithmetic processing; 6
10 is a carry save arithmetic unit that performs an operation between the outputs of the upper sum register 12, the upper carry register 13, and the output of the multiplicand shifter 2, and outputs the accumulated sum and carry; The upper sum shifter performs a 2-bit arithmetic shift of the accumulated sum to the right, and 13 is a carry save arithmetic unit 6.
An upper carry shifter that arithmetic shifts the accumulated carry output from a by 2 bits to the right; 14 is a lower sum register that holds the lower part of the accumulated sum; 15 is a lower carry register that holds the lower part of the accumulated carry; 11 is the upper register. A lower thumb shifter uses the overflow from the thumb shifter 10 as a carry input and shifts the numerical value held in the lower sum register 14 to the right by 2 bits. 9 is the numerical value held in the lower carry register 16 as a carry input for all overflow from the upper carry shifter 8. The lower carry shifter 17 shifts 2 bits to the right of the lower sum register 141 after the operation by the carry save arithmetic unit 6a is completed.
- a lower adder for adding the lower carry register 15, 1;
An upper adder 19 6 performs addition between the upper sum register 12 and the upper carry register 13 using the carry output of the lower adder 17 as a carry input after the operation of the carry save arithmetic unit 6 is completed.
18 is a lower product register that holds the numerical value output from the lower adder 17 and stores the lower part of the product as the calculation result, and 18 holds the numerical value output from the upper adder 16 and stores the higher part of the product as the calculation result. The upper product register 7a inputs the lower two bits of the multiplier register 3 and the carry flag 5, and performs an operation in the carry save arithmetic unit 6 and the multiplicand shifter 2.
This is an arithmetic control circuit that controls the number of shifts.

Regarding the multiplication circuit of this embodiment configured as above,
The operation will be explained below.

FIG. 2 is a control table diagram of the arithmetic control circuit 7a, in which the lower two bits of the multiplier register 3 and a total of three bits of the carry flag 6 are decoded to perform the operation of the carry save arithmetic unit 6& and the shift number of the multiplicand thick 2. It is up to you to decide. In Figure 2, the operation “Jinshi B” is the addition of A input and B input, “A
+B+I" is the addition of human power, B input, and labor input, "A-1
-B-I” represents the addition of human power and B input and the subtraction of manpower input.When the manpower input is X, the multiplicand is input as is without shifting, and when it is 2x, the initial multiplier? The carry save arithmetic unit 82L is assumed to be able to perform the above operations, and its outputs are S (accumulated sum) and C (accumulated carry).

First, a multiplicand and a multiplier are input into multiplicand register 1 and multiplier register 3, respectively, and upper sum register 12, upper carry register 13, lower sum register 14, lower carry register 16, and carry flag 5 are cleared to zero.

The output of the multiplicand shifter 2, the value of the high-order sum register 12, and the value of the high-order carry register 13 are input to the carry-save arithmetic unit 61L, and the arithmetic operation determined by the arithmetic control circuit 71L is performed.
The resulting S output is shifted to the right by the upper thumb shifter 1o.
The C output is arithmetic shifted by 2 bits to the right by the upper carry shifter 8, and the shifted value is stored in the upper carry register 13. Top thumb shifter 10 at the same time
Lower sum register 1 as carry input for overflow from
The numerical value held at 4 is shifted to the right by 2 bits by the lower sum shifter 11, and the shifted value is stored in the lower sum register 14. At the same time, the overflow from the upper carry shifter 8 is used as a carry input, and the value held in the lower carry register 15 is shifted to the right by 2 bits by the lower carry shifter 9, and the shifted value is stored in the lower carry register 16. On the other hand, the multiplier shifter 4 shifts the multiplier register 3 to the right by 2 bits and stores it in the multiplier register 3.

The above operations and shifts are performed by dividing the focus length of the multiplier by 2 times when the multiplier has an even number of bits, and by dividing the focus length of the multiplier by 2 times when the multiplier has an odd number of bits.
Multiplier pit length + 1) ÷ repeated 2 times.

After the operation in the carry save arithmetic unit 6& is completed, the multiplication result is obtained by adding the numerical values in the lower sum register 14 and the lower carry register 15 by the lower adder 17 and storing it in the lower product register 19.
The numerical values in the upper sum register 12 and the upper carry register 13 are added by the upper adder 16 using the carry output of the lower adder 17 as the carry input, and then stored in the upper product register 18, respectively. The multiplication results are held in the upper product register 18 and the lower product register 19 separately into upper and lower parts.

In the embodiment, two adders, the upper adder 16 and the lower adder 1, are used, but these adders 16 and 17
'i is one adder, a selection circuit is provided on the input side of this adder, first the sum of the lower sum register 14 and the lower carry register 15 is calculated and stored in the lower product register 19, and then this carry output Alternatively, the sum of the upper sum register 12 and the upper carry register 13 may be calculated and stored in the upper product register 18.

As described in detail, according to the present invention, since the calculation time during multiplication processing does not depend on the pit length of the multiplicand, signed multiplication can be performed at high speed, and its practical effects are significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiplication circuit according to an embodiment of the present invention, FIG. 2 is a control table diagram of an arithmetic control circuit according to the same embodiment, FIG. 3 is a block diagram of a conventional multiplication circuit, and FIG. 4 is a block diagram of a conventional multiplication circuit. FIG. 3 is a control table diagram of the arithmetic control circuit of the circuit. 1... Multiplicand register, 2a, 2b...
・Multiplicand shifter, 3... Multiplier register, 4...
... Multiplier shifter, 5 ... Carry flag, 6
a...Carry storage arithmetic unit, 6b...Carry propagation arithmetic unit, 72L, 7b...Arithmetic control circuit, 8...Upper carry shifter, 9・・・・・・
・Lower carry shifter, 1o... Upper thumb shifter, 11°°゛... Lower thumb shifter, 12...
Upper sum register, 13... Upper carry register, 14... Lower sum register, 16...
...lower carry register, 16°°. ... Upper adder, 17 ... Lower adder, 18
...Upper product register, 19...Lower product register, 20...91. Lower product register, 21...
...Lower accumulated partial product shifter, 22... Upper accumulated partial product shifter, 23... Upper product register,
24...Selection circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] A 3-input carry save arithmetic unit used for accumulation processing, an upper thumb shifter that shifts the sum output of the carry save arithmetic unit, a lower thumb shifter that uses the overflow of the upper thumb shifter as a carry input, and the carry save arithmetic unit. an upper carry shifter that shifts the carry output of the upper carry shifter, and a lower carry shifter that takes the overflow of the upper carry shifter as a carry input, and the output of the upper thumb shifter by the carry save arithmetic unit, the output of the upper carry shifter, and an integer multiple of the multiplicand. and shifting the lower thumb shifter and shifting the lower carry shifter together with the accumulation,
A multiplication circuit characterized in that the product of the multiplier and the multiplicand is obtained by repeating the accumulation and the shift a certain number of times.