JPS6317220B2 - - Google Patents
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- Publication number
- JPS6317220B2 JPS6317220B2 JP56111869A JP11186981A JPS6317220B2 JP S6317220 B2 JPS6317220 B2 JP S6317220B2 JP 56111869 A JP56111869 A JP 56111869A JP 11186981 A JP11186981 A JP 11186981A JP S6317220 B2 JPS6317220 B2 JP S6317220B2
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- Prior art keywords
- silicon
- film
- insulating film
- substrate
- crystal silicon
- Prior art date
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 4
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 3
- 239000010408 film Substances 0.000 description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910020781 SixOy Inorganic materials 0.000 description 4
- 238000001953 recrystallisation Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- -1 that is Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特に絶縁膜上
に形成されるSOI（Silicon on Insulating
Substrate）構造の半導体装置の製造方法に関す。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, especially SOI (Silicon on Insulating) formed on an insulating film.
This invention relates to a method for manufacturing a semiconductor device having a substrate structure.
例えば酸化シリコンよりなる絶縁膜上に島状に
分離された半導体素子を形成するSOI構造の半導
体装置の製造工程において、絶縁膜上の非単結晶
シリコンすなわち多結晶シリコン或いは非結晶シ
リコンにより形成された島状に分離された薄膜状
半導体領域を波動或いは粒子ビーム照射による熱
処理により融解し、冷却再結晶化せしめて単結晶
シリコンとする場合において、融解されたシリコ
ンの絶縁膜を形成する二酸化シリコン（SiO2）
面への濡れの悪さから、単結晶化後に半導体領域
が絶縁膜から剥離することがあるなど、付着力が
不充分である。 For example, in the manufacturing process of semiconductor devices with an SOI structure in which semiconductor elements separated into islands are formed on an insulating film made of silicon oxide, non-monocrystalline silicon, that is, polycrystalline silicon or amorphous silicon formed on an insulating film, is used. When thin film-like semiconductor regions separated into islands are melted by heat treatment using wave or particle beam irradiation, and then cooled and recrystallized to form single-crystal silicon, silicon dioxide (SiO 2 )
Due to poor surface wetting, the semiconductor region may peel off from the insulating film after single crystallization, resulting in insufficient adhesion.
本発明は、前記の如く再結晶化により形成され
た単結晶シリコン領域と酸化シリコン絶縁膜との
付着力を増大し、剥離等の障害を未然に防止する
ことを目的とする。 An object of the present invention is to increase the adhesion between the single crystal silicon region formed by recrystallization as described above and the silicon oxide insulating film, and to prevent problems such as peeling.
本発明は酸化シリコン絶縁膜の表面近傍におい
て、酸素原子に対してシリコン原子を過剰とする
ことにより、その表面上に融解再結晶により形成
された単結晶シリコン薄膜との付着力を増加せし
めるものである。 The present invention increases the adhesion force with the single-crystal silicon thin film formed on the surface of the silicon oxide insulating film by melting and recrystallization by making silicon atoms in excess of oxygen atoms near the surface of the silicon oxide insulating film. be.
以下に本発明を実施例により図面を用いて詳細
に説明する。 The present invention will be explained in detail below using examples and drawings.
第１図ａに断面図を示す如く、シリコン基板１
上に二酸化シリコン（SiO2）により厚さ約500n
ｍの絶縁膜２を形成する。二酸化シリコン絶縁膜
２はモノシラン（SiH4）10％：アルゴン（Ar）
90％の混合気体と酸素（O2）とを容量比200：１
として、温度約650℃の反応管内で反応せしめる
化学蒸着法により基板１上に成長せしめられる。 As shown in the cross-sectional view in FIG. 1a, a silicon substrate 1
Approximately 500n thick with silicon dioxide (SiO 2 ) on top
m insulating film 2 is formed. Silicon dioxide insulating film 2 is monosilane (SiH 4 ) 10%: argon (Ar)
90% mixed gas and oxygen (O 2 ) volume ratio 200:1
The film is grown on the substrate 1 by a chemical vapor deposition method in which a reaction is carried out in a reaction tube at a temperature of about 650°C.
次いで前記モノシランの混合気体と酸素との容
量比を1000：１程度として、酸素原子に対してシ
リコン原子の過剰な酸化物SixOyにより膜３を厚
さ100nｍに成長せしめる。しかる後酸素の供給
を完全に停止し、多結晶シリコン膜４を厚さ約
400nｍに成長せしめる。 Next, the film 3 is grown to a thickness of 100 nm using an oxide SixOy containing an excess of silicon atoms relative to oxygen atoms, with the volume ratio of the monosilane gas mixture to oxygen being about 1000:1. After that, the supply of oxygen is completely stopped, and the polycrystalline silicon film 4 is reduced to a thickness of approximately
Grow to 400nm.
なお多結晶シリコン膜４形成後、通常の気相成
長法によつて、窒化シリコン（Si3N4）膜５を厚
さ約100nｍ成長せしめ被覆層とすることが望ま
しい。以上の実施例の如くに形成された第１図ａ
の如き構造を有する基板に対して、第１図ｂの断
面図に示す如く、窒化シリコン膜５及び多結晶シ
リコン膜４を選択的に除去して島状に分離された
領域を形成し、波動或いは粒子ビーム照射により
多結晶シリコン膜４を融解、再結晶せしめて単結
晶シリコン膜よりなる領域４′を得る。 After forming the polycrystalline silicon film 4, it is preferable to grow a silicon nitride (Si 3 N 4 ) film 5 to a thickness of about 100 nm by a normal vapor phase growth method to form a covering layer. FIG. 1a formed as in the above embodiment
As shown in the cross-sectional view of FIG. 1b, the silicon nitride film 5 and the polycrystalline silicon film 4 are selectively removed from a substrate having a structure as shown in FIG. Alternatively, the polycrystalline silicon film 4 is melted and recrystallized by particle beam irradiation to obtain a region 4' made of a single-crystalline silicon film.
本実施例においては、融解したシリコンはシリ
コン過剰なシリコン酸化物上にあるために、二酸
化シリコン上にある場合と異なり濡れ性が良く、
単結晶シリコン領域４′とSixOy膜３との付着力
は充分にある。 In this example, since the molten silicon is on silicon oxide with excess silicon, it has good wettability unlike when it is on silicon dioxide.
Adhesion between the single crystal silicon region 4' and the SixOy film 3 is sufficient.
更に窒化シリコン膜５を被覆層とすることによ
り、再結晶後の単結晶シリコン領域４′の上面は
平滑であり、更にSixOy膜３との付着力が強化さ
れる効果を有する。 Further, by using the silicon nitride film 5 as a covering layer, the upper surface of the single crystal silicon region 4' after recrystallization is smooth, and the adhesive force with the SixOy film 3 is further strengthened.
次に他の実施例を第２図ａ及びｂの断面図を用
いて説明する。単結晶シリコン基板１１上の半導
体素子を形成すべき位置に選択的に二酸化シリコ
ン膜１２を熱酸化法により厚さ約600nｍに形成
し、次いで基板全面に前記例と同様な化学蒸着法
により多結晶シリコン膜１３を厚さ約100nｍに
成長せしめる。この基板全面にAr+イオンを約
180KeVにて１×1016／cm2程度のドーズ量にイオ
ン注入すると、多結晶シリコン膜１３中のシリコ
ン原子がAr+イオンとの衝突により５×1015／cm2
程度二酸化シリコン膜１２中に入る。なお本実施
例においては、Ar+イオンの分布のピークは二酸
化シリコン膜１２中にある。 Next, another embodiment will be described using the cross-sectional views of FIGS. 2a and 2b. A silicon dioxide film 12 is selectively formed on the single crystal silicon substrate 11 at a position where a semiconductor element is to be formed to a thickness of about 600 nm by a thermal oxidation method, and then a polycrystalline silicon film 12 is formed on the entire surface of the substrate by a chemical vapor deposition method similar to the above example. A silicon film 13 is grown to a thickness of about 100 nm. Approximately Ar + ions are applied to the entire surface of this substrate.
When ions are implanted at a dose of about 1×10 16 /cm 2 at 180 KeV, silicon atoms in the polycrystalline silicon film 13 collide with Ar + ions, resulting in 5×10 15 /cm 2
It enters into the silicon dioxide film 12 to a certain extent. Note that in this embodiment, the peak of the distribution of Ar + ions is located in the silicon dioxide film 12.
以上の如く、二酸化シリコン膜１２の表層部分
１２′をシリコン過剰とした後に、再び化学蒸着
法により多結晶シリコンを厚さ約400nｍ成長せ
しめて、多結晶シリコン膜１４を得る。 As described above, after the surface layer portion 12' of the silicon dioxide film 12 is made to have an excess of silicon, polycrystalline silicon is grown to a thickness of about 400 nm by chemical vapor deposition again to obtain the polycrystalline silicon film 14.
次いで、例えば10W連続波アルゴンレーザ光を
ビーム直径50μｍ、50％オーバーラツプとして10
cm／secの速度で走査照射することにより、多結
晶シリコン膜１４を融解し、再結晶せしめると
き、基板１１に接する部分より基板１１の単結晶
にエピタキシヤルに再結晶化が進行し、二酸化シ
リコン膜１２の上部に及んで単結晶シリコン膜１
４′を得る。本実施例においても前記実施例と同
様に単結晶シリコン膜１４′と二酸化シリコン膜
１２との付着力は充分である。 Next, for example, a 10W continuous wave argon laser beam is used with a beam diameter of 50μm and a 50% overlap.
When the polycrystalline silicon film 14 is melted and recrystallized by scanning irradiation at a speed of cm/sec, recrystallization progresses epitaxially to the single crystal of the substrate 11 from the part in contact with the substrate 11, and the silicon dioxide The single crystal silicon film 1 extends over the top of the film 12.
We get 4'. In this embodiment, as in the previous embodiment, the adhesion between the single crystal silicon film 14' and the silicon dioxide film 12 is sufficient.
なお前記第二の実施例の多結晶シリコン膜１３
を200nｍ程度と厚くし、同様のAr+イオン注入を
行えばAr+イオン分布のピークは多結晶シリコン
膜１３中にあり、一旦この多結晶シリコン膜１３
を除去し、改めて多結晶シリコン膜１４を成長せ
しめても同様の効果が得られる。 Note that the polycrystalline silicon film 13 of the second embodiment
If the thickness is increased to about 200 nm and similar Ar + ion implantation is performed, the peak of Ar + ion distribution will be in the polycrystalline silicon film 13, and once this polycrystalline silicon film 13
The same effect can be obtained by removing the polycrystalline silicon film 14 and growing the polycrystalline silicon film 14 again.
前記各実施例の如く、表層部分を深部よりシリ
コン過剰とした酸化シリコン絶縁膜上に形成され
た単結晶シリコン領域４′或いは１４′に半導体素
子を形成すれば、絶縁膜との付着力不足等の懸念
なく安定した半導体素子を得ることが可能とな
る。 As in each of the above embodiments, if a semiconductor element is formed in the single crystal silicon region 4' or 14' formed on a silicon oxide insulating film in which the surface layer has an excess of silicon from the deep part, problems such as insufficient adhesion with the insulating film will occur. This makes it possible to obtain a stable semiconductor element without any concerns.
本発明は以上説明した如く、シリコン基板上に
酸化シリコンよりなる絶縁膜を形成し、該絶縁膜
上の非単結晶シリコン領域を波動或いは粒子ビー
ム照射により融解再結晶せしめて単結晶シリコン
とし、これより半導体素子を形成するSOI構造の
半導体装置の製造方法において、該絶縁膜の表層
部分をシリコン過剰とすることにより単結晶シリ
コン領域と該絶縁層との付着力を充分ならしめる
ものであつて、SOI構造の半導体装置の発展に大
きく寄与する。 As explained above, the present invention forms an insulating film made of silicon oxide on a silicon substrate, melts and recrystallizes a non-single crystal silicon region on the insulating film by wave or particle beam irradiation to form single crystal silicon. In a method for manufacturing a semiconductor device having an SOI structure in which a semiconductor element is formed, the surface layer portion of the insulating film is made to have an excess of silicon to ensure sufficient adhesion between the single crystal silicon region and the insulating layer, This will greatly contribute to the development of semiconductor devices with SOI structure.
第１図ａ及びｂは本発明の一実施例を示す基板
断面図、第２図ａ及びｂは本発明の他の実施例を
示す基板断面図である。
図において、１はシリコン基板、２は二酸化シ
リコン絶縁膜、３はSixOy膜、４は多結晶シリコ
ン膜、５は窒化シリコン膜、１１はシリコン基
板、１２は二酸化シリコン膜、１２′はシリコン
過剰な表層部分、１３は多結晶シリコン膜、１４
は多結晶シリコン膜を示す。
1A and 1B are cross-sectional views of a substrate showing one embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views of a substrate showing another embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a silicon dioxide insulating film, 3 is a SixOy film, 4 is a polycrystalline silicon film, 5 is a silicon nitride film, 11 is a silicon substrate, 12 is a silicon dioxide film, and 12' is an excess silicon film. Surface layer portion, 13, polycrystalline silicon film, 14
indicates a polycrystalline silicon film.
Claims (1)
成し、前記絶縁膜を含む前記基板面上に非単結晶
シリコン膜を形成し、前記非単結晶シリコン膜を
波動或いは粒子ビーム照射により融解後結晶化せ
しめて単結晶シリコン膜とし、前記単結晶シリコ
ン膜に半導体素子を形成する半導体装置の製造方
法において、前記絶縁膜の深部に比較し表層部分
において酸素原子に対しシリコン原子を過剰とす
ることを特徴とする半導体装置の製造方法。1. An insulating film made of silicon oxide is formed on a substrate, a non-single-crystal silicon film is formed on the surface of the substrate including the insulating film, and the non-single-crystal silicon film is melted by wave or particle beam irradiation and then crystallized. In the method for manufacturing a semiconductor device, in which a semiconductor element is formed in the single crystal silicon film, silicon atoms are present in excess of oxygen atoms in the surface layer of the insulating film compared to the deep part of the insulating film. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111869A JPS5814529A (en) | 1981-07-17 | 1981-07-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111869A JPS5814529A (en) | 1981-07-17 | 1981-07-17 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5814529A JPS5814529A (en) | 1983-01-27 |
| JPS6317220B2 true JPS6317220B2 (en) | 1988-04-13 |
Family
ID=14572196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56111869A Granted JPS5814529A (en) | 1981-07-17 | 1981-07-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814529A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0614511B2 (en) * | 1983-05-10 | 1994-02-23 | ソニー株式会社 | Crystallization method of semiconductor thin film |
| JPS61270812A (en) * | 1985-05-22 | 1986-12-01 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Manufacture of semiconductor device |
-
1981
- 1981-07-17 JP JP56111869A patent/JPS5814529A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5814529A (en) | 1983-01-27 |
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