JPS63172193A - Driving of active matrix type display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A scan canvas line and a data bus line in an active matrix display device are formed on one glass substrate and the other glass substrate, and a switching element is provided between the scan canvas lines. By connecting and omitting the ground pass line, we aim to improve manufacturing yield and driving area ratio.
In addition, the polarity of the data voltage applied to the data bus line is inverted every time the scan canvas line is scanned, and the potential immediately before the application of the address pulse applied to the scan canvas line is set to the display level rOJ applied to the display element and the display level. The voltage is set to an intermediate value between "1" and the data voltage can be selected to a low value, and fluctuations in the effective value voltage applied to the display element are suppressed, enabling highly accurate gradation display. That is.

[Industrial application field]

The present invention relates to a method for driving an active matrix display device of a facing matrix type in which switching elements are connected between adjacent scan canvas lines.

Active matrix display devices can control a large number of pixels independently, so even if the number of lines increases with an increase in display capacity, the drive duty ratio decreases, unlike a simple matrix display device. It has the advantage of not causing problems such as a decrease in contrast or a decrease in viewing angle, and has been put into practical use as display devices for portable television receivers and small information terminal devices. but,
In order to use it in place of a CRT (cathode ray tube) display device, it is necessary to further improve the display quality, and in particular, obtaining good gradation display characteristics is an important issue.

[Conventional technology]

Active matrix display devices use liquid crystal as the display medium and thin film transistors (
TPT) is common. FIG. 5 is an explanatory diagram of a conventional display panel, in which liquid crystal is used as a display medium, 30 is a liquid crystal display panel, 31 is a thin film transistor (hereinafter abbreviated as rTFTJ) as a switching element, and 35 is a display medium. 36 is a scan canvas line, 37 is a data bus line, 41 is a data bus driver, and 42 is a scan canvas driver. Further, Cd is the capacitance between the drain and source of the TPT 31, and Cc is the capacitance of the liquid crystal cell 35.

The gate of T F T 31 is connected to the scan canvas line 36, the drain is connected to the data bus line 37, the source is connected to one electrode of the liquid crystal cell 35, and the other electrode of this liquid crystal cell 35 is connected to all cells. Serves as a common ground electrode.

TPT 31 connected to scan canvas line 36 to which address pulse from scan canvas driver 42 is applied
is in the on state, and the data voltage applied from the data bus driver 41 to the data bus line 37 is applied to the liquid crystal cell 35 via the TPT 31 which is in the on state, and the data voltage is applied to the capacitance of the liquid crystal cell 35. It is held by CC until the next address pulse is applied to the same scan canvas line 36.

FIG. 6 is an explanatory diagram of the operation, where fat is the address pulse applied to the scan canvas line 36, (b) is the data voltage applied to the data bus line 37, and +C) is the liquid crystal cell 3.
This is the voltage applied to 5. Scan canvas line 3
6, the address pulse shown in (a) is applied every frame, and the TPT 31 to which this address pulse is applied to the gate is in the on state, and the data bus line 37 is as shown in fb). A data voltage whose polarity is inverted every frame is applied, and T is turned on.
A data voltage is applied to the liquid crystal cell 35 via the PT 31 and held by the capacitance Cc until the next frame.

However, since data voltages to be applied to the liquid crystal cells are sequentially sent to the data bus line 37 from the data bus driver 41 via TPTs connected to other scan canvas lines, this data voltage is applied to the TPTs 37 in the off state. The data voltage is applied to the liquid crystal cell 35 through the drain-source capacitance Cd of
The voltage applied to 5 varies between the dotted line and the solid line.

In other words, the liquid crystal cell voltage, which is held for one frame and maintains the display state, changes due to the influence of the data voltage of other lines. 36, the display becomes uneven as if it had a tail in the scanning direction.

Therefore, as shown in FIG. 7, a method was proposed in Japanese Patent Application No. 61-60804 in which the polarity of the data voltage is inverted every time the scan line is scanned. In the figure, (al indicates an example of input data, F indicates the period of one field, and (b) indicates the data voltage applied to the i-th data bus line, Dj, Dj+1.Dj+2.
... is j, j+l, j+2. . . . indicates the data voltage applied when the th scan line is scanned. Further, (C) shows the address voltage applied to the j-th scan bus line, and (d) shows the voltage of the liquid crystal cell at the intersection of the i-th data bus line and the j-th scan bus line. Further, (el is an address pulse applied to the j+1th scan canvas line, and (f) is the voltage of the liquid crystal cell at the intersection of the i-th data bus line and the j+1th scan canvas line.

When the address pulse shown in (e) is applied to the j-th scan bus line, (b) is applied to the i-th data bus line.
), the positive data voltage Dj is applied to the liquid crystal cell at the intersection of the j-th scan line and the i-th data bus line, and is maintained until the next frame. Therefore, the liquid crystal cell voltage is as shown in (d).

Then, on the next j+1st scan line, (e
), by applying a negative data voltage Dj+1 to the i-th data bus line, the liquid crystal cell at the intersection of the i-th data bus line and the j+1-th scan canvas line is , negative polarity data voltage Dj+1 is applied and held until the next frame, so the liquid crystal cell voltage becomes as shown in (f).

In the Bunmu frame, the liquid crystal cell at the intersection of the i-th data bus line and the j-th scan bus line,
The polarity of the data voltage is controlled so that a negative data voltage is applied.

゛As mentioned above, data voltages of positive polarity and negative polarity are applied alternately to the data bus line, and this data voltage is applied to the liquid crystal cell via the capacitance Cc between the drain and source of the TPT. Therefore, even if the amount of change is larger than when data voltages of the same polarity are applied, the time average value of the liquid crystal cell voltage is independent of the polarity of the data voltage (is approximately constant).

In the above-mentioned display panel, the scan canvas line 36 and the data bus line 37 are formed on the same substrate, so it is necessary to prevent short circuits at the intersection, which makes it difficult to improve the manufacturing yield. there were. Therefore, a facing matrix type display panel was proposed in which no intersection occurs on the same substrate. Figure 8 was originally published in Japanese Patent Application No. 61-2126.
FIG. 9 shows an exploded perspective view of the equivalent circuit of the facing matrix type display panel proposed as No. 93.

This display panel consists of one glass substrate 3 disposed facing each other.
9, the TPT 31 and one electrode 38 of the liquid crystal cell 35
and a scan canvas line 36 are formed.The gate 32 of the TPT 31 is connected to the scan canvas line 36, the drain 33 is connected to one electrode 38 of the liquid crystal cell 35, and the source 34 is connected to the adjacent scan canvas line 36. However, a striped data bus line 37 is formed on the other glass substrate 40 as the other electrode of the liquid crystal cell 35. Also Vd1. Vd2. ...is the 1st, 2nd
The data voltage applied to the data bus line of th,...
Vgl, Vg2. ... is number 1.

The second address pulse is applied to the scan canvas lines. .

In this display panel, the scan canvas line 36 and the data bus line 37 are formed on different substrates, so there is no need to insulate the intersections, so the manufacturing yield can be improved. In addition, since the electrode of the liquid crystal cell 35 can be made large, there is an advantage that the driving area ratio can be increased.

FIG. 10 is an explanatory diagram of the operation, where (a) is the data voltage, (
bl, (C1 is the address pulse applied to the scan canvas line, (d) is the potential of the display electrode of the liquid crystal cell, (el
indicates the voltage across the liquid crystal cell. The address pulse is a potential Vgof to turn off the TPT31 during non-address.
For f, the potential immediately before address is Vgc, and the potential at address is V go to turn on the TFT 31.
n, and the relationship is selected such that Vgc-Vgoff≧2■a.

For example, at time tQ, an address pulse that becomes the potential Vgon is applied to the j-th scan line at time t1, and at time t1, a data voltage +Va is applied to the i-th data bus line. At t1, an address pulse is applied to the j+1st scan canvas line at a potential Vgc, and at the next time t2, an address pulse that becomes a potential Vgon is applied, and the potential V
When gc is 0■, at time t1, a data voltage +Va is applied to the liquid crystal cell 35 at the intersection of the j-th scan line and the i-th data bus line via the TFT 31.
is applied and held for one frame F as shown in tel.

Similarly, the scan canvas line adjacent to the scan canvas line to which the address pulse is applied can serve as a ground pass line to apply a data voltage to each liquid crystal cell.

[Problem that the invention seeks to solve]

The previously proposed driving method shown in FIG. 7 alternately switches the data voltage applied to the data bus line between positive and negative polarities, and changes the time average value of the liquid crystal cell voltage regardless of its polarity. Although the display brightness of the liquid crystal cell is determined by the effective value (rms) voltage applied to the liquid crystal cell, it is determined by the time average value of the liquid crystal cell voltage. Even if the value is constant, if the effective value changes, the display brightness will also change, making it difficult to display normal gradations.

In particular, when driving a display panel configured as shown in FIGS. 8 and 9, the liquid crystal cell 35 is equivalently divided into the drain-source capacitance of the TFT 31 and the gate capacitance. The capacitance is added and connected,
Since the parasitic capacitance is large, the influence of the data voltage becomes large, and even if a method of alternating the polarity of the data voltage as shown in Figure 7 is adopted, the effective value voltage changes and the display becomes uneven. There was a problem that occurred.

FIG. 11 is a diagram explaining the change in the effective value voltage mentioned above. When the data voltage consists of +Vs and -Vs as shown in (al), the display element voltage changes as shown in (bl). , and when the data voltage consists of +Vt and -yt after +VsO as shown in C1, the display element voltage is (
d). Here, Vs and Vt are the first
These are the saturation voltage and threshold voltage in the voltage-transmittance characteristics of the liquid crystal cell shown in Figure 2. The waveform (a) in Figure 11 is for the display when all lines are transmitted, and the waveform (bl is for the display when only the first line is transmitted). All remaining lines support non-transparent display.

Since the effective value V b (rms) in the above (b) is the square root of the time average of the square value of the voltage, wVs
−r+r −・(1). Note that n is the number of lines of the liquid crystal panel, τ.

The unit time r indicates the rate of change of the display element voltage with respect to the data voltage (r<1), and takes a relatively large value when the parasitic capacitance is large. Also, the effective value Vd(rm
s) is V d (rms) − 1 − τa (Vs−r−Vs−r−Vt)”*□ ·−(21).

Change in effective value ΔV c (rms) = (V b (
rms) -2VS, /1- r+ r x (V s - V t) (V s + V t)
---(It becomes 31.

It is an object of the present invention to suppress such fluctuations in the effective value voltage to enable desired gradation display.

[Means for solving problems]

The method for driving an active matrix display device of the present invention will be explained with reference to FIG. 1. A switching element 1 such as a TPT and a display element 5 such as a liquid crystal cell are placed on one glass substrate facing each other. One electrode and a scan canvas line 6 are formed, the control electrode 2 of the switching element 1 is connected to the scan canvas line 6, and the controlled electrodes 3 and 4 such as the drain and source are connected to one electrode of the display element 5. A striped data bus line 7 is formed on the other glass substrate as the other electrode of the display element 5, connected to the adjacent scan canvas line 6, and a display medium such as a liquid crystal is sandwiched between the glass substrates. In the active matrix type display device of the facing matrix type, data voltages Vdl, Vd2 .・・・
The address pulses Vg1 . Vg2. ... is a waveform consisting of a potential Vgon for turning on the switching element 1 to which the control electrode 2 is connected, and a potential Vgc just before that, and a potential Vgoff for turning on the switching element 1 to which the control electrode 2 is connected. The potential Vgc is selected to be an intermediate value between the voltages of the display level "0" and the display level "1" of the display element 5.

[Effect]

For example, if the data voltage applied to the data bus line 7 is of positive polarity at time T (2n-1) when an odd numbered line of the scan bus line 6 is scanned, then at a time T (2n-1) when an even numbered line is scanned.
In (2n), the data voltage applied to the data bus line 7 is set to negative polarity, and the address pulse applied to the scan bus line 6 is set to a waveform consisting of the potentials of Vgoff, Vgc, and Vgon, and the switching element 1 is turned on. A potential V gon is applied to the control electrode 2, and a potential Vgc is applied to the controlled electrode 4 of the switching element 1, and the potential Vgc is applied to the display level "0" of the display element 5.
(dark value) voltage Vt and display level “1” (saturation)
The value is selected to be between the voltage Vs and the voltage Vs. for example,
Address pulse V when positive data voltage is applied
The potential Vgc at gl is selected to be (Vs+Vt)/2, and the potential Vgc at address pulse Vg2 when a negative data voltage is applied is selected to be -(Vs+Vt)/2.

Also, data voltages Vdl, Vd2 . ... is the same value of +(Vs-V
t)/2 or -(Vs-Vt)/'l, and the potential Vgc applied to the controlled electrode 4 when a positive data voltage is applied is selected to be -(Vs+Vt)/2. ,
Further, the potential Vgc applied to the controlled electrode 4 when a data voltage of negative polarity is applied is selected to be (Vs+Vt)/2. Therefore, the difference between the potential of the data bus line 7 applied to one electrode of the display element 5 and the potential of the scan bus line 6 when the display level is "1" is Vs, and the voltage at the display level "1" is This will be applied to the display element 5.

Further, when a positive data voltage is applied at display level "0", the potential Vgc applied to the controlled electrode 4 is (V
s+Vt)/2, and when a negative data voltage is applied, the potential Vgc applied to the controlled electrode 4 is -(
V s +V t) / 2 is selected. Therefore, the difference between the potential of the data bus line 7 applied to the display element 5 and the potential of the scan canvas line 6 is Vt, and a voltage of display level "0" is applied to the display element 5.

With such a driving method, the fluctuation of the effective value voltage due to display data can be calculated by converting Vs in the above equation (3) to (Vs+Vt)/l.
::, Vt is replaced with -(Vs+Vt)/2, and the last term is O, so the fluctuation in the effective value voltage is also 0.

In the case of display levels other than display levels rlJ and rOJ, the fluctuation in the effective value voltage does not become zero, but since the amplitude of the data voltage is small, the voltage fluctuation can be suppressed to a low level.

That is, the data voltage applied to the data bus line 7 is
The same value can be set for the display levels "1" and "0", and the amplitude of the data voltage can be made small for other display levels as well. Thereby,
Fluctuations in the voltage held in the display element 5 can be reduced.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is an explanatory diagram of the operation of the embodiment of the present invention, in which (a) is the data voltage applied to the i-th data bus line;
+1. -1 is the data voltage of positive polarity and negative polarity display level "1", +0.5. −0.5 is a data voltage at a display level intermediate between positive and negative polarity display levels “0” and “1”, +0. -0 indicates a data voltage of display level "0" of positive polarity and negative polarity. Also, fbl is an address pulse applied to the j-th scan line, and (C) is j
+1 address pulse applied to the 100th scan canvas line; (d) is the potential of the display electrode of the display element at the intersection of the i-th data bus line and the j-th scan canvas line;
(e) shows the voltage of the display element having the display electrode.

The data voltage is set to display level "0" when the voltage at display level rOJ is Vt and the voltage at display level "1" is Vs.
The data voltage is the same as that of the display level "1", and the positive polarity is (Vs-Vt)/2 and the negative polarity is -(Vs-Vt)/
2, when a data voltage of positive polarity display level "1" is applied to the i-th data bus line, an address pulse with a potential of V gon is applied to the j-th scan bus line, and the j+1-th scan bus line Potential Vgc on the line
=-(Vs+Vt)/2 is applied. Therefore, the display element at the intersection of the i-th data bus line and the j-th scan bus line has ((Vs+Vt)/2)
A voltage of ((Vs-Vt)/2)=-Vs is applied, and (
As shown in e), it is held until the next frame.

At Bunmu time, when an address pulse with a potential of V gon is applied to the j+1st scan canvas line shown in (C), Vgc is applied to the j+2 scan canvas line.
A potential of = (V s +v t)/2 is applied.

Then, when a data voltage of display level "1" with negative polarity is applied to the i-th data bus line, the display element at the intersection of the i-th data bus line and the j+1-th scan canvas line is shown as [( Vs+Vt)/2) ((V
A voltage of s-Vt)/2)-Vs is applied.

In addition, the data voltage applied to the data bus line in the case of an intermediate display between display level "0" and display level "1" is (
The OV is between Vs-Vt)/2 and -(Vs-Vt)/2.

FIG. 3 is a block diagram of main parts of an embodiment of the present invention, and 11
1 or 8, 12 is a scan canvas line, 13 is a data bus line, 14a and 14b are data bus drivers, 15a,
15b is a scan canvas driver, 16a and 16b are shift registers, 17a and 17b are buffer amplifiers, and 18a
, 18b is a switching circuit for switching the voltage.

One line of display data is accumulated in each of the data bus drivers 14a and 14b, and the scan bus driver 15a
, 15b sequentially apply address pulses to the scan canvas line 12. Further, the voltage v1 is a voltage Vgon that turns on the switching element (not shown) of the display panel 11, and the voltage v2 is Vgc=(V s +V
t) / 2, voltage ■3 is Vgc = −(V s +
Vt) / 2 is selected and outputted from the switching circuits 18a and 18b by the switching signal, added to the buffer amplifiers 17a and 17b of the scan canvas drivers 15a and 15b, and selectively driven by the outputs of the shift registers 16a and 16b. Then, the voltages output from the switching circuits 18a, 18b are applied to the scan canvas line 12, and the unselected buffer amplifiers 17a, 17b output a voltage Vgoff that turns off the switching elements. Further, data voltage for one line is outputted from the data bus drivers 14a and 14b.

FIG. 4 is an explanatory diagram of the operation, where (al is a horizontal synchronizing signal, (
b) is the shift clock 5CK1, (C) is the shift clock 5CK2, (d) is the shift data 5Dle) is the address pulse output from the scan canvas driver 15a,
(d) is an address pulse output from the scan canvas driver 15b.

The shift clocks 5CKI and 5CK2 have a phase difference of H/2 when the horizontal period is H, and the shift data SD is sent to the shift registers 16a and 16b in synchronization with the vertical synchronization signal.
and shifted according to the shift clocks 5CKI and 5CK2, and correspondingly the buffer amplifiers 17a,
An address pulse is output from 17b.

At time to, voltage ■1 is switched and outputted by the switching circuit 18a, voltage v3 is switched and outputted by the switching circuit 18b, and the buffer amplifier 1 connected to the first scan canvas line 12 is switched by the output of the shift register 16a.
7a is driven, and when the buffer amplifier 17b connected to the second scan canvas line 12 is driven by the output of the shift register 16b, an address pulse of voltage V gon is applied to the first scan canvas line 12. , the second scan canvas line 12 adjacent to it
A voltage Vgc--(Vs+Vt)/2 is applied to. That is, (e), the waveform between t□ and t1 of (fl) is applied. Then, a positive data voltage is output from the data bus drivers 14a and 14b, and the data bus line 13
is applied to

At the next time t1, the switching circuit 18a causes the voltage
2 is switched and outputted, and voltage 1 is switched and outputted by the switching circuit 18b. The buffer amplifier 17a connected to the third scan line 12 is driven by the output of the shift register 16a, and the shift register 16a is driven by the output of the shift register 16a.
The buffer amplifier 17b connected to the second scan line 12 is continuously driven by the output of 2.
The address pulse of V gon is applied to the 3rd scan canvas line 12, and Vgc is applied to the 3rd scan canvas line 12.
A voltage of (V s + V t) / 2 is applied,
fed, (a waveform shown by a dotted line between t1 and t2 of fl is applied. Then, the data bus drivers 14a and 14b
A data voltage of negative polarity is outputted from and applied to the data bus line 13.

In the above-mentioned embodiment, the scanning direction is described as going from top to bottom, but if the scanning direction is from bottom to top, for example, the control electrode 2 of the switching element 1 in FIG.
It is sufficient if the connection relationship between the electrode 4 and the controlled electrode 4 is reversed.

〔Effect of the invention〕

As described above, in the active matrix display device of the facing matrix type, the present invention allows the data voltage to be applied to the data bus line 7 to be applied to the data bus line 7 for each scan of the scan bus line 6, such as for each horizontal scan line. Reverse the polarity,
Furthermore, when the potential Von for turning on the switching element 1 is applied to the control electrode 2, the potential Von applied to the controlled electrode 4
gc is selected to be an intermediate value between the voltages of display levels "1" and "0", so that the data voltage is
The display levels "1" and "0" can be set to the same value, and the amplitude of the data voltage applied to the data bus line 7 can be reduced to significantly reduce the influence on the display element voltage. Therefore, it is possible to reduce the change in the effective value of the display element voltage and enable desired gradation display. Furthermore, by reducing the amplitude of the data voltage, power consumption in the data bus driver can be reduced.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of the operation of an embodiment of the invention, Fig. 3 is a block diagram of main parts of an embodiment of the invention, and Fig. 4 is an embodiment of the embodiment of Fig. 3. FIG. 5 is an explanatory diagram of the display panel of the conventional example, FIG. 6 is an explanatory diagram of the operation of the conventional example, FIG. 7 is an explanatory diagram of the previously proposed driving method, and FIG. 8 is an explanatory diagram of the previously proposed driving method. An explanatory diagram of the proposed display panel, FIG. 9 is an exploded perspective view of the display panel of FIG. 8, and FIG. 10 is an exploded perspective view of the display panel of FIG.
FIG. 11 is an explanatory diagram of the operation of the display panel shown in the figure, FIG. 11 is an explanatory diagram of effective value fluctuation, and FIG. 12 is a voltage-transmittance characteristic curve diagram of a liquid crystal cell. 2 is a switching element, 2 is a control electrode, 3.4 is a controlled electrode, 5 is a display element, 6 is a scan canvas line, and 7 is a data bus line.

Claims (1)

[Claims] A switching element (1), one electrode of a display element (5), and a scan canvas line (6) are formed on one glass substrate arranged to face each other, and the switching element ( The control electrode (2) of 1) is connected to the scan canvas line (6).
), and the controlled electrodes (3, 4) are connected to a scan canvas line adjacent to the scan canvas line to which the one electrode and the control electrode (2) of the display element (5) are connected, A striped data bus line (7) is formed on the other glass substrate as the other electrode of the display element (5), and the active matrix type has a display medium sandwiched between the one and the other glass substrates. In the display device, the data voltage applied to the data bus line (7) is
The switching element (1) has a polarity reversed every time the scan canvas line (6) is scanned, and the control electrode (2) is connected to the scan canvas line (6).
) is applied to the scan canvas line (6) to which the controlled electrode (4) of the switching element (1) is connected, and the display level of the display element (5) is set to "1". A method for driving an active matrix display device, the method comprising: applying a potential (Vgc) selected to be an intermediate value between a voltage between "0" and a display level "0".